A hardening method for changing a trap contact area to increase single event performance of a cell

Abstract

The application discloses a reinforcing method for changing a trap contact area to increase a single event performance of a unit, comprising the following steps: 1) when phit bombardment is set, selecting parameters of each part of a device, selecting a bombardment position of incident particles, and setting a first mixed simulation circuit; 2) calculating and analyzing SET pulse width generated by different P trap contacts phit; 3) when nhit bombardment is set, selecting parameters of each part of the device, selecting the bombardment position of the incident particles, and setting a second mixed simulation circuit; 4) calculating and analyzing SET pulse width generated by different P trap contacts nhit; and 5) selecting an optimal P trap contact area in combination with a pulse width change curve. According to the method, the P trap contact area is changed under the condition that other parameters of the device remain unchanged, so that the single event transient effect is effectively reinforced, and the influence on the SET pulse width is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of radiation effect simulation, and in particular to a hardening method for increasing the single-particle resistance of a unit by changing the trap contact area. Background Technology

[0002] As circuit technology becomes increasingly integrated and spacecraft technology matures, spacecraft integrate diverse functions and have longer service lives. However, the natural radiation environment in space can cause serious space radiation effects on spacecraft. Among these, single-event effects account for a high proportion of failures and have become an important factor affecting spacecraft operation. Therefore, research on single-event effects and radiation hardening design is of great significance for improving the radiation resistance of integrated circuits.

[0003] Single-event effects (SEAs) are classified into soft errors and hard errors based on whether they cause irreversible damage to devices. Single-event transients (SETs) are a type of soft error, referring to transient currents propagating in mixed logic circuits and causing output errors. The SET pulse width characterizes the amount of charge collected at the impact node, the rate of charge accumulation, and the rate of charge removal from the impact node. Inverters, as a typical standard unit, can be used to accurately reflect the charge collection process by establishing a TCAD (Technology Computer Aided Design) simulation model to observe the physical process of SETs, saving significant experimental time and resources and accelerating research progress. Methods to mitigate SET pulse width include reducing the amount of charge collected during SET generation, which shortens the rising edge of the transient current forming the SET pulse and thus reduces its width. Layout hardening techniques typically utilize guard rings or different types of trap contacts to distribute electron-hole pairs generated on the incident particle track, effectively affecting the characteristics of the SET pulse, mitigating SEAs, and achieving a hardening effect.

[0004] The patent document with application number 201710001744.9, entitled "A Method for Strengthening Nanoscale CMOS Layout to Suppress Single-Particle Transients Using Rotating Transistors," describes a method that brings a PMOS transistor closer together by rotating it clockwise and an NMOS transistor counterclockwise. This moves the P-well and N-well contacts, reducing the spacing between the active regions, thereby enhancing the charge-sharing effect between the PMOS and NMOS transistors within the same logic gate and weakening the bipolar amplification effect generated after a particle incident on the PMOS transistor, thus reducing the single-particle transient pulse width. Its advantage lies in effectively reducing the impact of the bipolar emulation effect on the PMOS transistor. However, the NMOS transistor is not strengthened, and the drift and diffusion collection during charge collection have an increasingly severe impact on the SET pulse width as the process node decreases, which is also an important factor that cannot be ignored.

[0005] Patent application 201710001483.0, entitled "A Single-Event Transient Hardening Method for Bombarded NMOS Transistors without Area Overhead," describes a method that accelerates the release of particle-deposited charge in NMOS transistors by disconnecting substrate contacts and the metal connections between transistors, moving the active region of the NMOS transistor along the gate derivation direction and reducing the gate length accordingly, and then restoring the substrate contacts and the connections between transistors. This method reduces the single-event transient pulse width without increasing area overhead by changing the layout position. The problem is that although it reduces the SET pulse width, the reduction is relatively small, with a maximum reduction of 18.6%, and the overall single-event transient pulse width of the device remains high.

[0006] The paper "Study on Single-Event Transient Effects in 65nm Bulk Silicon NMOS" published by Liang Yongsheng et al. in *Electronic Science and Technology* referenced experimental data on anti-particle transient effects in 65nm bulk silicon CMOS. They constructed a TCAD model of a 65nm bulk silicon NMOS transistor and analyzed the resistance to single-event transient effects and the mechanism of the guard ring and guard drain structures by controlling variables. Simulation results showed that when single-event charge sharing occurs in two side-by-side NMOS devices, increasing the area of ​​the guard ring (well electrode) and reducing the distance between the guard ring and the source can enhance the charge collection capability of the source junction. The combined structure of the guard ring and guard drain can effectively reduce the total pulse width of the single-event transient effect caused by charge sharing. However, the guard ring and guard drain occupy a large amount of layout area, which increases the power consumption of the device to some extent.

[0007] Therefore, how to effectively reduce the impact on the SET pulse width has become an urgent problem for industry professionals. Summary of the Invention

[0008] As device feature sizes continue to decrease, single-event transient (SET) events become increasingly likely to occur. Traditional hardening techniques primarily target N-well contact layouts. However, at different process nodes, variations in the P-well contact area can significantly impact the SET pulse width. The purpose of this invention is to provide a hardening method that increases cell SET resistance by altering the well contact area, thus effectively reducing the impact on the SET pulse width.

[0009] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0010] This invention provides a method for hardening a unit cell by changing the well contact area to increase its resistance to single-particle interference, comprising the following steps:

[0011] 1) When setting up the phit bombardment, select the parameters of each part of the device, select the incident particle bombardment position, and set up the first hybrid simulation circuit;

[0012] 2) Calculate and analyze the SET pulse width generated by different P-well contact phit;

[0013] 3) When setting up n-hit bombardment, select the parameters of each part of the device, select the incident particle bombardment position, and set up the second hybrid simulation circuit;

[0014] 4) Calculate and analyze the SET pulse width generated by different P-well contact nhit;

[0015] 5) Select the optimal P-trap contact area by combining the pulse width variation curve.

[0016] Further, step 1) specifically includes:

[0017] The initial voltage of each electrode of the 40nm CMOS inverter is set to 1.1V. The bombardment position is selected as the center phit of the drain of the P-type active region. The P-well contact is grounded and the N-well contact is connected to VDD. The drain electrodes of the P-type and N-type active regions are used as output terminals. The source electrode of the P-type active region is connected to VDD and the gate is connected to the input Vin. The source electrode of the N-type active region is grounded. The input Vin of the inverter is set to 0V and VDD is set to 1.1V.

[0018] Further, step 2) specifically includes:

[0019] Based on the first hybrid simulation circuit established in step 1), the N-well contact area and shape remain unchanged; at the same time, the control variables are changed to change the P-well contact area, keeping its width unchanged, reducing the length of the P-well contact while keeping the number of device transistors, substrate contact width, and doping concentration unchanged; the P-well contact area is changed until the inflection point where the SET pulse width no longer changes.

[0020] Furthermore, step 3) specifically includes:

[0021] Set the voltages of each electrode, VDD, and the device operating voltage of the CMOS inverter. Select the center nhit of the drain of the N-type active region as the bombardment position. Ground the P-well contact and connect the N-well contact to VDD. Use the drain electrodes of the P-type and N-type active regions as output terminals. Connect the source electrode of the P-type active region to VDD and the gate to the input. Ground the source electrode of the N-type active region.

[0022] Furthermore, step 4) specifically includes:

[0023] Based on the second hybrid simulation circuit established in step 3), the N-well contact area and shape remain unchanged; at the same time, the control variables are changed to alter the P-well contact area, keeping its width unchanged and increasing the length of the P-well contact. The single-particle interference resistance is strengthened by increasing the P-well contact area, and the number of transistors, substrate contact width, and doping concentration of the device remain unchanged. The P-well contact area is then increased until the trend of SET pulse width variation disappears.

[0024] Furthermore, step 5) specifically includes:

[0025] Based on the simulation results of steps 2) and 4), the inflection point of the trend curve of P-well contact area versus SET pulse width was found.

[0026] When the inflection point occurs, the effect of P-well contact area on SET hardening decreases. At this point, considering the influence of layout area on device power consumption, a suitable P-well contact area is selected as the optimal area for hardening.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] This invention provides a method for hardening a unit by changing the well contact area to increase its resistance to single-event transients. By changing the P-well contact area while keeping other device parameters constant, the method effectively hardens the unit against single-event transients and reduces the impact on the SET pulse width.

[0029] 1. Unlike traditional reinforcement approaches, this invention selects to adjust the contact area of ​​the P-well, providing a new reinforcement approach from the perspective of layout process reinforcement.

[0030] 2. This invention strengthens the device from a layout process perspective by changing the well contact area, without occupying too much layout area and affecting device power consumption, but with a significant strengthening effect on single-event transient effects.

[0031] 3. This invention is based on TCAD simulation software, and the simulation results are accurate. It provides a reference for the single-event transient design of CMOS devices, thereby reducing the test cycle and test cost of device fabrication testing and subsequent radiation hardening treatment. Attached Figure Description

[0032] Figure 1 This is a flowchart of a hardening method for increasing the single-particle resistance of a unit by changing the trap contact area, as provided in an embodiment of the present invention.

[0033] Figure 2 This is a structural diagram of the TCAD simulation model provided in an embodiment of the present invention;

[0034] Figure 3This is a schematic diagram illustrating the effect of the P-well contact area on the SET pulse width under the n-hit condition provided in an embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram illustrating the effect of the P-well contact area on the SET pulse width under the phit condition provided in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram illustrating the trend of P-well contact pulse width variation in an embodiment of the present invention. Detailed Implementation

[0037] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0038] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front end," "rear end," "both ends," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] This invention uses TCAD Sentaurus 2018 to build a model for simulation research. TCAD simulation software is an internationally widely used semiconductor device simulation tool. Its main functions include Sentaurus Workbench (SWB) for creating self-contained simulation experimental projects, Sentaurus Device Editor (SDE) for building device structural models, Sentaurus Mesh (SNMESH) for doping devices, meshing, and adding various semiconductor technologies, and Sentaurus Device (SDEVICE) for testing the electrical performance of devices. It allows users to write test times, set heavy ion parameters, set device initial voltage bias, and other conditions as needed, and can perform hybrid simulations of the devices.

[0041] Referring to the circuit design process library model, characteristic parameters were extracted, and TCAD simulation software was used to construct a CMOS inverter by adjusting process parameters such as chamfer, light doping (LDD) concentration, and source / drain doping concentration, while adjusting heavy ion bombardment parameters.

[0042] Reference Figure 1 As shown, the present invention provides a method for increasing the single-particle resistance of a unit by changing the well contact area, comprising the following steps:

[0043] S1. When setting up phit bombardment, select the parameters of each part of the device, select the incident particle bombardment position, and set the first hybrid simulation circuit.

[0044] S2. Calculate and analyze the SET pulse width generated by different P-well contact phit;

[0045] S3. When setting up n-hit bombardment, select the parameters of each part of the device, select the incident particle bombardment position, and set the second hybrid simulation circuit.

[0046] S4. Calculate and analyze the SET pulse width generated by different P-well contacts nhit;

[0047] S5. Based on the pulse width variation curve, select the optimal P-trap contact area.

[0048] This invention provides a hardening method from a layout and process perspective to increase the single-event transient (SET) performance of cell units by changing the P-well contact area. The P-well contact area significantly affects the SET pulse width generated by SET based on the device's input state. When the device input voltage is low, increasing the P-well contact area can effectively reduce the SET pulse width; when the device input voltage is high, increasing the P-well contact area will significantly increase the SET pulse width. Therefore, to achieve a hardening effect, the P-well contact area should be minimized as much as possible. Considering both situations, when hardening inverters from a layout and process perspective, a comprehensive trade-off must be made based on the actual situation. This hardening method is used to study the SET effect generated by heavy ion bombardment of CMOS inverters and is suitable for testing and research related to SET performance evaluation. By changing the P-well contact area while keeping other device parameters constant, it effectively hardens the inverter against SET and effectively reduces its impact on the SET pulse width.

[0049] The following is a detailed explanation of each of the above steps:

[0050] Step 1: As Figure 2The diagram shows the TCAD model structure of a 40nm process node CMOS inverter (a) and a two-dimensional structure diagram (b), with the doping concentration reference shown. To set the initial voltage of each electrode of the 40nm CMOS inverter to 1.1V, the bombardment location is selected as the center phit of the P-type active region drain. The P-well contact is grounded, the N-well contact is connected to VDD, the P-type and N-type active region drain electrodes are used as output terminals, the P-type active region source electrode is connected to VDD, the gate electrode is connected to the input Vin, the N-type active region source electrode is grounded, and the inverter input Vin is set to 0V and VDD is set to 1.1V.

[0051] Step Two: Based on the model established in Step One, keep the N-well contact area and shape unchanged, while controlling the variables to change the P-well contact area. Keep its width constant, but reduce the length of the P-well contact while maintaining the same number of transistors, substrate contact width, and doping concentration. In this example, the P-well contact length is reduced from 1750nm to 500nm. At this point, the increase in P-well contact area no longer significantly amplifies the SET pulse width, and the P-well contact area accounts for 3.5% of the P-well area. Figure 3 As shown, the effect of the P-well contact area on the SET pulse width is given by the n-hit condition. The horizontal axis represents time in ps (picoseconds), and the vertical axis represents voltage in V.

[0052] Step 3: Set the initial voltage of each electrode of the 40nm CMOS inverter to 0V. Select the N-type active region drain center nhit as the bombardment position. Ground the P-well contact and connect the N-well contact to VDD. Use the P-type active region drain electrode and the N-type active region drain electrode as the output terminals. Connect the P-type active region source electrode to VDD. Connect the gate to the input Vin. Ground the N-type active region source electrode. Set the inverter input Vin to 0V and VDD to 1.1V.

[0053] Step Four: Based on the model established in Step Three, keep the N-well contact area and shape unchanged, while controlling the variables to change the P-well contact area. Keep its width constant, increase the length of the P-well contact. This increases the P-well contact area to harden the single-event immunity, while maintaining the number of transistors, substrate contact width, and doping concentration. Continue increasing the P-well contact area until the SET pulse width variation trend disappears. In this invention, the P-well contact length increases from 500 nm to 1750 nm. At this point, the increase in P-well contact area no longer significantly affects the mitigation of the SET pulse width, and the P-well contact area accounts for 3.5% of the P-well area. Figure 4As shown, the effect of the P-well contact area on the SET pulse width under the phit condition is illustrated. The horizontal axis represents time in ps (picoseconds), and the vertical axis represents voltage in V.

[0054] Step 5: Based on the simulation results from Steps 2 and 4, such as... Figure 5 As shown, in the PHIT case, the larger the P-well contact area, the larger the SET pulse width. Therefore, the P-well contact area should be minimized while ensuring normal device function. In the NHIT case, increasing the P-well contact area significantly reduces the SET pulse width. When the P-well contact length increases from 500nm to 750nm, the SET pulse width decreases from 1405ns to 418ns, a reduction of 70.2%. The decreasing trend then gradually slows down. When the P-well contact length increases from 1500nm to 1750nm, the SET pulse width decreases from 154ns to 142ns, a reduction of only 0.85%. It can be considered that the influence curve of the P-well contact area on the SET pulse width reaches an inflection point at this point. Therefore, a P-well contact with a length of 1750nm and a width of 300nm is the most suitable hardening method.

[0055] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for hardening a unit by changing the trap contact area to increase its resistance to single-particle interference, characterized in that, Includes the following steps: 1) When setting up phit bombardment, ground the P-well contact and connect the N-well contact to VDD; select the parameters of each part of the device, select the incident particle bombardment position, and set up the first hybrid simulation circuit. 2) Calculate and analyze the SET pulse width generated by different P-well contact phit; 3) When setting up n-hit bombardment, select the parameters of each part of the device, select the incident particle bombardment position, and set up the second hybrid simulation circuit; 4) Calculate and analyze the SET pulse width generated by different P-well contact nhit; 5) Select the optimal P-trap contact area based on the pulse width variation curve; Specifically, step 2) includes: Based on the first hybrid simulation circuit established in step 1), the N-well contact area and shape are kept unchanged; at the same time, the control variables are changed to change the P-well contact area, keeping its width unchanged, while reducing the length of the P-well contact and keeping the number of device transistors, substrate contact width, and doping concentration unchanged; the P-well contact area is changed until the inflection point where the SET pulse width no longer changes. Step 4) specifically includes: Based on the second hybrid simulation circuit established in step 3), the N-well contact area and shape remain unchanged; at the same time, the control variables are changed to alter the P-well contact area, keeping its width unchanged and increasing the length of the P-well contact. The single-particle interference resistance is strengthened by increasing the P-well contact area, and the number of transistors, substrate contact width, and doping concentration of the device remain unchanged. The P-well contact area is then increased until the trend of SET pulse width variation disappears.

2. The method for hardening a unit by changing the trap contact area to increase its resistance to single-particle interference, as described in claim 1, is characterized in that... Step 1) specifically includes: The initial voltage of each electrode of the 40nm CMOS inverter is set to 1.1V. The bombardment position is selected as the center phit of the drain of the P-type active region. The drain electrodes of the P-type active region and the drain electrodes of the N-type active region are used as output terminals. The source electrode of the P-type active region is connected to VDD, the gate is connected to the input Vin, the source electrode of the N-type active region is grounded, the input Vin of the inverter is set to 0V, and VDD is set to 1.1V.

3. The method for hardening a unit by changing the trap contact area to increase its resistance to single-particle interference, as described in claim 2, is characterized in that... Step 3) specifically includes: Set the voltages of each electrode, VDD, and the device operating voltage of the CMOS inverter. Select the center nhit of the drain of the N-type active region as the bombardment position. Ground the P-well contact and connect the N-well contact to VDD. Use the drain electrodes of the P-type and N-type active regions as output terminals. Connect the source electrode of the P-type active region to VDD and the gate to the input. Ground the source electrode of the N-type active region.

4. The method for hardening a unit by changing the trap contact area to increase its resistance to single-particle interference, as described in claim 3, is characterized in that... Step 5) specifically includes: Based on the simulation results of steps 2) and 4), the inflection point of the trend curve of P-well contact area versus SET pulse width was found. When the inflection point occurs, the effect of P-well contact area on SET hardening decreases. At this point, considering the influence of layout area on device power consumption, a suitable P-well contact area is selected as the optimal area for hardening.

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