A field-effect transistor based on germanium selenide two-dimensional material and its application

Abstract

The present invention relates to a field effect transistor based on germanium selenide two-dimensional material and its application, which includes a substrate, a first isolation layer, a germanium selenide channel, a second isolation layer, a single gate structure, and a source / drain adjacent to the single gate structure, stacked in sequence from bottom to top. The advantages of the present invention are that the field effect transistor is small in volume and has a neat structure; and germanium selenide is used as the channel, which can achieve switching current and subthreshold swing that meet the HP application standard, thereby improving the performance of the field effect transistor.

Description

Technical Field

[0001] The present invention relates to the technical field of field effect transistors, and particularly to a field effect transistor based on germanium selenide two-dimensional material and its application. Background Art

[0002] A field effect transistor is a semiconductor device that uses the electric field effect of a control input circuit to control an output circuit. With the continuous development of electronic information technology, there are requirements for lower energy consumption, smaller size, and higher integration of electronic devices. However, for nearly fifty years, the size of FETs has been shrinking. Nowadays, the feature sizes of MOS-type field effect transistors and other multi-gate transistors have reached 5 nanometers, and the reduction process is extremely difficult, and it is almost impossible to further reduce the size. Moreover, further scaling will lead to practical problems such as short channel effects (SCE). One of the solutions is to develop FETs by exploring new channel materials with high bandgaps to overcome the physical size limitations of silicon-based chips.

[0003] As the earliest discovered two-dimensional nanomaterial, since graphene emerged in 2004, with its unique physical and chemical properties, it has great application potential in the field of nano-optoelectronics, attracting a large amount of attention and research. However, its natural zero-bandgap structure limits its extensive practical applications in the field of nanoelectronics. In recent years, germanium selenide materials have attracted people's attention. It has a unique structure and exhibits excellent optoelectronic properties, so it has become an alternative to graphene two-dimensional materials. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a field effect transistor based on germanium selenide two-dimensional material and its application. The field effect transistor is small in volume and has a neat structure; and uses germanium selenide as the channel, which can achieve switching current and subthreshold swing that meet the HP application standard, thereby improving the performance of the field effect transistor.

[0005] The present invention is achieved through the following technical solutions: On the one hand, a field effect transistor based on germanium selenide two-dimensional material is provided, which includes a substrate, a first isolation layer, a germanium selenide channel, a second isolation layer, a single gate structure, and a source / drain adjacent to the single gate structure, stacked in sequence from bottom to top.

[0006] Through the above technical solutions, the present invention can not only regulate the source-drain current through the dielectric layer material and gate voltage, but also regulate the source-drain by changing the doping concentration of the silicene substrate, thereby greatly improving the regulation ability of the field effect transistor. Among them, the first isolation layer and the second isolation layer are an oxide layer and a vacuum layer, preferably a vacuum layer; the obtained field effect transistor is small in volume and has a neat structure; and uses germanium selenide as the channel, which can achieve switching current and subthreshold swing that meet the HP application standard, thereby improving the performance of the field effect transistor.

[0007] Furthermore, the substrate is prepared from two-dimensional honeycomb silicene, and the silicene has a warped single-layer hexagonal ring structure.

[0008] Furthermore, the first isolation layer is an oxide layer or a vacuum layer; the second isolation layer is an oxide layer or a vacuum layer.

[0009] Through the above technical solutions, both the oxide layer and the vacuum layer can be used to prevent the germanium selenide channel from interacting with the single-gate structure and the substrate.

[0010] Furthermore, the thickness of the oxide layer is 10 - 70 nm.

[0011] Through the above technical solutions, a silicene substrate layer is grown under the germanium selenide channel using a vacuum pumping technique. The channel material and the substrate material layer have different materials, and a Schottky contact is formed between the channel material layer and the substrate material layer.

[0012] Furthermore, the germanium selenide channel is made of N-type doped or P-type doped germanium selenide.

[0013] Through the above technical solutions, a 10-nm germanium selenide P-type or N-type heavily doped region is grown on the germanium selenide epitaxial layer using vertical hot-wall chemical vapor deposition (CVD); a 10-nm silicene P-type or N-type heavily doped region is grown on the silicene epitaxial layer using vertical hot-wall chemical vapor deposition (CVD).

[0014] Furthermore, the single-gate structure is stacked by an insulating dielectric layer and a metal layer.

[0015] Through the above technical solutions, a gate electrode is fabricated using photolithography and metal evaporation techniques; the substrate used includes a metal layer and an insulating dielectric layer; first, 601 positive photoresist is spin-coated onto the insulating dielectric layer 1 for 60 s at a spin speed of 4000 revolutions per minute; then, through photolithography and development, an electrode pattern mask is formed on the insulating dielectric layer 1, where the developer used is tetramethylammonium hydroxide and the development time is 15 s. Finally, a metal layer with a thickness of 10 nm is sequentially evaporated using an electron beam evaporation machine, and then acetone is used for soaking and washing to remove the photoresist and the metal layer outside the electrode region, obtaining a metal electrode.

[0016] Furthermore, the material of the insulating dielectric layer is any one of SiO 2 , SiC, SiN, HfO 2 , TiO 2 .

[0017] Furthermore, the metal used for the gate electrode, source electrode, and drain electrode is one or two of Au, Cu, Ni, Ti, Cr, Ag.

[0018] Further, the source / drain includes silicon germanium and germanium selenide, the Ge concentration in the germanium selenide is 23% to 27%, and the Si concentration in the silicon germanium is 17% to 24%.

[0019] On the other hand, an application of the above field effect transistor based on germanium selenide two-dimensional material is provided.

[0020] Through the above technical solution, due to the short-channel effect and Moore's law approaching the physical limit, it is almost impossible for silicon transistors with a gate length reduced to less than 10 nanometers to achieve the goals of the International Technology Roadmap for Semiconductors (ITRS), and this field effect transistor has multiple advantages such as small size and fast response. It can meet the requirements of ITRS for HP and low power consumption (LP).

[0021] The beneficial effects of the present invention are as follows: The present invention can not only regulate the source-drain current through the dielectric layer material and gate voltage, but also regulate the source-drain by changing the doping concentration of the silicene substrate, thereby greatly improving the regulation ability of the field effect transistor.

[0022] Through the discovery of changing the gate dielectric layer material in the present invention, different subthreshold swings and on-state currents can be obtained for different dielectric layers. Among them, different dielectric layers have different relative dielectric constants. As the dielectric constant increases, the influence of the dielectric layer on the device performance gradually increases. For example, when using SiO 2 、Al 2 O 3 and HfO 2 as substrates, both ions and SS gradually improve as the relative dielectric constant decreases. When the substrate is Al 2 O 3 , the ions increase from 786 μA / μm to 1206 μA / μm, and the SS value decreases from 134.2 mV / dec to 123.4 mV / dec.

[0023] The present invention regulates the output characteristic curve through the gate voltage. When a positive bias voltage is applied, as the gate voltage increases, the source-drain electrode decreases and saturates at a smaller source-drain voltage; when a negative gate voltage is applied, the saturation current increases.

[0024] The present invention is regulated by doping the silicene substrate in the source-drain region, and the optimal doping concentration is 1×10 13 cm -2 . BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of the field effect transistor embodying the present invention;

[0026] Figure 2 is a schematic structural diagram of the source / drain of the field effect transistor embodying the present invention;

[0027] Figure 3 Output characteristic curves of field effect transistors under different gate voltages.

[0028] Among them, 1 - metal layer; 2 - insulating dielectric layer; 3 - germanium selenide channel; 4 - silicene substrate; 5 - source electrode; 6 - drain electrode. Specific implementation manner

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the embodiments of the invention and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0030] Embodiment 1

[0031] A field effect transistor based on germanium selenide two-dimensional material, as Figure 1 and Figure 2 shown, includes a substrate, a first isolation layer, a germanium selenide channel, a second isolation layer, a single gate structure, and a source / drain adjacent to the single gate structure, which are stacked in sequence from bottom to top; wherein the single gate structure is formed by stacking an insulating dielectric layer and a gate electrode; the specific manufacturing method of the field effect transistor of the germanium selenide two-dimensional material is as follows:

[0032] Step 1: Fabricate the gate electrode using photolithography and metal evaporation techniques; the substrate used includes a metal layer and an insulating dielectric layer; first, spin-coat 601 positive photoresist onto the insulating dielectric layer 1 for 60 s at a spin-coating speed of 4000 revolutions per minute.

[0033] After that, through photolithography and development, an electrode pattern mask is made on the insulating dielectric layer 1, and the developer used is tetramethylammonium hydroxide with a development time of 15 s.

[0034] Finally, use an electron beam evaporation coater to evaporate a metal layer with a thickness of 10 nm in sequence, and then perform a bubble wash with acetone to remove the photoresist and the metal layer outside the electrode area to obtain a metal electrode.

[0035] Step 2: Prepare a germanium selenide layer under the gate electrode through a vacuum pumping technique; first, grow germanium selenide material under the gate electrode through a vacuum pumping technique to prepare the channel material.

[0036] Then, through the low-temperature chemical vapor deposition technique, the germanium selenide layer is prepared under the gate, and the germanium selenide layer is prepared on the gate layer by thermal oxidation; then, a vacuum pumping technique is used to grow a silicene substrate layer under the germanium selenide channel; based on the different materials of the channel material layer and the substrate material layer, a Schottky contact is formed between the channel material layer and the substrate material layer.

[0037] Specifically, the substrate is made of two-dimensional honeycomb silicene, and the silicene has a warped single-layer hexagonal ring structure; a high-resistivity epitaxial layer is grown on a silicon substrate with extremely low resistance, and the device is fabricated on the epitaxial layer. In this way, the high-resistivity epitaxial layer ensures a high breakdown voltage for the tube, while the low-resistance substrate reduces the resistance of the substrate, thereby reducing the saturation voltage drop.

[0038] Furthermore, the germanium selenide channel is made of N-type doped and P-type doped germanium selenide. Using the vertical hot-wall chemical vapor deposition method CVD, a 10-nm germanium selenide P-type or N-type heavily doped region is grown on the germanium selenide epitaxial layer; using the vertical hot-wall chemical vapor deposition method CVD, a 10-nm silicene P-type or N-type heavily doped region is grown on the silicene epitaxial layer.

[0039] Furthermore, the single-gate structure is stacked by an insulating dielectric layer and a gate electrode. First, the gate electrode is fabricated using photolithography and metal evaporation techniques. This substrate includes a metal layer and an insulating dielectric layer. First, the 601 positive photoresist is spin-coated onto the insulating dielectric layer 1 for 60 s at a spin-coating speed of 4000 revolutions per minute. After that, through photolithography and development, an electrode pattern mask is made on the insulating dielectric layer 1, and the developer used is tetramethylammonium hydroxide with a development time of 15 s. Finally, using an electron beam evaporation coater, a metal layer with a thickness of 10 nm is evaporated in sequence, and then acetone is used for soaking and washing to remove the photoresist and the metal layer outside the electrode area, obtaining the metal electrode.

[0040] Furthermore, the material of the insulating dielectric layer is SiO 2 , SiC, SiN, HfO 2 , TiO 2 any one of them.

[0041] Furthermore, the metal used for the gate electrode, source electrode, and drain electrode is one or two of Au, Cu, Ni, Ti, Cr, Ag.

[0042] Furthermore, the source / drain contains silicon germanium and germanium selenide, and the Ge concentration in germanium selenide is 23% - 27%, and the Si concentration in silicon germanium is 17% - 24%.

[0043] In this embodiment, the germanium selenide channel 3 is prepared from the two-dimensional material germanium selenide. Germanium selenide has good optical, electrical, mechanical, and thermal properties, and using it as the channel of the field-effect transistor improves the performance.

[0044] In this embodiment, using N-doped and P-doped germanium selenide as the channel in a double-gate field-effect transistor can achieve a switching current and subthreshold swing that meet the HP application standard, thereby improving the performance of the field-effect transistor.

[0045] In this embodiment, the silicene substrate 4 is prepared from the two-dimensional material silicene. Silicene has advantages such as a moderate bandgap, good stability, environmental friendliness, and low cost, and is often selected as the material basis for the semiconductor industry.

[0046] In this embodiment, the first isolation layer is an oxide layer or a vacuum layer; the second isolation layer is an oxide layer or a vacuum layer; specifically, the insulating layer 2 and the germanium selenide channel 3 are isolated by a vacuum layer / oxide layer, and the germanium selenide channel 3 and the silicene substrate 4 are isolated by a vacuum layer / oxide layer; preferably, the thickness of the oxide layer is 10 - 70 nm. Moreover, both the oxide layer and the vacuum layer can be used to prevent the germanium selenide channel from interacting with the single-gate structure and the substrate.

[0047] As Figure 3 shown, the output characteristic curve is regulated by the gate voltage. When a positive bias voltage is applied, as the gate voltage increases, the source-drain electrodes decrease and saturate at a smaller source-drain voltage. When a negative gate voltage is applied, the saturation current increases. Regulation is carried out by doping the silicene substrate in the source-drain region, and the optimal doping concentration is 1×10 13 cm -2 .

[0048] On the other hand, an application of the above-mentioned field-effect transistor based on germanium selenide two-dimensional material in the optoelectronic field is provided. Due to the short-channel effect and Moore's Law approaching the physical limit, it is almost impossible for silicon transistors with a gate length reduced to less than 10 nanometers to meet the goals of the International Technology Roadmap for Semiconductors (ITRS). And this field-effect transistor has multiple advantages such as small volume and fast response, and can meet the requirements of ITRS for HP and low power consumption (LP).

[0049] In summary, the present invention can not only regulate the source-drain current through the electron concentration in the channel and the gate voltage, but also regulate the source-drain by changing the doping concentration of the silicene substrate 4, thereby greatly improving the regulation ability of the field-effect transistor.

[0050] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A field effect transistor based on germanium selenide two-dimensional material, characterized in that, it includes a substrate, a first isolation layer, a germanium selenide channel, a second isolation layer, a single gate structure, and a source / drain adjacent to the single gate structure, which are stacked in sequence from bottom to top; wherein, the substrate is prepared from two-dimensional honeycomb silicene, and the silicene has a warped single-layer hexagonal ring structure; the germanium selenide channel is made of N-type doped or P-type doped germanium selenide, that is, a 10-nm germanium selenide P-type or N-type heavily doped region is grown on the germanium selenide epitaxial layer by vertical hot-wall chemical vapor deposition (CVD); a 10-nm silicene P-type or N-type heavily doped region is grown on the silicene epitaxial layer by vertical hot-wall chemical vapor deposition (CVD); the substrate and the germanium selenide channel form a Schottky contact; The single-gate structure is formed by stacking an insulating dielectric layer and a gate electrode; the insulating dielectric layer is made of any one of SiO 2 , SiC, SiN, HfO 2 , TiO 2 . The metal used for the gate electrode, source electrode, and drain electrode is one or two of Au, Cu, Ni, Ti, Cr, and Ag; the source / drain contains silicon germanium and germanium selenide, the Ge concentration in the germanium selenide is 23% to 27%, and the Si concentration in the silicon germanium is 17% to 24%; the doping concentration of the silicene substrate in the source-drain region is 1×10 13 cm -2 .

2. The field effect transistor based on germanium selenide two-dimensional material according to claim 1, characterized in that, the first isolation layer is an oxide layer or a vacuum layer; the second isolation layer is an oxide layer or a vacuum layer.

3. The field effect transistor based on germanium selenide two-dimensional material according to claim 2, characterized in that, the thickness of the oxide layer is 10 - 70 nm.

4. Application of the field effect transistor based on germanium selenide two-dimensional material according to any one of claims 1 - 3 in the optoelectronic field.

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