Video data encoding method and apparatus

Abstract

Various schemes related to video coding parallelization techniques are described. An apparatus receives video data. The apparatus then calculates a plurality of figures of merit (FOMs), each FOM representing how much quality a particular coding tool can achieve when encoding the video data. The apparatus also determines coding tools that can be suitable for encoding the video data by comparing the FOMs. In determining the coding tools, the apparatus utilizes a time interleaving technique to process the video data in parallel. The video data can include an array of coding blocks, and the apparatus can receive the video data using a snake processing order to scan the array of coding blocks.

Description

[0001] CROSS-REFERENCE

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 290,073, filed December 16, 2021, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to video coding, and more particularly, to methods and apparatus for efficient video coding with parallelization techniques. BACKGROUND

[0004] Unless otherwise stated in this document, the methods described in this section are not prior art to the claims listed below and are not admitted to be prior art by virtue of their inclusion in this section.

[0005] Video coding generally involves encoding a video (i.e., an original video) into a bitstream by an encoder, transmitting the bitstream to a decoder, and parsing and processing the bitstream by the decoder to produce a reconstructed bitstream. The encoder can employ various encoding modes or tools when encoding the video, one of the purposes of which is to reduce the total size of the bitstream that needs to be transmitted to the decoder, while still providing the decoder with enough information about the original video so that the decoder can generate a reconstructed video that is very faithful to the original video. For example, in the final version of the most advanced video coding standard, Versatile Video Coding (VVC) standard, released in 2020, where various encoding tools are newly defined to achieve about 40% coding gain (e.g., Bjontegaard Delta-Rate gain) compared to the previous generation of video coding standard, i.e., High Efficiency Video Coding (HEVC) standard, a video coding specification since 2013. With the new encoding tools provided by VVC, high performance video coding becomes possible, supporting new video use cases, such as field-of-view related 360° video streaming, advanced features such as region random access, signal-to-noise ratio scalability, etc.

[0006] For example, the VVC standard includes new coding tools related to intra prediction, such as matrix-based intra prediction (MIP), chroma separation tree (CST), intra sub-partition (ISP), and intra block copy (IBM). New coding tools related to inter prediction, such as adaptive motion vector resolution (AMVR), motion vector difference merge mode (MMVD), combined inter / intra prediction (CIIP), and geometric partitioning (GPM) are also included in VVC. New tools applicable to both intra and inter prediction are also included in VVC, such as sample adaptive offset (SAO), adaptive loop filter (ALF), cross-component adaptive loop filter (CCALF), and joint chrominance coding (JCCR). In addition, new tools related to encoder block partitioning are also included in VVC, such as ternary tree partitioning (TT), binary tree ternary tree partitioning (BT_TT), larger maximum coding tree unit size of 64 pixels x 64 pixels (CTU64), and larger maximum transform unit size of 32 pixels x 32 pixels (TU32). Other newly developed video coding standards also follow similar trends of VVC, including more coding tools to achieve better coding performance.

[0007] Thus, the coding tools that need to be used by an encoder will depend on which video coding standard the encoder is designed to support. As video coding standards continue to evolve, more and more coding tools are defined in the standards, and thus it is desirable for a general-purpose video encoder to be able to implement various coding tools. It is therefore important for the encoder to quickly determine, for each picture or a portion thereof to be encoded, the preferred or otherwise suitable coding tools to be applied to the direct video data to be encoded in order to achieve the desired video quality at a reasonable encoding cost. SUMMARY

[0008] The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce some of the novel and non-obvious aspects of the technology described herein. The selected implementation further described in the following detailed description. Accordingly, the following summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in determining the scope of the claimed subject matter.

[0009] It is an object of the present disclosure to provide schemes, concepts, designs, techniques, methods, and apparatuses related to video coding with parallelization techniques. It is believed that with various embodiments in the present disclosure, benefits including improved encoding latency, simplified search memory access, and / or reduced hardware overhead are achieved.

[0010] In one aspect, a method of encoding video data using a preferred coding tool is presented. The method can involve receiving the video data by a plurality of processing elements (PEs), each PE configured to perform a coding efficiency evaluation for a respective coding tool to evaluate when performing the coding efficiency evaluation. In some embodiments, each PE can be a low complexity rate-distortion optimizer (LC-RDO). The method can then involve calculating, by each of the plurality of PEs performing the coding efficiency evaluation, a respective figure of merit (FOM) specific to the respective coding tool and the video data. In some embodiments, the FOM can be a sum of squared differences (SSD), a sum of absolute differences (SAD), or a sum of absolute transformed differences (SATD). The method can also include determining the coding tool specific to the video data by comparing the FOMs calculated by the plurality of PEs. In some embodiments, the method can also involve determining a set of parameter settings related to the determined coding tool. Finally, the method can encode the video data using the determined coding tool and parameter settings.

[0011] In some embodiments, the video data can be a coding block (CB) that is divided into a plurality of sub-blocks forming an array of columns and rows. Each PE can receive a plurality of sub-blocks consecutively at a time when receiving the video data. The number of sub-blocks received by each PE at a time can be the same as the number of PEs involved, i.e., the number of coding tools to be evaluated. In some embodiments, the PEs can use a zigzag processing order to receive and process the video data to process by columns or rows.

[0012] In some embodiments, the sub-blocks can be stored in a cache memory having a plurality of banks. The banks can be divided into two groups, where each group can have as many banks as the number of PEs. In the case where the PEs receive the sub-blocks by column-wise zigzag or raster scan, any two columns of adjacent sub-blocks are stored in the two groups of banks, respectively. In the case where the PEs receive the sub-blocks by row-wise zigzag scan or raster scan, any two rows of adjacent sub-blocks are stored in the two groups of banks, respectively.

[0013] In another aspect, an apparatus is presented that includes a cache memory, a processor, a plurality of processing elements (PEs), and a comparator. The processor is configured to store video data in the cache memory according to a bank allocation scheme specific to the video data, where the bank allocation scheme is determined by the processor based on various factors such as the size of a coding block of the video data, the size of a sub-block of the video data, the number of PEs running simultaneously in a time-interleaved manner, the scan order (e.g., raster scan or zigzag scan) used to process the sub-block of the video data, etc. Each PE is configured to apply a respective coding mode or coding tool to the video data and subsequently determine its coding efficiency by calculating a figure of merit (FOM), such as sum of squared difference (SSD), sum of absolute difference (SAD), or sum of absolute transformed difference (SATD). The comparator is used to compare the FOMs calculated by the PEs to determine the coding tool. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. It is noted that the drawings are not necessarily drawn to scale, as some components can be shown disproportionately to clearly illustrate the concepts of the present disclosure.

[0015] FIG. 1 is a diagram of an example design in accordance with an embodiment of the present disclosure.

[0016] FIG. 2 is a diagram of an example design in accordance with an embodiment of the present disclosure.

[0017] FIG. 3 is a diagram of an example design in accordance with an embodiment of the present disclosure.

[0018] FIG. 4 is a diagram of an example design in accordance with an embodiment of the present disclosure.

[0019] FIG. 5 is a diagram of an example design in accordance with an embodiment of the present disclosure.

[0020] FIG. 6 is a diagram of an example coding efficiency evaluation apparatus in accordance with an embodiment of the present disclosure.

[0021] FIG. 7 is a flowchart of an example process in accordance with an embodiment of the present disclosure.

[0022] FIG. 8 is a diagram of an example electronic system in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Detailed embodiments and implementations of the claimed subject matter are disclosed herein. It should be understood, however, that the disclosed embodiments and implementations are merely illustrative of the claimed subject matter that can be embodied in various forms. The disclosure, however, can be embodied in many different forms and should not be construed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art. In the following description, details of well-known features and techniques can be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

[0024] Implementations in accordance with the present disclosure relate to various techniques, methods, schemes, and / or solutions related to efficient parallelized video encoding and search memory access. In accordance with the present disclosure, a variety of possible schemes can be implemented individually or in combination. That is, while these possible solutions can be described individually below, two or more of these possible solutions can be implemented in one or another combination.

[0025] I. Parallel encoding tool evaluation

[0026] As described elsewhere above, it is important for an encoder (i.e., a video encoder) to quickly determine which encoding tool is suitable for encoding the on-the-fly video data. The encoder will thus encode the video data using the determined encoding tool rather than other encoding modes that the encoder is also capable of performing. The encoder can determine that a certain encoding tool is the most suitable according to various factors, such as particular attributes of the video to be encoded, particular characteristics of the encoded bitstream, etc. Moreover, different portions of the video data can be encoded using different encoding tools or modes. For example, each frame of a video can be divided into non-overlapping blocks, sometimes referred to as coding blocks (CBs), and each frame can be divided into multiple slices, each slice having a related group of non-overlapping blocks. The video data can be encoded in a manner where each slice (i.e., its coding blocks) is encoded with a respective encoding tool.

[0027] To determine the encoding tool (i.e., the most suitable encoding tool for encoding the on-the-fly video data or a slice thereof), the encoder can need to evaluate a number of candidate encoding tools using data of at least a portion of the on-the-fly video to be encoded. In order to quickly determine the encoding tool, the purpose of the evaluation process is not to obtain fine (i.e., highly accurate) encoding results, but rather to obtain coarse (i.e., less accurate) results for each candidate encoding tool in a timely manner so that the results can be compared and the encoding tool determined therefrom. The encoder will then use the determined encoding tool to encode the on-the-fly video data. This evaluation process can be interchangeably referred to as a "coding tool evaluation process" or a "coding efficiency evaluation process" hereinafter.

[0028] Notably, the determined coding tools are generally dependent on the video data to be encoded. This is because a coding tool that is suitable for encoding a certain type of video data can not be equally suitable for encoding other types of video data. For example, different coding tools can be determined when encoding video data that mainly contains natural images versus video data that mainly contains screen content.

[0029] To timely evaluate multiple candidate coding tools, the encoder can employ parallelization for the evaluation process. That is, two or more processing elements (PEs) operate concurrently, each PE evaluating the performance (e.g., coding efficiency) of a respective candidate coding tool. FIG. 1 is a diagram of an example design according to an embodiment of the present disclosure, in which a parallel coding tool evaluation scheme 100 is presented. In scheme 100, parallelization is implemented by four concurrently operating processing units (PEs), namely PE 130, 131, 132, and 133. Each of PE 130-133 is configured to evaluate the coding efficiency of a respective coding tool applied to video data stored in search memory 110. For example, PE 130 is configured to perform a coding efficiency evaluation on coding tool T0, and PE 131 is configured to perform a coding efficiency evaluation on coding tool T1. Meanwhile, PE 132 and PE 133 are configured to perform coding efficiency evaluations on coding tools T2 and T3, respectively. Each of coding tools T0, T1, T2, and T3 can be one of the coding tools defined in VVC, HEVC, or other video coding standards, such as the VVC coding tools described elsewhere herein.

[0030] As noted above, the PEs 130-133 are intended to evaluate the efficiency of the coding tools in a timely manner. Thus, simple evaluation algorithms involving low complexity hardware and / or software modules are typically used to implement the PEs. For example, each of the PEs 130-133 can be a low-complexity rate-distortion optimizer (LC-RDO) configured to evaluate the coding efficiency of the coding tools by performing relatively simple calculations, such as spatial pixel filtering, absolute pixel difference calculation, pixel-wise squared difference calculation, pixel-wise transform difference calculation. Generally, each of the PEs 130-133 can have a pipelined structure or architecture that includes multiple processing stages. The pipelined structure is configured to process data by sequentially passing the data from one stage to the next. In some embodiments, the PEs 130-133 can incrementally fetch video data from the search memory (cache) 110 for processing. For example, each of the PEs 130-133 can be an LC-RDO having a pipelined structure that includes a horizontal filtering (HFIR) stage followed by a vertical filtering (VFIR) stage followed by a distortion calculation (DIST) stage followed by a comparison (COMP) stage. The LC-RDO can incrementally process data using the pipelined stages, where each stage processes a different portion of the data during each pipeline cycle.

[0031] Each PE 130-133 uses the same video data, i.e., video data 113 stored in search memory 110, to evaluate the coding efficiency of a respective coding tool. In some embodiments, video data 113 can include a coding block (CB) of a video. The coding tool 160 is determined in scheme 100 to be used to encode CB 113. Coding tool 160 is determined to be one of coding tools TO, Tl, T2, and T3. Coding tool 160 is determined by comparator 150, which is configured to compare evaluation results generated by PEs 130-133. Each PE 130-133 can perform a coding efficiency evaluation by applying a respective coding tool to video data 113, thereby generating an evaluation result. For example, PE 130 can perform a coding efficiency evaluation by applying coding tool TO to video data 113, thereby producing an evaluation result represented in figure of merit (FOM) 140. Similarly, each of PEs 131, 132, and 133 can perform a coding efficiency evaluation by applying coding tools Tl, T2, and T3, respectively, to video data 113, thereby producing evaluation results represented in FOMs 141, 142, and 143, respectively. In some embodiments, each of FOMs 140-143 can be a sum of squared differences (SSD), a sum of absolute differences (SAD), or a sum of absolute transformed differences (SATD) between the resulting encoded video and original video data 113, where the sum is computed for each pixel in video data 113. Comparator 150 can compare FOMs 140-143 and determine which of coding tools TO, Tl, T2, and T3 is coding tool 160, which will later be used to encode CB 113. For example, each FOM 140-143 can be a respective SSD value, and comparator 150 can compare FOMs 140-143 and determine that FOM 142 has the lowest value among FOMs 140-143. Accordingly, comparator 150 can thereby decide that coding tool T2 is coding tool 160 to be used to encode video data 113.

[0032] In some embodiments, in addition to the determined coding tool 160, comparator 150 can also determine a set of coding parameters to be used with the determined coding tool 160 to encode video data 113. To this end, some PEs 130-133 can be configured to operate using the same coding tool but using different sets of coding parameters applied to the same coding tool. For example, TO and Tl can be the same coding tool, while PEs 130 and 131 operate with different sets of coding parameters applied to the same coding tool, e.g., a first set of coding parameters and a second set of coding parameters. The resulting FOMs 140 and 141 will indicate which set of coding parameters is preferred between the first and second sets. The preferred set of coding parameters is included as part of the determined coding tool 160.

[0033] In some embodiments, the scheme 100 can involve a PE (e.g., PE 130, 131, 132, or 133) that includes a high complexity rate distortion optimizer (HC-RDO) in place of or in addition to the PE’s LC-RDO. The HC-RDO can be cascaded with the PE’s LC-RDO. Compared to an implementation of the PE with only the LC-RDO, the PE with the HC-RDO can determine or otherwise compute the corresponding FOM (i.e., FOM 140, 141, 142, or 143) with higher accuracy by involving more complex operations, albeit typically at the cost of more processing time. Due to the higher accuracy, the coding tools 160 determined by the PE involving the HC-RDO can be different from the coding tools 160 determined by the PE involving only the LC-RDO, and can be more suitable for coding, with enhanced coding efficiency and / or performance.

[0034] II. Time-interleaved cache access

[0035] The search memory 110 is sometimes referred to as a “cache” or “cache memory.” The cache 110 is designed as a temporary memory for storing video data, e.g., CB 113, during the coding tool evaluation process, where the PEs 130-133 can repeatedly access the cache 110 to load different portions of the CB 113. However, the cache 110 cannot provide simultaneous access to each of the PEs 130-133. That is, even though the scheme 100 illustrates that the PEs 130-133 can access the cache 110 through the data buses 120, 121, 122, and 123, the aforementioned property of the cache memory 110 requires that only one of the data buses 120-123 can be “open” at any time, i.e., transferring data from the cache 110 to one of the PEs 130-133. It follows that true parallelization among the PEs 130-133 is only possible if the cache 110 is replicated into multiple copies, each of which is accessed by a corresponding one of the PEs 130-133. Obviously, replicating the cache 110 is not an attractive parallelization solution because the hardware cost of replicating copies is high and can be impractical.

[0036] FIG. 2 is a diagram of an example design according to an implementation of the present disclosure, where actual meaningful parallelization is achieved without replicating the cache 110. Specifically, FIG. 2The time-interleaved cache access method 200 is illustrated, where the PEs 130-133 can operate concurrently, where no more than one data bus 120-123 is open to access the cache 110 at any time. That is, no more than one PE 130-133 can receive data (e.g., video data 113) from the cache 110 at any given time.

[0037] Prior to commencing the encoding efficiency evaluation process, the PEs 130-133 can not load or otherwise read all of the video data 113 from the cache 110. Rather, the PEs 130-133 can load only a portion of the video data 113, such as a portion 115 of the CB 113. The PEs 130-133 can not need to access the cache 110 to load more portions of the CB 113 until the portion 115 is processed. Each of the PEs 130-133 can have an internal memory, often referred to as a“line buffer,” to store the portion of the video data 113 that is currently being loaded. The PEs can access the line buffer to retrieve the portion of the video data 113 for the encoding tool evaluation process. The PEs can use the line buffer to save or store the portion of the video data 113 until the cache window is open again, at which time the next portion of the video data 113 is being loaded. The line buffer can then be replenished by the new portion of the video data 113 that is currently being loaded.

[0038] In some embodiments, the CB 113 can be divided into a plurality of non-overlapping sub-blocks, typically having the same size (e.g., 4 pixels in height and 4 pixels in width). That is, the sub-blocks of the CB 113 can form an array of columns and rows of the CB 113. The portion 115 of the CB 113 can include a plurality of sub-blocks, such as labeled“0,”“1,”“2,”“3,”“4,”“5.” Further, as described elsewhere above, each of the PEs 130-133 can be an LC-RDO pipeline composed of a HFIR stage, a VFIR stage, a DIST stage, and a COMP stage. Data can pass through the various stages of the LC-RDO pipeline, first processed by the HFIR stage, then by the VFIR stage, then by the DIST stage, and finally by the COMP stage. FIG. 2 A timeline 299 is provided. Progression of the first 13 pipeline cycles is represented, i.e., pipeline cycles 1-13.

[0039] Reference FIG. 2PEs 130-133 access cache 110 in a staggered manner. For example, during the first pipeline cycle, it is PE130's turn to access cache 110 (indicated by the "Read" phase in the diagram), during which PE130 loads sub-block "0" of CB 113. PEs 131-133 load sub-block "0" of CB 113 in the next three pipeline cycles, namely the second, third, and fourth pipeline cycles. After PEs 131-133 load sub-block "0" in sequence, PE 130 accesses cache 110 again in the fifth pipeline cycle, during which PE130 loads the next sub-block (i.e., sub-block "1" of CB 113). Similarly, PEs 131-133 load sub-block "1" of CB 113 in the next three pipeline cycles (i.e., the sixth, seventh, and eighth). After PEs 131-133 load sub-block "1" sequentially, PE 130 accesses cache 110 again in the ninth pipeline cycle, during which time PE 130 loads the next sub-block (i.e., sub-block "2" of CB 113). PEs 131-133 load sub-block "2" of CB 113 in the next three pipeline cycles (i.e., the tenth, eleventh, and twelfth pipeline cycles).

[0040] Because accesses to cache 110 by PEs 130-133 are time-interleaved, the processing of sub-blocks loaded within PEs 130-133 is also time-interleaved due to the pipeline characteristics of PEs. For example, PE 130 completes the processing of sub-block "0" of CB 113 at the end of the fourth pipeline cycle (the COMP stage of PE 130 completes the processing of sub-block "0"), while PEs 131, 132, and 133 complete the processing of sub-block "0" of CB 113 at the end of the fifth, sixth, and seventh pipeline cycles, respectively.

[0041] According to the time-interleaved cache access method 200, at most one sub-block of data is loaded from cache 110 in PEs 130-133 at any given time. Therefore, the parallelization scheme 100 can utilize only one copy of cache 110 by employing the time-interleaved cache access method 200. However, method 200 results in very low PE utilization. FIG. 2 As shown, the PE pipeline stage is idle (i.e., does not process any data) for most pipeline cycles. With four PEs parallelized, the time-interleaved cache access method 200 results in approximately 25% PE utilization. With more than four PEs involved in the parallelization scheme, the time-interleaved cache access method 200 will result in even lower PE utilization.

[0042] FIG. 3This is a diagram illustrating an example design based on an embodiment of this disclosure, showing an alternative time-interleaved cache access method (i.e., method 300) that significantly improves the low PE utilization caused by method 200. As... FIG. 3 As shown, the PE idle time is significantly less than in Method 200. In fact, after multiple pipeline cycles, the PE utilization of Method 300 approaches 100%. By loading more than one sub-block of CB 113 in each cache access window, most of the PE idle time in Method 200 is eliminated in Method 300. For example, while Method 200 instructs PE 130 to load only sub-block "0" of CB 113 from cache 110 during the first pipeline cycle, Method 300 encourages loading four sub-blocks, namely sub-blocks "0", "1", "2", and "3" of block CB 113 during the first pipeline cycle. Assuming that sub-blocks "1", "2", and "3" are loaded and stored in the queue buffer of PE 130 in the same pipeline cycle as sub-block "0", the start of PE 130 pipeline operations on sub-blocks "1", "2", and "3" can be advanced. For example, PE 130 can begin processing sub-block "1" as early as the second pipeline cycle and complete processing in the fifth pipeline cycle, three pipeline cycles earlier than method 200. The completion of PE 130 processing sub-block "2" is further advanced, from... FIG. 2 The twelfth pipeline cycle shown is dragged to... FIG. 3 The sixth production line cycle.

[0043] Specifically, according to the time-interleaved cache access method 300, each of PEs 130-133 receives video data 113 in batches of sub-blocks. Each batch contains multiple sub-blocks of video data 113, and the number of sub-blocks in each batch is equal to the number of PEs operating in parallel during the coding efficiency evaluation process. For example, in the coding efficiency evaluation process of parallelization scheme 100, four PEs (i.e., PEs 130-133) are used in parallel. Therefore, each of the four PEs is required to load a batch of four sub-blocks of CB113 (e.g., sub-blocks "0-3", "4-7", or "8-11") each time a time window is opened to access cache 110, as shown in the time-interleaved cache access method 300.

[0044] In some embodiments, the cache 110 can be divided into several "banks" (i.e., memory banks). The number of banks of a cache is an important parameter of the cache, as the number of banks represents the number of data entries that can be read from or written to the cache at the same time. Specifically, at any time, at most one data entry can be read from or written to a memory bank. Given that each PE 130-133 is expected to receive four sub-blocks of the CB 113 within one pipeline cycle, the cache 110 needs to have at least four memory banks, where the four sub-blocks in a batch in one pipeline cycle are stored in four separate memory banks, respectively. As discussed elsewhere below, considerations such as the number of memory banks that a cache such as the cache 110 must have, and which sub-blocks of the video data 113 are stored in which memory banks, are important design parameters in implementing the combination of the parallel encoding tool evaluation scheme 100 and the time-interleaved cache access method 300.

[0045] III. Sub-Block Scan Order

[0046] As discussed elsewhere above, an encoding block can be divided into a plurality of sub-blocks such that the sub-blocks form an array of columns and rows of the encoding block. FIG. 4 is a diagram of an example design according to an embodiment of the present disclosure in which the CB 113 is divided into non-overlapping sub-blocks that form an array of columns and rows. Specifically, the CB 113 is as shown. FIG. 4 The CB size of is 32 pixels wide and 32 pixels high, while the size of each sub-block is 4 x 4 pixels. Thus, the CB 113 is divided into 64 sub-blocks, as shown in each of 411, 412, 451, and 452.

[0047] According to the time-interleaved cache access method 300, each of the PEs 130-133 is designed to load or otherwise receive sub-blocks of the CB 113 in batches, each batch containing four consecutive sub-blocks of the CB 113. FIG. 4 Two types of scan orders that the PEs 130-133 can use to receive the sub-blocks of the CB 113 are shown. Specifically, the PEs 130-133 can use a scan order called "raster scan" to receive the sub-blocks of the CB 113, as shown in charts 411 and 412. Or a scan order called "serpentine scan," as shown in charts 451 and 452. The raster scan can be performed in a column-wise manner or in a row-wise manner. The row-wise manner is shown in chart 411, in which the PEs 130-133 load the sub-blocks in the first row of the CB 113 from left to right, then load the sub-blocks in the second row of the CB 113 also from left to right, and so on. The column-wise manner is shown in chart 412, in which the PEs 130-133 load the sub-blocks in the first column of the CB 113 from top to bottom, then load the sub-blocks in the second column of the CB 113 also from top to bottom, and so on.

[0048] Similarly, the serpentine scan can also be performed in a column-wise manner or a row-wise manner. In the serpentine scan, the scan direction alternates every row or column. A column-wise serpentine scan is shown in chart 451, where PEs 130-133 load sub-blocks in the first column of CB 113 from top to bottom, then load sub-blocks in the second column of CB 113 from bottom to top, then load sub-blocks in the third column of CB 113 from top to bottom again, and so on. A row-wise serpentine scan is shown in chart 452, where PEs 130-133 load sub-blocks in the first row of CB 113 from left to right, then load sub-blocks in the second row of CB 113 from right to left, then load sub-blocks in the third row of CB 113 from left to right again, and so on.

[0049] As described elsewhere above, each of PEs 130-133 needs to load a batch of four sub-blocks once (i.e., during a pipeline cycle) according to the time-interleaved cache access method 300. As shown, for CB 113, each column or row can be loaded exactly in two batches, whether it is a raster scan or a serpentine scan, and there is no cross-column or cross-row situation when loading any batch of 4 sub-blocks. That is, there is no situation where two of the four sub-blocks in a batch fetched during a pipeline cycle are located in two adjacent columns or rows of CB 113.

[0050] For FIG. 4 The corresponding cache bank allocation for the sub-blocks of CB 113 can also be easily determined. For example, cache bank allocation 422 can be used for the raster scan of chart 412 and the serpentine scan of chart 451. As shown in cache bank allocation 422, cache 110 needs to have four banks, i.e., “0”, “1”, “2”, “3” as shown in cache bank allocation 422. The sub-blocks of CB 113 are stored in cache 110 according to cache bank allocation 422. That is, the first and fifth sub-blocks of each column are stored in bank “0”; the second and sixth sub-blocks of each column are stored in bank “1”; the third and seventh sub-blocks of each column are stored in bank “3”; and finally, the fourth and eighth sub-blocks of each column are stored in bank “4”.

[0051] However, for coding blocks having more or less number of sub-blocks in a row or column, or for different number of parallel PEs involved in parallel coding tool evaluation scheme 100, the cross-column or cross-row situation can be unavoidable, and the corresponding cache bank allocation can become more complex. For these situations, the serpentine scan processing order is superior to the raster scan processing order because the corresponding cache bank allocation for the serpentine scan is relatively simple compared to the raster scan. It can be difficult to find or determine the corresponding cache bank allocation for the raster scan processing order because the cross-column or cross-row address difference can be very different depending on the size of the coding block used. In contrast, the serpentine scan processing order has limited address difference when facing cross-column or cross-row scenarios.

[0052] FIG. 5 are diagrams of example designs according to embodiments of the present disclosure, in which all possible cross-column serpentine scanning scenarios are illustrated regardless of the size of the CB 113. Specifically, chart 540 illustrates all four possible scenarios involving four PEs in the cross-column parallel coding tool evaluation scheme 100. As shown in chart 540, the maximum address difference between the four possibilities is equal to four times the sub-block height. Similarly, chart 530 illustrates all three possibilities for cross-column scenarios when three PEs are involved in the parallel coding tool evaluation scheme 100; the maximum address difference between the three possibilities is equal to three times the sub-block height. Likewise, chart 550 illustrates all five possibilities for cross-column scenarios when five PEs are involved in the parallel coding tool evaluation scheme 100; the maximum address difference between the five possibilities is equal to five times the sub-block height.

[0053] Also as shown. FIG. 5 are the corresponding bank allocations for the scenarios illustrated in charts 530, 540, and 550, respectively, i.e., bank allocations 532, 542, and 552 for cache 110. The banks of cache 110 can be divided into two groups, where each group can have as many banks as the number of PEs. For example, in bank allocation 542, cache 110 has two groups of four banks, with the first group consisting of banks “0”, “1”, “2”, and “3”, and the second group consisting of banks “4”, “5”, “6”, and “7”. The banks in the first group are repeatedly allocated to the sub-blocks of each odd column (i.e., the first, third, fifth, seventh, ninth, and eleventh columns, etc.) from top to bottom, while the banks in the second group are repeatedly allocated to the sub-blocks of each even column (i.e., the second, fourth, sixth, eighth, tenth, and twelfth columns, etc.) also from top to bottom. Thus, the sub-blocks of any two column neighbors are stored in the banks of the two groups, respectively. As another example, in bank allocation 552, cache 110 has two groups of five banks, with the first group consisting of banks “0”, “1”, “2”, “3”, and “4”, and the second group consisting of banks “5”, “6”, “7”, “8”, and “9”. The banks in the first group are repeatedly allocated to the sub-blocks of each odd column from top to bottom, while the banks in the second group are repeatedly allocated to the sub-blocks of each even column also from top to bottom. Thus, the sub-blocks of any two column neighbors are stored in the banks of the two groups, respectively.

[0054] IV. Illustrative Implementation

[0055] FIG. 6An example apparatus 600 is shown that is capable of evaluating the coding efficiency of multiple coding tools using the parallelization methods described above. As shown, the apparatus 600 receives video data 601 for evaluation of coding tools and accordingly determines a coding tool 660 that is suitable for encoding the video data 601. In some embodiments, the apparatus 600 can also determine a setting 666 of encoding parameters that will be used with the determined coding tool 660. The video data 601 can comprise the coding block 113, and the determined coding tool 660 can be an embodiment of the coding tool 160. The apparatus 600 can be used to implement the parallel coding tool evaluation scheme 100 using the time-interleaved cache access methods 200 or 300.

[0056] As shown, the apparatus 600 has several components or modules for processing the video data 601 and determining the coding tool 660, at least some of which are selected from a processor 605, a search memory or cache 610, a plurality of processing elements (e.g., as PEs 631-634), a memory 640, and a comparator 650. The cache 610 can comprise a plurality of banks, e.g., banks 611-614, each of which is capable of providing respective data entries concurrently with the remaining banks.

[0057] In some embodiments, the modules 605-650 listed above are modules of software instructions executed by one or more processing units (e.g., processors) of a computing or electronic device. In some embodiments, the modules 605-650 are hardware circuit modules implemented by one or more integrated circuits (ICs) of an electronic device. Although the modules 605-650 are shown as separate modules, some of the modules can be combined into a single module.

[0058] The processor 605 is configured to receive and analyze the video data 601, thereby determining a bank allocation (e.g., the bank allocations 422, 532, 542, or 552). That is, the bank allocation is specific to the video data 601. The processor 605 is also configured to store sub-blocks of the video data 601 in the search memory 610 according to the determined bank allocation.

[0059] The cache 610 can comprise a plurality of banks, e.g., banks 611, 612, 613, and 614. The number of banks can be consistent with (e.g., equal to) the number of banks indicated in the bank allocation, which is determined by the processor 605. The number of banks of the cache 610 can be more than FIG. 6 The four banks shown. For example, the bank allocation 542 indicates eight different banks for the snake scan. The processor 605 can accordingly store the video data 601 in eight different banks of the cache 610. The cache 610 can comprise the search memory 110.

[0060] Each of the processing elements 631-634 can be an embodiment of one of the PEs 130-133. In some embodiments, each of the processing elements 631-634 can be a low complexity RDO pipeline. In some embodiments, each of the processing elements 631-634 can additionally or alternatively include a high complexity RDO. The processing elements 631-634 can be configured to fetch a portion of the video data 601 by accessing the cache 610 in a time-interleaved manner (e.g., following the time-interleaved approach 200 or 300). The portion of video data 601 fetched at a time can include multiple sub-blocks of the video data 601 (e.g., sub-blocks 0-3, 4-7, or 8-11 of the portion 115 of the CB 113). In some embodiments, each processing element 631-634 can include a queue buffer configured to temporarily store sub-blocks fetched in bulk from the cache 610 until all sub-blocks of the bulk have been processed via the pipeline stages of the respective processing element.

[0061] Each of the processing elements 631-634 can also be configured to compute a respective figure of merit (FOM) (e.g., FOMs 140, 141, 142, or 143) for the video data 601 indicative of the coding efficiency of the respective encoding tool applied. Thus, the FOM is specific to the respective encoding tool and the video data 601. That is, the FOM is specific to the combination of the respective encoding tool and the video data 601. The FOM can be a sum of squared differences, a sum of absolute differences, or a sum of absolute transform differences. The FOMs computed by the processing elements 631-634 can be stored in the memory 640 and used as inputs to the comparator 650. In some embodiments, the processing elements 631-634 can also store the encoding parameters used to compute the FOMs. In some embodiments, each of the PEs 631-634 can compute multiple FOMs for the video data 601 using the same encoding tool but with different encoding parameter settings. That is, in these embodiments, each computed FOM is specific to the combination of the respective encoding tool, the respective encoding parameter, and the video data 601. Each FOM and the respective encoding parameter setting can be saved in the memory 640.

[0062] The comparator 650 can be one embodiment of the comparator 150 and is configured to determine the encoding tool 660 by comparing the FOMs computed by the processing elements 631-634 and stored in the memory 640. The comparison by the comparator 650 can determine a preferred FOM. For example, the preferred FOM can be the SAD with the lowest value. Thus, the encoding tool that results in the lowest value of the SAD can be determined as the encoding tool 660. In some embodiments, the comparator 650 can also determine the parameter settings 666 that can be the parameter settings used by the processing elements 631-634 that result in the preferred FOM (e.g., with the lowest value of the SAD).

[0063] V. Illustrating a Process

[0064] FIG. 7 An example process 700 is illustrated in accordance with an embodiment of the present disclosure. The process 700 can represent aspects of the designs, concepts, schemes, systems, and methods implementing the various proposals described above. More specifically, the process 700 can represent aspects of the proposed concepts and schemes related to determining an encoding tool from a plurality of encoding tools in accordance with the present disclosure. The process 700 can include one or more operations, actions, or functions as illustrated in one or more of blocks 710, 720, 730, and 740. While illustrated as discrete blocks, various blocks of the process 700 can be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. Further, the blocks / sub-blocks of the process 700 can be performed in the order specified, or in a different order. Moreover, one or more of the blocks / sub-blocks of the process 700 can be performed repeatedly or iteratively. The process 700 can be implemented by or in the apparatus 600 and any variants thereof. For purposes of illustration only, and without limitation of scope, the process 700 is described below in the context of the apparatus 600. The process 700 can begin at block 710. FIG. 7 The order shown, or in a different order. Moreover, one or more of the blocks / sub-blocks of the process 700 can be performed repeatedly or iteratively. The process 700 can be implemented by or in the apparatus 600 and any variants thereof. For purposes of illustration only, and without limitation of scope, the process 700 is described below in the context of the apparatus 600. The process 700 can begin at block 710.

[0065] At 710, the process 700 can involve each processing element (e.g., PEs 631-634) of the apparatus 600 receiving video data (e.g., video data 113 or 601) to be evaluated in performing an encoding efficiency evaluation. Each processing element is configured to evaluate the video data for a respective encoding tool (e.g., encoding tools 121-124 or 651-654) and compute a FOM (e.g., SAD) for the respective encoding tool. The FOMs are stored in the memory 640. FIG. 1encoding efficiency evaluation. In some embodiments, the PEs of the apparatus 600 receive the video data 601 by accessing the cache 610 in a time-interleaved manner. That is, at any time, no more than one PE of the apparatus 600 can access the cache 610. In some embodiments, the video data 601 can include a coding block (CB), which can be divided into a plurality of sub-blocks forming an array of columns or rows. The PEs of the apparatus 600 can receive the CB in batches of sub-blocks, each batch having a plurality of sub-blocks. In some embodiments, the number of sub-blocks in a batch is equal to the number of simultaneously operating PEs of the apparatus 600. In some embodiments, the sub-blocks of the video data 601 can be accessed by the PEs of the apparatus 600 using a snake scan through the columns or rows of the sub-blocks of the video data 601. The process 700 can continue from 710 to 720.

[0066] At 720, the process 700 can involve each PE of the apparatus 600 computing a respective FOM. In some embodiments, each PE can be an LC-RDO, and the respective FOM can be a sum of squared differences (SSD), a sum of absolute differences (SAD), or a sum of absolute transformed differences (SATD). The FOMs computed by the PEs of the apparatus 600 can be stored in the memory 640. In some embodiments, the encoding parameters used to compute the FOMs can also be stored in the memory 640. The process 700 can proceed from 720 to 730.

[0067] At 730, the process 700 can involve the comparator 650 comparing the FOMs stored in the memory 640 and accordingly determining an encoding tool 660, which is specific to the video data 601. In some embodiments, the comparator 650 can determine a parameter setting 666 to use with the determined encoding tool 660. The determined parameter setting 666 can be a set of settings including values for a plurality of encoding parameters. The process 700 can proceed from 730 to 740.

[0068] At 740, the process 700 can involve the processor 605 encoding the video data 601 using the determined encoding tool 660. In some embodiments, the processor 605 can encode the video data 601 using the determined encoding tool 660 and the determined parameter setting 666.

[0069] Six, Illustrative Electronic Systems

[0070] Many of the above-described features and applications are implemented as software processes that are specified as a set of instructions recorded on a computer readable storage medium (also referred to as computer readable medium). When these instructions are executed by one or more computational or processing units (e.g., one or more processors, cores of processors, or other processing units), they cause the processing unit(s) to perform the actions indicated in the instructions. Examples of computer readable media include, but are not limited to, CD-ROMs, flash drives, random access memories (RAM) chips, hard drives, erasable programmable read only memories (EPROM), electrically erasable programmable read only memories (EEPROM), etc. Computer readable media does not include wireless or wired carrying signals, and electronic signals that travel through wired or wireless networks.

[0071] In this specification, the term "software" means including an application program that resides in read-only memory or is stored in memory that can be read into memory for processing by a processor. Also, in some embodiments, multiple software inventions can be implemented as sub-parts of a larger program while remaining distinct software inventions. In some embodiments, multiple software inventions can also be implemented as separate programs. Finally, any combination of separate programs that together implement the software inventions described here are within the scope of the present disclosure. In some embodiments, the software programs, when installed to operate on one or more electronic systems, define one or more specific machine implementations that execute and perform the operations of the software programs.

[0072] FIG. 8 The electronic system 800 conceptually illustrates an electronic system, including a processing device 810, a storage device 820, an input device 840, and an output device 845, with which a software implementation of embodiments of the present disclosure can be implemented. The electronic system 800 can be a computer (e.g., a desktop computer, a personal computer, a tablet computer, etc.), a telephone, a PDA, or any other sort of electronic device. Such an electronic system includes various types of computer readable media and interfaces for various other types of computer readable media. Electronic system 800 includes a bus 805, a processing device 810, a graphics processing unit (GPU) 815, a system memory 820, a network 825, a read-only memory (ROM) 830, a permanent storage device 835, an input device 840, and an output device 845.

[0073] The bus 805 collectively represents all system, peripheral and chipset buses that communicatively connect the various internals of the electronic system 800. For instance, the bus 805 communicatively connects the processing device 810 with the GPU 815, the read-only memory 830, the system memory 820, and the permanent storage device 835.

[0074] From these various memory units, processing unit 810 retrieves instructions to execute and data to process in order to execute processes of the present disclosure. The processing unit can be a single processor or a multi-core processor in different embodiments. Some instructions are passed to GPU 815 and executed by it. GPU 815 can offload various computations or supplement image processing provided by processing unit 810.

[0075] Read only memory (ROM) 830 stores static data and instructions that are used by processing unit 810 and other modules of the electronic system. Permanent storage device 835 on the other hand, is a read-and-write memory device. This device is a non-volatile memory unit that stores instructions and data even when electronic system 800 is off. Some embodiments of the present disclosure use a mass-storage device (such as a magnetic or optical disk and its corresponding disk drive) as permanent storage device 835.

[0076] Other embodiments use a removable storage device (such as a floppy disk, flash drive, etc., and its corresponding disk drive) as permanent storage device. Like permanent storage device 835, system memory 820 is a read-and-write memory device. However, unlike storage device 835, system memory 820 is a volatile read-and-write memory, such as a random access memory. System memory 820 stores some of the instructions and data that processing unit uses at runtime. In some embodiments, the processes according to the present disclosure are stored in system memory 820, permanent storage device 835, and / or read only memory 830. For example, various memory units include instructions for processing multimedia clips with some embodiments. From these different memory units, processing unit 810 retrieves instructions to execute and data to process in order to execute the processes of some embodiments.

[0077] Bus 805 also connects to input and output devices 840 and 845. Input device 840 enables the user to communicate information and select commands to the electronic system. Input device 840 includes alphanumeric and other keys, a cursor control device (also called a cursor control device), a camera (such as a webcam), a microphone or similar device for receiving voice commands, etc. Output device 845 displays information generated by the electronic system or otherwise outputs data. Output device 845 includes a printer and display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for

[0078] Finally, as FIG. 8As shown, bus 805 also couples electronic system 800 to a network 825 through a network adapter (not shown). In this manner, the computer can be a part of a network of computers such as a local area network ("LAN"), a wide area network ("WAN"), or an Intranet, for example. Any or all components of electronic system 800 can be used in conjunction with the subject disclosure.

[0079] Some embodiments include a machine-readable or computer- readable medium (also referred to as computer-readable storage media, machine-readable media, or machine- readable storage media). Some examples of such computer-readable media include RAM, ROM, read-only compact discs (CD-ROM), recordable compact discs (CD-R), rewritable compact discs (CD-RW), read-only digital versatile discs (e.g., DVD- ROM, dual-layer DVD-ROM), a variety of recordable / rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD cards, mini-SD cards, micro-SD cards, etc.), magnetic and / or solid-state hard drives, read-only and recordable Blu-Ray® discs, ultra-density optical discs, any other optical or magnetic media, and floppy disks. The computer-readable media can store a computer program, which is executable by at least one processing unit and includes sets of instructions for performing a variety of operations. Examples of computer programs or computer code include machine code, such as is produced by a compiler, and files including higher-level code that are executed by a computer, an electronic component, or a microprocessor using an interpreter. As shown, bus 805 also couples electronic system 800 to a network 825 through a network adapter (not shown). In this manner, the computer can be a part of a network of computers such as a local area network ("LAN"), a wide area network ("WAN"), or an Intranet, for example. Any or all components of electronic system 800 can be used in conjunction with the subject disclosure.

[0080] While the above discussion primarily refers to microprocessor or multi-core processors that execute software, some embodiments are performed by one or more integrated circuits, for example application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In some embodiments, such integrated circuits execute instructions stored on the circuit itself. In other embodiments, the instructions are stored on RAM, ROM, or flash memory devices associated with the integrated circuit.

[0081] As used in this specification and any claims of this application, the terms “computer”, “server”, “processor”, and “memory” all refer to electronic or other technological devices. These terms do not encompass humans or groups of humans. For purposes of this specification, the term display or displaying means display on an electronic device. As used in this specification and any claims of this application, the terms “computer readable medium”, “computer readable media”, and “machine readable medium” are entirely restricted to tangible, physical objects that store information in a

[0082] Supplemental Note

[0083] The subject matter described herein is sometimes illustrated using different components contained within, or in connection with, different other components. It will be understood that the architecture shown is merely illustrative of one way in which the same functionality can be implemented, and that many other architectures can be implemented which achieve the same functionality.

[0084] Further, with respect to the use of substantially any plural and / or singular term herein, those having skill in the art can translate the permutations of the term in this context to the corresponding singular and / or plural context, and / or vice versa, as appropriate to the use of the term in this specification. For the sake of clarity, the various singular / plural permutations of the term “a” or “an” and “the” will be explicitly set forth with the appropriate designation if intended to be solely singular or be exclusively plural.

[0085] Further, those skilled in the art will appreciate that, in general, the terms used herein, especially in the appended claims, such as in the body of the appended claims, are generally intended as open terms, e.g., the term "comprising" is to be construed as "including but not limited to" the elements recited in the claim, the term "having" is to be construed as "including at least the elements recited in the claim," the term "including" is to be construed as "including but not limited to," the term "containing" is to be construed as "including but not limited to the elements recited in the claim," and the like. Those skilled in the art will further appreciate that if a specific number of an introduced claim statement is intended, that intent would be expressly recited in the claim, and no such intent exists without such recitation. For example, to assist in understanding, the following appended claims can contain the use of introductory phrases such as "at least one" and "one or more" to introduce recitations of claims. However, the use of such phrases is not to be construed as implying that the claims introduced by the indefinite article "a" or "an" are limited to only one such claim embodiment of the claim, even when the same claim includes the introductory phrase "one or more" or "at least one" and the indefinite article, e.g., "a" or "an," is to be construed as "at least one" or "one or more"; the same applies to the use of the definite article to introduce recitations of claims. Moreover, even if a specific number of an introduced claim recitation is expressly recited, those skilled in the art will recognize that such recitation is to be construed as referring at least to the recited number, e.g., only "two recitations" are recited without other modifiers, means at least two recitations, or two or more recitations. Furthermore, in those instances where a convention analogous to "at least one of A, B, and C, etc." is used, in general such a construction is intended to be interpreted in the same way as "A, B, and / or C," etc. as set forth above, e.g., "a system having at least one of A, B, and C" is intended to cover a system having A alone as well as a system having B alone as well as a system having C alone as well as a system having both A and B together as well as a system having both A and C together as well as a system having both B and C together as well as a system having all of A, B, and C together, etc. In those instances where a convention analogous to "at least one of A, B, or C, etc." is used, in general such a construction is intended to be interpreted in the same way as "A, B, and / or C," etc. as set forth above, e.g., "a system having at least one of A, B, or C" is intended to cover a system having A alone as well as a system having B alone as well as a system having C alone as well as a system having both A and B together as well as a system having both A and C together as well as a system having both B and C together as well as a system having all of A, B, and C together, etc. Those skilled in the art will further recognize that where a statement analogous to "at least one of A or B" is used, that statement is intended to cover both the case where one or the other of A or B is included, as well as the case where both A and B are included, e.g., the statement "at least one of A or B" is intended to cover the case where A alone is included, the case where B alone is included, the case where A and B are both included, etc.

[0086] From the foregoing, it will be appreciated that various embodiments of the disclosure have been described herein for purposes of illustration, and that various modifications can be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are by way of example only, and are not intended to limit the true scope and spirit of the disclosure as encompassed by the claims attached hereto.

Claims

1. A video data encoding method, comprising: Video data is received by multiple processing elements (PEs), each of which is configured to perform an encoding efficiency evaluation on a corresponding encoding tool. The video data includes an encoding block (CB) divided into multiple sub-blocks. The multiple processing elements include a first number of processing elements. The multiple processing elements receive the video data by each of the multiple processing elements receiving multiple sub-blocks of the encoding block in batches, with each batch including a second number of multiple sub-blocks, the second number being equal to the first number. The coding efficiency evaluation is performed by each of a plurality of processing elements, and a corresponding quality factor (FOM) specific to the corresponding coding tool and video data is calculated by each of the plurality of processing elements, wherein each of the plurality of processing elements has a pipeline structure comprising multiple stages. By comparing the quality factors calculated by multiple processing elements, a specific encoding tool for the video data is determined. as well as The video data is encoded using a specific encoding tool.

2. The video data encoding method according to claim 1, characterized in that, No more than one of the plurality of processing elements may simultaneously receive video data.

3. The video data encoding method according to claim 1, characterized in that: Multiple sub-blocks form an array of columns and rows.

4. The video data encoding method according to claim 3, characterized in that, Receiving the video data by the plurality of processing elements includes each of the plurality of processing elements receiving the plurality of sub-blocks using a serpentine scan through columns or rows.

5. The video data encoding method according to claim 3, characterized in that... Also includes: Each of the plurality of processing elements stores the second number of sub-blocks in a corresponding buffer accessible by the respective processing element.

6. The video data encoding method according to claim 3, characterized in that, Calculating the corresponding quality factor involves processing the second number of sub-blocks sequentially through the multiple levels.

7. The video data encoding method according to claim 1, characterized in that: Video data consists of coded blocks (CBs) divided into multiple sub-blocks, which form an array of columns and rows. Receiving video data includes receiving video data stored in a memory having multiple storage units, wherein the multiple storage units include a first group having a third number of storage units and a second group having a fourth number of storage units, and Each pair of columns or rows in adjacent columns or rows of the array is stored in the first group and the second group of storage, respectively.

8. The video data encoding method according to claim 7, characterized in that: The plurality of processing elements includes a first number of processing elements, and Each of the third quantity and the fourth quantity is equal to the first quantity.

9. The video data encoding method according to claim 1, characterized in that, Each of the plurality of PEs is a low-complexity rate distortion optimizer (LC-RDO), and the quality factor mentioned therein includes sum of squared differences (SSD), sum of absolute differences (SAD), or sum of absolute transform differences (SATD).

10. The video data encoding method according to claim 1, characterized in that... Also includes: Determine a set of encoding parameters associated with the determined encoding tool.

11. A video data encoding apparatus, comprising: A high-speed cache memory with multiple memory banks; The processor is configured to store video data in a cache memory according to a video data-specific block allocation scheme; Multiple processing elements (PEs), each configured to calculate a corresponding quality factor (FOM) specific to a corresponding encoding tool and video data, the video data including encoded blocks (CBs) divided into multiple sub-blocks, the multiple processing elements including a first number of processing elements, the multiple processing elements receiving the video data including each of the multiple processing elements receiving multiple sub-blocks of the encoded blocks in batches, each batch including a second number of multiple sub-blocks, the second number being equal to the first number, wherein each of the multiple processing elements has a pipeline structure including multiple stages; and The comparator is configured to determine the specific encoding tool for the video data by comparing quality factors calculated by the plurality of processing elements.

12. The video data encoding apparatus according to claim 11, characterized in that, No more than one of the plurality of processing elements may access the cache memory.

13. The video data encoding apparatus according to claim 11, characterized in that: Multiple sub-blocks form an array of columns and rows.

14. The video data encoding apparatus according to claim 13, characterized in that, Each of the plurality of processing elements accesses the cache memory using a serpentine scan through the columns or rows of the plurality of sub-blocks.

15. The video data encoding apparatus according to claim 13, characterized in that... Each of the plurality of processing elements is configured to store the second number of sub-blocks in a corresponding buffer accessible by the respective processing element.

16. The video data encoding apparatus according to claim 13, characterized in that, Each of the plurality of processing elements is configured to calculate its own quality factor by sequentially processing the second number of sub-blocks through multiple levels.

17. The video data encoding apparatus according to claim 11, characterized in that: The video data includes coded blocks (CBs) divided into multiple sub-blocks, which form an array of columns and rows. The multiple storage banks include a first group of storage banks having a third number of storage banks, and a second group of storage banks having a fourth number of storage banks, and Each pair of adjacent columns or rows of the array is stored in the first group and the second group of multiple storage banks, respectively.

18. The video data encoding apparatus according to claim 17, characterized in that: The plurality of processing elements includes a first number of processing elements, and Each of the third and fourth quantities is equal to the first quantity.

19. The video data encoding apparatus according to claim 11, characterized in that... Each of the plurality of PEs is a low-complexity rate distortion optimizer (LC-RDO), and the quality factor mentioned therein includes sum of squared differences (SSD), sum of absolute differences (SAD), or sum of absolute transform differences (SATD).

20. The video data encoding apparatus according to claim 11, characterized in that, The comparator further determines a set of encoding parameters associated with the determined encoding tool.

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