Image sensor readout circuit, image sensor and method of operation thereof

Abstract

The application discloses an image sensor readout circuit, an image sensor and a working method thereof, and belongs to the field of sensors. A switch selection circuit is connected with a pixel circuit of the image sensor. In a first state, a slope voltage is connected to a first node, and a reset signal and an image signal output by the pixel circuit under high conversion gain are connected to a second node in sequence. In a second state, the slope voltage and a coupling signal of the reset signal or the image signal output by the pixel circuit under low conversion gain are connected to the first node, and a reference voltage is connected to the second node. An analog-to-digital conversion circuit quantizes the high-gain reset signal and the high-gain image signal to obtain effective image signal quantization values under high gain, and quantizes the low-gain reset signal and the low-gain image signal to obtain effective image signal quantization values under low gain. While realizing high dynamic range of the image sensor, the cost is reduced and the volume is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of sensors, and particularly relates to an image sensor readout circuit, an image sensor and a working method thereof. BACKGROUND

[0002] Dynamic range is a key factor of imaging quality of an image sensor, and a large dynamic range can output scene image information in a wider light intensity range and present more abundant image details. Generally, the dynamic range of an image sensor output is about 60dB to 70dB, and the dynamic range required for simultaneously capturing image information of high light and shadow parts in a general natural environment application is about 100db. In the design of an image sensor, there are several ways to improve the dynamic range, for example, further improving the full-well charge capacity of a pixel circuit to obtain a larger dynamic range, or using a multi-frame synthesis method to realize high dynamic range of an image sensor by reading multiple frames of images.

[0003] Dual conversion gain (DCG) is applied to a pixel circuit of an image sensor, and in a low-illumination condition, a smaller integration capacitor is used to improve conversion gain to improve sensitivity, and in a high-illumination condition, a larger integration capacitor is used to store more charges to reduce conversion gain to improve dynamic range. A related image sensor readout circuit sequentially reads a low-conversion-gain reset signal, a high-conversion-gain reset signal, a high-conversion-gain image signal and a low-conversion-gain image signal output by the pixel array according to control by a control circuit; the readout circuit includes a selection switch, a low-conversion-gain analog-to-digital conversion circuit and a high-conversion-gain analog-to-digital conversion circuit, the low-conversion-gain analog-to-digital conversion circuit is used to quantize the reset signal and the image signal output by the pixel array under low conversion gain, and the high-conversion-gain analog-to-digital conversion circuit is used to quantize the reset signal and the image signal output by the pixel array under high conversion gain. Therefore, two analog-to-digital conversion circuits are required to process the signals output under low conversion gain and the signals output under high conversion gain, which is high in cost and large in size. SUMMARY

[0004] The present application aims to provide an image sensor readout circuit, an image sensor and a working method thereof, and aims to solve the defects of high cost and large size of the related image sensor readout circuit.

[0005] An image sensor readout circuit is provided in the embodiments of the present application, which comprises:

[0006] A switch selection circuit is connected to the pixel circuit of the image sensor. The pixel circuit is configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal. The switch selection circuit is configured, in a first state, to connect a ramp voltage to a first node and sequentially connect the reset signal and image signal output by the pixel circuit at high conversion gain to a second node. The switch selection circuit is further configured, in a second state, to connect the ramp voltage and the coupling signal between the reset signal and the image signal output by the pixel circuit at low conversion gain to the first node, while simultaneously connecting a reference voltage to the second node.

[0007] An analog-to-digital converter circuit, connected to the first node and the second node, is configured to quantize the high-gain reset signal and the high-gain image signal respectively to obtain the quantized value of the effective image signal under high gain, and to quantize the low-gain reset signal and the low-gain image signal respectively to obtain the quantized value of the effective image signal under low gain.

[0008] This application also provides an image sensor, including:

[0009] The pixel circuit is configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal; and

[0010] The readout circuit of the image sensor described above.

[0011] This application also provides an electronic device including the image sensor described above.

[0012] This application also provides a method for operating an image sensor readout circuit, including:

[0013] Input a first switch control signal to enable the switch selection circuit to connect the ramp voltage to the first node, connect the high-gain reset signal and the high-gain image signal output sequentially by the pixel circuit under high gain to the second node, and enable the analog-to-digital conversion circuit to quantize the high-gain reset signal and the high-gain image signal respectively to obtain the quantized value of the effective image signal under high gain;

[0014] A second switch control signal is input so that the switch selection circuit connects the ramp voltage and the low-gain image signal and low-gain reset signal output sequentially by the pixel circuit under low gain to the first node, and connects the reference voltage to the second node; and causes the analog-to-digital conversion circuit to quantize the low-gain image signal and the low-gain reset signal respectively to obtain the quantized value of the effective image signal under low gain.

[0015] The beneficial effects of this invention compared to existing technologies are as follows: By connecting the low-gain image signal and the high-gain image signal to the analog-to-digital converter circuit in different ways through a switching selection circuit for quantization processing, a single analog-to-digital converter circuit achieves a dual-conversion gain mode for quantization. This reduces cost and size while achieving a high dynamic range for the image sensor. Since there is no need to sample and hold the output of the pixel circuit to improve the KT / C noise of the circuit, the noise level of the circuit is lower, further improving the performance of the image sensor. Attached Figure Description

[0016] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an image sensor readout circuit provided in one embodiment of this application;

[0018] Figure 2 This is a schematic diagram of another structure of the analog-to-digital conversion circuit in the image sensor readout circuit provided in an embodiment of this application;

[0019] Figure 3 An example circuit diagram of an image sensor readout circuit provided in an embodiment of this application;

[0020] Figure 4 yes Figure 3 The timing diagram of the image sensor readout circuit is shown. Detailed Implementation

[0021] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0022] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0023] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0024] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0025] Figure 1 A schematic diagram of the image sensor readout circuit provided in Embodiment 1 of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0026] The image sensor readout circuit described above has two states.

[0027] The image sensor readout circuit described above includes a switch selection circuit 12 and an analog-to-digital conversion circuit 13.

[0028] The pixel circuit 11 is configured to sequentially output a high-gain image signal and a low-gain image signal.

[0029] The switch selection circuit 12 is connected to the pixel circuit 11 of the image sensor. The pixel circuit 11 is configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal. The switch selection circuit 12 is configured to connect the ramp voltage to the first node in the first state, and sequentially connect the reset signal and the image signal output by the pixel circuit 11 under high conversion gain to the second node. The switch selection circuit 12 is also configured to connect the ramp voltage and the coupled signal of the reset signal or image signal output by the pixel circuit 11 under low conversion gain to the first node in the second state, and simultaneously connect the reference voltage to the second node.

[0030] The analog-to-digital converter circuit 13 is connected to the first node and the second node. It quantizes the high-gain reset signal and the high-gain image signal to obtain the quantized value of the effective image signal under high gain, and quantizes the low-gain reset signal and the low-gain image signal to obtain the quantized value of the effective image signal under low gain.

[0031] Here, high-gain image signal refers to the image signal under high conversion gain; low-gain image signal refers to the image signal under low conversion gain. High-gain reset signal refers to the reset signal under high conversion gain; low-gain reset signal refers to the reset signal under low conversion gain. The effective image signal quantization value under high gain refers to the difference between the high-gain reset signal and the high-gain image signal; the effective image signal quantization value under low gain refers to the difference between the low-gain reset signal and the low-gain image signal.

[0032] The high-gain image signal and the low-gain image signal are acquired through the same exposure.

[0033] In particular, by combining a high-gain reset signal to quantize a high-gain image signal and a low-gain reset signal to quantize a low-gain image signal, the accuracy of the image signal quantization result is improved.

[0034] It should be noted that, as Figure 2 As shown, the analog-to-digital converter circuit 13 includes a comparator circuit 131, a counter 132, and a memory 133 connected in sequence; the comparator circuit 131 includes a comparator, the non-inverting input terminal of the comparator is connected to the first node, and the inverting input terminal of the comparator is connected to the second node.

[0035] In a specific implementation, when the analog-to-digital converter 13 quantizes the high-gain reset signal, the comparator circuit 131 is configured to compare the ramp voltage and the high-gain reset signal and output a first comparison signal; the counter 132 is configured to count down when the first comparison signal is received, and record the first counting result when the state of the first comparison signal flips (e.g., from high level to low level, or from low level to high level). In one specific embodiment, when the first comparison signal is 0, the counter stops counting and records the first counting result.

[0036] In a specific implementation, when the analog-to-digital converter circuit 13 quantizes the high-gain image signal, the comparator circuit 131 is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter 132 is configured to start counting upwards from the first counting result when the second comparison signal is received, and output the second counting result when the state of the second comparison signal flips, the second counting result being the difference between the quantization result of the high-gain image signal and the high-gain reset signal; the memory 133 is configured to store the second counting result and use the second counting result as the quantization value of the effective image signal under high gain.

[0037] In a specific implementation, when the analog-to-digital converter circuit 13 quantizes the low-gain image signal, the comparator circuit 131 is configured to compare the first composite signal and the reference signal and output the third comparison signal; the counter 132 is configured to count down when the third comparison signal is received, and record the third counting result when the state of the third comparison signal flips; the first composite signal is a coupled signal of the ramp voltage and the low-gain image signal.

[0038] In a specific implementation, when the analog-to-digital converter 13 quantizes the low-gain reset signal, the comparator circuit 131 is configured to compare the second composite signal and the reference signal and output a fourth comparison signal; the counter 132 is configured to start counting upwards from the third counting result when the fourth comparison signal is received, and output the fourth counting result when the state of the fourth comparison signal flips, the fourth counting result being the difference between the quantization results of the low-gain image signal and the low-gain reset signal; the memory 133 is configured to store the fourth counting result and use the fourth counting result as the quantization value of the effective image signal under low gain; the second composite signal is a coupled signal of the ramp voltage and the low-gain reset signal.

[0039] By using the comparison circuit 131, counter 132 and memory 133 connected in sequence, the low-gain image signal and the high-gain image signal are quantized in different ways, and the single analog-to-digital converter circuit 13 is quantized in a dual-conversion gain mode. This achieves the high dynamic range of the image sensor while reducing cost and size.

[0040] As an example and not a limitation, the reference voltage is adjustable.

[0041] The gain of the circuit in low conversion gain mode can be further improved by adjusting the reference voltage.

[0042] As an example rather than a limitation, the slope of the ramp voltage is adjustable.

[0043] During the quantization process of the output of pixel circuit 11, the slopes of its low conversion gain downslope voltage and high conversion gain downslope voltage can be set to be different, thus further improving the circuit gain and thereby further increasing the dynamic range of the image sensor.

[0044] This invention also provides a method for operating an image sensor readout circuit, including steps 101 to 102.

[0045] Step 101: Input the first switch control signal so that the switch selection circuit connects the ramp voltage to the first node, connects the high-gain reset signal and the high-gain image signal output sequentially under high gain of the pixel circuit to the second node respectively, and makes the analog-to-digital conversion circuit quantize the high-gain reset signal and the high-gain image signal respectively to obtain the effective image signal quantization value under high gain.

[0046] Step 102: Input the second switch control signal so that the switch selection circuit connects the ramp voltage and the low-gain image signal and low-gain reset signal output sequentially by the pixel circuit under low gain to the first node, and connects the reference voltage to the second node; and causes the analog-to-digital conversion circuit to quantize the low-gain image signal and low-gain reset signal to obtain the effective image signal quantization value under low gain.

[0047] When the analog-to-digital conversion circuit includes the comparator circuit, the counter, and the memory, step 100 includes steps A1 and B1.

[0048] Step A1: The comparison circuit compares the ramp voltage and the high-gain reset signal, and outputs a first comparison signal.

[0049] Step B1: When the counter receives the first comparison signal, it counts down, and when the state of the first comparison signal flips, it records the first counting result.

[0050] When the analog-to-digital conversion circuit includes the comparator circuit, the counter, and the memory, step 101 includes steps A2, B2, and C2.

[0051] Step A2: The comparison circuit compares the ramp voltage and the high-gain image signal and outputs a second comparison signal.

[0052] Step B2: When the counter receives the second comparison signal, it starts counting upward from the first counting result, and when the state of the second comparison signal flips, it outputs the second counting result, which is the difference between the quantization result of the high-gain reset signal and the high-gain image signal.

[0053] Step C2: The memory is configured to store the second counting result and use the second counting result as the effective image signal quantization value under the high gain.

[0054] When the analog-to-digital conversion circuit includes the comparator circuit, the counter, and the memory, step 102 includes steps A3 and B3.

[0055] Step A3: The comparison circuit compares the first composite signal and the reference signal, and outputs a third comparison signal.

[0056] Step B3: When the counter receives the third comparison signal, it counts down, and when the state of the third comparison signal flips, it records the third counting result.

[0057] The first composite signal is the coupled signal of the ramp voltage and the low-gain image signal.

[0058] When the analog-to-digital conversion circuit includes the comparator circuit, the counter, and the memory, step 103 includes steps A4, B4, and C4.

[0059] Step A4: The comparison circuit compares the second composite signal and the reference signal, and outputs a fourth comparison signal.

[0060] Step B4: The counter is configured to start counting upwards from the third counting result when the fourth comparison signal is received, and to output the fourth counting result when the state of the fourth comparison signal flips. The fourth counting result is the difference between the quantization results of the low-gain image signal and the low-gain reset signal.

[0061] Step C4: The memory is configured to store the fourth counting result and use the fourth counting result as the effective image signal quantization value under low gain.

[0062] The second composite signal is a coupled signal of the ramp voltage and the low-gain reset signal.

[0063] When the analog-to-digital conversion circuit includes the comparator circuit, the counter, and the memory, step 99 is also included before step 100 and between steps 101 and 102.

[0064] Step 99: Clear the comparison circuit.

[0065] Figure 3 An example circuit structure of an image sensor readout circuit provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0066] Pixel circuit 11 includes a reset transistor RST, a dual-conversion gain transistor DCG, a transmission transistor TX, a source follower transistor SF, a row selection transistor RS, a photoelectric conversion element PD, and a dual-conversion gain capacitor Cdcg.

[0067] The drain of the reset transistor RST and the drain of the source follower transistor SF are connected to the first power supply PIXVDD. The source of the reset transistor RST is connected to the first terminal of the dual conversion gain capacitor Cdcg and the drain of the dual conversion gain transistor DCG. The source of the dual conversion gain transistor DCG, the gate of the source follower transistor SF, and the source of the transmission transistor TX are connected to the floating diffusion point FD. The drain of the transmission transistor TX is connected to the negative terminal of the photoelectric conversion element PD. The source of the source follower transistor SF is connected to the drain of the row selection transistor RS. The source of the row selection transistor RS serves as the output terminal of the pixel circuit 11 to output a high-gain image signal, a low-gain image signal, a high-gain reset signal, and a low-gain reset signal. The gate of the reset transistor RST is connected to the reset signal rst. The gate of the dual conversion gain transistor DCG is connected to the conversion gain control signal dcg. The gate of the row selection transistor RS is connected to the row selection signal rowsel. The gate of the transmission transistor TX is connected to the control signal tx. The second terminal of the dual conversion gain capacitor Cdcg is connected to the second power supply VC. The positive terminal of the photoelectric conversion element PD is connected to the power supply ground.

[0068] The comparator circuit 131 includes a comparator U1, a first reset switch cmp_az1, and a second reset switch cmp_az2;

[0069] The non-inverting input terminal Vinp of comparator U1 and the first terminal of the first reset switch cmp_az1 are connected to the first node. The inverting input terminal Vinn of comparator U1 and the first terminal of the second reset switch cmp_az2 are connected to the second node. The first non-inverting output terminal Vop1 of comparator U1 is connected to the second terminal of the first reset switch cmp_az1. The first inverting output terminal Von1 of comparator U1 is connected to the second terminal of the second reset switch cmp_az2. The output terminal Vout of comparator U1 serves as the output terminal of comparator circuit 131.

[0070] By setting the first reset switch cmp_az1 and the second reset switch cmp_az2, the comparator U1 is reset in a timely manner, which improves the accuracy of the comparator circuit 131.

[0071] The switch selection circuit 12 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first high-gain switch SH1, a first low-gain switch SL1, and a second low-gain switch SL2.

[0072] The first terminal of the first high-gain switch SH1 and the first terminal of the first low-gain switch SL1 together serve as the high-gain image signal input terminal, the high-gain reset signal input terminal, the low-gain image signal input terminal, and the low-gain reset signal input terminal of the switch selection circuit 12. The second terminal of the first low-gain switch SL1 is connected to the first terminal of the third capacitor C3. The first terminal of the second capacitor C2 is connected to the ramp voltage. The second terminals of the third capacitor C3 and the second terminals of the second capacitor C2 are connected to the first node. The second terminal of the first high-gain switch SH1 is connected to the first terminal of the first capacitor C1. The first terminal of the second low-gain switch SL2 is connected to the reference voltage. The second terminals of the first capacitor C1 and the second terminals of the second low-gain switch SL2 are connected to the second node.

[0073] Both the third capacitor C3 and the second capacitor C2 can be variable capacitors. Adjusting the variable capacitors can further improve the circuit gain.

[0074] The switch selection circuit 12 also includes a second high-gain switch SH2;

[0075] The first terminal of the second high-gain switch SH2 is connected to the ramp voltage, and the second terminal of the second high-gain switch SH2 is connected to the first terminal of the third capacitor C3.

[0076] The gain of the circuit is further adjusted by coupling the ramp voltage to the first node through multiple ports.

[0077] The following is based on the working principle. Figure 3 Further explanation is provided below:

[0078] Figure 4 yes Figure 3 The timing diagram of the image sensor readout circuit is shown.

[0079] At time t0, the row selection signal rowsel is set to high level, the row selection transistor RS is turned on, the high gain control signal SH is set to high, the first high gain switch SH1 and the second high gain switch SH2 are turned on, the low gain control signal SL is set to low, the first low gain switch SL1 and the second low gain switch SL2 are turned off, the output terminal pixout of pixel circuit 11 and the inverting input terminal Vinn of comparator U1 are connected; the ramp voltage vramp and the non-inverting input terminal Vinp of comparator U1 are connected.

[0080] At time t1, the clear control signal cmp_az is set high, the first clear switch cmp_az1 and the second clear switch cmp_az2 are turned on, the non-inverting input terminal Vinp of comparator U1 and the first-stage non-inverting output terminal Vop1 of comparator U1 are shorted together, and the inverting input terminal Vinn of comparator U1 and the first-stage inverting output terminal Von1 of comparator U1 are shorted together, and comparator U1 begins to clear.

[0081] At time t2, the reset signal rst is set to low level, and the conversion gain control signal dcg is set to low level, thus obtaining a high-gain reset signal.

[0082] At time t3, the zeroing control signal cmp_az is set low, and the first zeroing switch cmp_az1 and the second zeroing switch cmp_az2 are disconnected.

[0083] At time t4, the ramp voltage vramp begins to decrease, and counter 132 begins counting downwards. The ramp voltage vramp and the high-gain reset signal pixout are coupled to the non-inverting input Vinp and the inverting input Vinn of comparator U1, respectively, through capacitors. When the ramp voltage vramp and the high-gain reset signal pixout overlap, comparator U1 outputs 0, counter 132 stops counting, and the quantized result of the high-gain reset signal (first count result) is obtained.

[0084] At time t5, the high-gain reset signal quantization ends, and the ramp voltage vramp returns to the reference state.

[0085] Between t6 and t7, the control signal tx is set to a high level, the transmission transistor TX is turned on, and the image signal is transmitted. The output terminal pixout of the pixel circuit 11 is coupled to the inverting input terminal Vinn of the comparator U1 through a capacitor to obtain a high-gain image signal.

[0086] At time t8, the ramp voltage vramp begins to decrease, and counter 132 begins to count upwards. The ramp voltage vramp and the high-gain image signal pixout are coupled to the non-inverting input Vinp and the inverting input Vinn of comparator U1 through capacitors. When the ramp voltage vramp and the high-gain image signal pixout overlap, the comparator outputs 0, and counter 132 stops counting, obtaining the difference between the high-gain image signal and the high-gain reset signal, which is the quantized value of the effective image signal under high gain.

[0087] At time t9, the high-gain image signal quantization ends, and the ramp voltage vramp begins to return to the reference state.

[0088] At time t10, the conversion gain control signal dcg is set to high level, the dual conversion gain transistor DCG is turned on, the high gain control signal SH is set to low, the first high gain switch SH1 and the second high gain switch SH2 are turned off, the low gain control signal SL is set to high, the first low gain switch SL1 and the second low gain switch SL2 are turned on, the image sensor readout circuit switches to low conversion gain mode, the ramp voltage vramp and the output terminal pixout of the pixel circuit 11 are coupled to the non-inverting input terminal Vinp of the comparator U1 through a capacitor, and the reference voltage vref is connected to the inverting input terminal Vinn of the comparator U1.

[0089] At time t11, the control signal tx is set to high level, the clear control signal cmp_az is set to high, the transmission transistor TX is turned on, and the transmission of the remaining image signal begins; the first clear switch cmp_az1 and the second clear switch cmp_az2 are turned on, the non-inverting input terminal Vinp of comparator U1 and the first-stage non-inverting output terminal Vop1 of comparator U1 are shorted together, the inverting input terminal Vinn of comparator U1 and the first-stage inverting output terminal Von1 of comparator U1 are shorted together, and comparator U1 begins clearing again.

[0090] At time t12, the control signal tx is set to low level, and the transmission transistor TX is turned off.

[0091] At time t13, the zeroing control signal cmp_az is set low, and the first zeroing switch cmp_az1 and the second zeroing switch cmp_az2 are disconnected.

[0092] At time t13, the ramp voltage vramp begins to decrease, and counter 132 begins counting downwards. The ramp voltage vramp and the low-gain image signal pixout are coupled to the non-inverting input Vinp of comparator U1 through a capacitor. A ramp voltage (first composite signal) is generated at the non-inverting input Vinp of comparator U1, which is a combination of the ramp voltage vramp and the low-gain image signal pixout. Meanwhile, the inverting input Vinn of comparator U1 is connected to the reference voltage vref. When the first composite signal and the reference voltage vref overlap, comparator U1 outputs 0, counter 132 stops counting, and the quantization result of the low-gain image signal (third counting result) is obtained.

[0093] At time t14, the low-gain image signal quantization ends, and the ramp voltage vramp returns to the reference state.

[0094] At time t15, the reset signal rst is set to high level, and pixel circuit 11 outputs a low-gain reset signal.

[0095] At time t16, the ramp voltage vramp begins to decrease, and counter 132 begins to count upwards. The ramp voltage vramp and the low-gain reset signal pixout are coupled to the non-inverting input Vinp of comparator U1 through a capacitor. A ramp voltage (second composite signal) is generated at the non-inverting input Vinp of comparator U1, which is a combination of the ramp voltage vramp and the low-gain reset signal pixout. Meanwhile, the inverting input Vinn of comparator U1 is connected to the reference voltage vref. When the second composite signal and the reference voltage vref overlap, comparator U1 outputs 0, counter 132 stops counting, and the difference between the low-gain image signal and the low-gain reset signal is obtained, which is the quantized value of the effective image signal under low gain.

[0096] At time t17, the high-gain reset signal quantization ends, and the ramp voltage vramp begins to return to the reference state.

[0097] The quantization of pixel circuit 11 ends, and the quantized values ​​of effective image signal under low gain and high gain are obtained. Then, the value of counter 132 is written into memory 133.

[0098] Among them, "overlapping" means that the two are equal and overlap.

[0099] In this embodiment of the invention, a switch selection circuit is connected to the pixel circuit of an image sensor. The pixel circuit sequentially outputs a high-gain reset signal, a high-gain image signal, a low-gain image signal, and a low-gain reset signal. In a first state, the switch selection circuit connects a ramp voltage to a first node and sequentially connects the reset signal and image signal output by the pixel circuit at high conversion gain to a second node. In a second state, the ramp voltage and the coupled signal of the reset signal or image signal output by the pixel circuit at low conversion gain are connected to the first node, while a reference voltage is connected to the second node. An analog-to-digital converter (ADC) is connected to the first and second nodes, quantizing the high-gain image signal to obtain the quantized value of the effective image signal at high gain, and quantizing the low-gain reset signal and the low-gain image signal to obtain the quantized value of the effective image signal at low gain. By connecting the low-gain image signal and the high-gain image signal to the ADC in different ways through the switch selection circuit for quantization processing, a dual-conversion-gain mode of quantization with a single ADC circuit is achieved. This reduces cost and size while achieving a high dynamic range for the image sensor. Since there is no need to sample and hold the output of the pixel circuit to improve the KT / C noise of the circuit, the noise level of the circuit will be lower, further improving the performance of the image sensor.

[0100] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0101] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An image sensor readout circuit, characterized by, The image sensor readout circuit has two states, and comprises: A switch selection circuit is connected with pixel circuits of the image sensor, and the pixel circuits are configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal and a low-gain reset signal; the switch selection circuit is configured to, in a first state, connect a ramp voltage to a first node, and sequentially connect the reset signal and the image signal output by the pixel circuits under a high conversion gain to a second node; the switch selection circuit is further configured to, in a second state, connect the ramp voltage and a coupling signal of the reset signal or the image signal output by the pixel circuits under a low conversion gain to the first node, and connect a reference voltage to the second node; An analog-to-digital conversion circuit is connected with the first node and the second node, and is configured to quantize the high-gain reset signal and the high-gain image signal to obtain effective image signal quantization values under a high gain, and quantize the low-gain reset signal and the low-gain image signal to obtain effective image signal quantization values under a low gain; The image sensor readout circuit quantizes a dual conversion gain mode through a single analog-to-digital conversion circuit.

2. The image sensor readout circuit of claim 1, wherein, The analog-to-digital conversion circuit comprises a comparison circuit, a counter and a memory connected in sequence; The comparison circuit comprises a comparator, a non-inverting input terminal of the comparator being connected with the first node, and an inverting input terminal of the comparator being connected with the second node.

3. The image sensor readout circuit of claim 2, wherein, When the analog-to-digital conversion circuit quantizes the high-gain reset signal, the comparison circuit is configured to compare the ramp voltage and the high-gain reset signal, and output a first comparison signal; the counter is configured to count down when receiving the first comparison signal, and record a first count result when a state of the first comparison signal is reversed; when the analog-to-digital conversion circuit quantizes the high-gain image signal, the comparison circuit is configured to compare the ramp voltage and the high-gain image signal, and output a second comparison signal; the counter is configured to count up from the first count result when receiving the second comparison signal, and output a second count result when a state of the second comparison signal is reversed, the second count result being a difference between high-gain image signal quantization results and high-gain reset signal quantization results; the memory is configured to store the second count result, and take the second count result as the effective image signal quantization value under the high gain; When the analog-to-digital conversion circuit quantizes the low-gain image signal, the comparison circuit is configured to compare a first composite signal and the reference voltage, and output a third comparison signal; the counter is configured to count down when receiving the third comparison signal, and record a third count result when a state of the third comparison signal is reversed; wherein the first composite signal is a coupling signal of the ramp voltage and the low-gain image signal. When the analog-to-digital conversion circuit quantizes the low-gain reset signal, the comparison circuit is configured to compare a second composite signal and the reference voltage and output a fourth comparison signal; the counter is configured to start counting up from the third counting result when receiving the fourth comparison signal, and output a fourth counting result when the state of the fourth comparison signal is reversed, the fourth counting result being a difference between the low-gain image signal and the low-gain reset signal quantization result; the memory is configured to store the fourth counting result and take the fourth counting result as the low-gain valid image signal quantization value; wherein the second composite signal is a coupling signal of the ramp voltage and the low-gain reset signal.

4. The image sensor readout circuit of claim 2, wherein, The comparison circuit comprises the comparator, a first clear switch and a second clear switch. The non-inverting input terminal of the comparator and the first terminal of the first clear switch are connected to the first node, the inverting input terminal of the comparator and the first terminal of the second clear switch are connected to the second node, the first non-inverting output terminal of the comparator is connected with the second terminal of the first clear switch, the first inverting output terminal of the comparator is connected with the second terminal of the second clear switch, and the output terminal of the comparator serves as the output terminal of the comparison circuit.

5. The image sensor readout circuit of claim 1, wherein, The switch selection circuit comprises a first capacitor, a second capacitor, a third capacitor, a first high-gain switch, a first low-gain switch and a second low-gain switch. The first terminal of the first high-gain switch and the first terminal of the first low-gain switch jointly serve as a high-gain image signal input terminal of the switch selection circuit, a high-gain reset signal input terminal of the switch selection circuit, a low-gain image signal input terminal of the switch selection circuit and a low-gain reset signal input terminal of the switch selection circuit, the second terminal of the first low-gain switch is connected with the first terminal of the third capacitor, the first terminal of the second capacitor is connected to the ramp voltage, the second terminal of the third capacitor and the second terminal of the second capacitor are connected to the first node, the second terminal of the first high-gain switch is connected with the first terminal of the first capacitor, the first terminal of the second low-gain switch is connected to the reference voltage, and the second terminal of the first capacitor and the second terminal of the second low-gain switch are connected to the second node.

6. The image sensor readout circuit of claim 5, wherein, The second capacitor and the third capacitor are variable capacitors.

7. The image sensor readout circuit of claim 5, wherein, The switch selection circuit further comprises a second high-gain switch. The first terminal of the second high-gain switch is connected to the ramp voltage, and the second terminal of the second high-gain switch is connected with the first terminal of the third capacitor.

8. The image sensor readout circuit of claim 1, wherein, The reference voltage is adjustable.

9. The image sensor readout circuit of claim 1, wherein, The slope of the ramp voltage is adjustable.

10. An image sensor, characterized by The image sensor comprises: a pixel circuit configured to sequentially output a high-gain reset signal, a high-gain image signal, a low-gain image signal and a low-gain reset signal; and a readout circuit of the image sensor as claimed in any one of claims 1 to 9. 11.An electronic device comprising the image sensor as claimed in claim 10. The image sensor comprises:

12. A method of operating a readout circuit for an image sensor as claimed in any one of claims 1-9, characterized by, ​ inputting a first switch control signal to make the switch selection circuit connect the ramp voltage to the first node, connect the high-gain reset signal and the high-gain image signal outputted by the pixel circuit in turn under high gain to the second node, and make the analog-to-digital conversion circuit quantize the high-gain reset signal and the high-gain image signal respectively to obtain a high-gain valid image signal quantization value; inputting a second switch control signal to make the switch selection circuit connect the ramp voltage and the low-gain image signal and the low-gain reset signal outputted by the pixel circuit in turn under low gain to the first node, connect a reference voltage to the second node, and make the analog-to-digital conversion circuit quantize the low-gain image signal and the low-gain reset signal respectively to obtain a low-gain valid image signal quantization value; The working method quantizes the dual conversion gain mode by a single analog-to-digital conversion circuit.

13. The method of operating a readout circuit for an image sensor as defined in claim 12, wherein, When the analog-to-digital conversion circuit comprises a comparison circuit, a counter and a memory, the steps of quantizing the high-gain reset signal, the high-gain image signal, the low-gain image signal and the low-gain reset signal by the analog-to-digital conversion circuit comprise: the comparison circuit compares the ramp voltage and the high-gain reset signal and outputs a first comparison signal; the counter counts down when receiving the first comparison signal, and records a first count result when the state of the first comparison signal flips; the comparison circuit compares the ramp voltage and the high-gain image signal and outputs a second comparison signal; the counter counts up from the first count result when receiving the second comparison signal, and outputs a second count result when the state of the second comparison signal flips, the second count result being a difference between the high-gain reset signal and the high-gain image signal quantization result; the memory is configured to store the second count result and take the second count result as the high-gain valid image signal quantization value; the comparison circuit compares a first composite signal and the reference voltage and outputs a third comparison signal; the counter counts down when receiving the third comparison signal, and records a third count result when the state of the third comparison signal flips; The first composite signal is a coupling signal of the ramp voltage and the low-gain image signal. the comparison circuit compares a second composite signal and the reference voltage and outputs a fourth comparison signal; the counter is configured to count up from the third count result when receiving the fourth comparison signal, and outputs a fourth count result when the state of the fourth comparison signal flips, the fourth count result being a difference between the low-gain image signal and the low-gain reset signal quantization result; the memory is configured to store the fourth count result and take the fourth count result as the low-gain valid image signal quantization value; The second composite signal is a coupling signal of the ramp voltage and the low-gain reset signal.

14. The method of operating a readout circuit for an image sensor as defined in claim 12, wherein, When the analog-to-digital conversion circuit includes a comparison circuit, a counter, and a memory, the analog-to-digital conversion circuit further includes, before the analog-to-digital conversion circuit quantizes the high-gain reset signal and before the analog-to-digital conversion circuit quantizes the low-gain image signal: clearing the comparison circuit.

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