Semiconductor device and power conversion device

Abstract

A semiconductor device is provided. A semiconductor substrate is divided into an inner region provided with an active region and an outer region surrounding the inner region. The semiconductor device includes: a semiconductor layer of a first conductivity type; a terminal well region of a second conductivity type selectively provided in an upper portion of the semiconductor layer so as to surround the inner region; an impurity region selectively provided in an upper portion of the terminal well region; a surface electrode; a back electrode; an insulating film provided so as to partially cover an upper portion of the terminal well region; an outer peripheral wiring layer at least partially provided on an upper portion of the insulating film to surround the inner region; and an interlayer insulating film covering at least the insulating film and the outer peripheral wiring layer. The surface electrode is provided from the inner region to an upper portion of the interlayer insulating film and is connected to the impurity region through a first contact hole penetrating the interlayer insulating film and reaching the impurity region. The outer peripheral wiring layer is provided to be located more outward from below an end portion of the surface electrode at an upper portion of the interlayer insulating film.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device having a surface protective film. Background Art

[0002] To ensure the breakdown voltage in a vertical semiconductor device used in a power device or the like, for example, as disclosed in Patent Document 1, a p-type protection ring region (terminal well region) is provided in a so-called terminal region in an n-type semiconductor layer.

[0003] In a semiconductor device having a protection ring region, an electric field generated when a reverse voltage is applied to a main electrode of the semiconductor device is mitigated by a depletion layer formed by a pn junction between an n-type semiconductor layer and the p-type protection ring region, and avalanche breakdown below the rated voltage or damage at an electrode end or the like can be avoided.

[0004] In the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) shown in Patent Document 1, a p-type impurity region is formed so as to protrude more toward the outer periphery than a surface electrode and a gate wiring layer. In such a semiconductor device such as a MOSFET, generally, except for a region where wire bonding is performed, a surface electrode is covered with a surface protective film such as polyimide. In addition, there is also a case where a surface electrode is sealed with a sealing material such as a gel.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: International Publication No. 2014 / 087600 Summary of the Invention

[0008] The above surface protective films such as polyimide and sealing materials such as gels tend to contain moisture in a high-humidity environment. The moisture contained in the surface protective film and the sealing material may have an adverse effect on the surface electrode. Specifically, there are cases where the surface electrode dissolves in the moisture or a precipitation reaction occurs due to the reaction between the moisture and the surface electrode.

[0009] The above-mentioned surface protective films such as polyimide and sealing materials such as gels are liable to contain moisture in a high-humidity environment. There is a possibility that this moisture has an adverse effect on the surface electrodes. Specifically, there are cases where the surface electrodes dissolve in the moisture or precipitation reactions occur due to the reaction between the moisture and the surface electrodes. In such cases, sometimes the surface electrodes and the surface protective films are broken, or the surface protective films are peeled off at the interface between the surface electrodes and the surface protective films. When the voids formed due to the breakage of the surface electrodes and the surface protective films or the peeling of the surface protective films function as leakage channels, there is a possibility that the insulation reliability of the semiconductor device is impaired.

[0010] The technology related to the present disclosure is completed to solve the above problems, and its object is to provide a semiconductor device with improved insulation reliability.

[0011] The semiconductor device related to the present disclosure has an active region through which a main current flows in the thickness direction of the semiconductor substrate. Among them, the semiconductor substrate is divided into an inner region provided with the active region and an outer region surrounding the inner region. The semiconductor device includes: a semiconductor layer of a first conductivity type; a terminal well region of a second conductivity type having a conductivity type different from that of the first conductivity type, selectively provided in the upper part of the semiconductor layer so as to surround the inner region in a top view; an impurity region of the first conductivity type or the second conductivity type, selectively provided in the upper part of the terminal well region; a surface electrode provided on the second main surface side opposite to the first main surface of the semiconductor substrate; a back electrode provided on the first main surface; an insulating film provided so as to partially cover the upper part of the terminal well region; an outer peripheral wiring layer, at least a part of which is provided on the upper part of the insulating film and surrounds the inner region in a top view; and an interlayer insulating film that covers at least the insulating film and the outer peripheral wiring layer. The terminal well region extends from the boundary between the inner region and the outer region to the outer region. The surface electrode is provided from the inner region to the upper part of the interlayer insulating film and is connected to the impurity region through a first contact hole that penetrates the interlayer insulating film and reaches the impurity region. The outer peripheral wiring layer is provided such that the outer peripheral end on the outer peripheral side, which is the side opposite to the inner region in a top view, is located more inward than the outer peripheral end of the terminal well region on the side opposite to the inner region in a top view, and is located more outward from below the end of the surface electrode on the upper part of the interlayer insulating film.

[0012] According to the semiconductor device related to the present disclosure, it is possible to suppress the generation of precipitates at the end of the surface electrode in the terminal region as the outer region, and the breakage or peeling of the surface electrode is suppressed. As a result, it is possible to suppress the increase in leakage current and gas discharge caused by the breakage or peeling of the surface electrode, and improve the insulation reliability of the semiconductor device. Brief Description of the Drawings

[0013] Figure 1 FIG. is a partial cross-sectional view showing the structure of the semiconductor device according to Embodiment 1 of the present disclosure.

[0014] Figure 2 FIG. is a top view showing the structure of the semiconductor device according to Embodiment 1 of the present disclosure.

[0015] Figure 3 FIG. is a partial cross-sectional view showing the structure of the semiconductor device according to Embodiment 1 of the present disclosure.

[0016] Figure 4 FIG. is a partial cross-sectional view showing the structure of a modified example of the semiconductor device according to Embodiment 1 of the present disclosure.

[0017] Figure 5 FIG. is a partial cross-sectional view showing the structure of a modified example of the semiconductor device according to Embodiment 1 of the present disclosure.

[0018] Figure 6 FIG. is a partial cross-sectional view showing the structure of a modified example of the semiconductor device according to Embodiment 1 of the present disclosure.

[0019] Figure 7 FIG. is a top view showing the structure of a modified example of the semiconductor device according to Embodiment 1 of the present disclosure.

[0020] Figure 8 FIG. is a partial cross-sectional view showing the structure of a modified example of the semiconductor device according to Embodiment 1 of the present disclosure.

[0021] Figure 9 FIG. is a partial cross-sectional view showing the structure of a modified example of the semiconductor device according to Embodiment 1 of the present disclosure.

[0022] Figure 10 FIG. is a diagram for explaining the region where the depletion layer reaches the upper surface of the epitaxial substrate.

[0023] Figure 11 FIG. is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0024] Figure 12 FIG. is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0025] Figure 13 FIG. is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0026] Figure 14It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0027] Figure 15 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0028] Figure 16 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0029] Figure 17 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0030] Figure 18 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 1 of the present disclosure.

[0031] Figure 19 It is a top view showing the structure of the semiconductor device according to Embodiment 2 of the present disclosure.

[0032] Figure 20 It is a partial cross-sectional view showing the structure of the semiconductor device according to Embodiment 2 of the present disclosure.

[0033] Figure 21 It is a partial cross-sectional view showing the structure of a modified example of the semiconductor device according to Embodiment 2 of the present disclosure.

[0034] Figure 22 It is a partial cross-sectional view showing the structure of a modified example of the semiconductor device according to Embodiment 2 of the present disclosure.

[0035] Figure 23 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0036] Figure 24 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0037] Figure 25 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0038] Figure 26 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0039] Figure 27 It is a partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0040] Figure 28 Partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0041] Figure 29 Partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0042] Figure 30 Partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0043] Figure 31 Partial cross-sectional view showing the manufacturing process of the semiconductor device according to Embodiment 2 of the present disclosure.

[0044] Figure 32 Block diagram showing the structure of a power conversion system of a power conversion device according to Embodiment 3 of the present disclosure. Detailed Description

[0045] <Preface>

[0046] In the following description, the "active region" of a semiconductor device refers to the region through which the main current flows in the on state of the semiconductor device, and the "terminal region" of the semiconductor device refers to the region around the active region. Further, hereinafter, the "outer side" of the semiconductor device refers to the direction from the central portion of the semiconductor device toward the peripheral portion, and the "inner side" of the semiconductor device refers to the direction opposite to the "outer side". Further, in the following description, regarding the conductivity type of impurities, the n-type is defined as the "first conductivity type", and the p-type, which is the conductivity type opposite to the n-type, is defined as the "second conductivity type". However, the "first conductivity type" may be defined as the p-type and the "second conductivity type" may be defined as the n-type, vice versa.

[0047] In addition, a term such as "MOS" was previously used for a metal-oxide-semiconductor junction structure, and the first letters of Metal-Oxide-Semiconductor were adopted. However, especially in a field effect transistor having a MOS structure (hereinafter simply referred to as "MOS transistor"), from the viewpoints of recent integration and improvement of manufacturing processes, etc., the materials of the gate insulating film and the gate electrode have been improved.

[0048] For example, in a MOS transistor, mainly from the viewpoint of self-matching formation of source / drain, polysilicon is used as the material of the gate electrode instead of metal. Further, from the viewpoint of improving electrical characteristics, a material having a high dielectric constant is used as the material of the gate insulating film, but this material is not necessarily limited to an oxide.

[0049] Therefore, terms such as "MOS" are not necessarily used only in the context of a metal-oxide-semiconductor stack structure, and such a limitation is not assumed in this specification. That is, in view of common technical knowledge, here "MOS" has the meaning of not only an abbreviation based on its etymology but also widely including a conductor-insulator-semiconductor stack structure.

[0050] In addition, in the following description, even if it is described as "on (upper surface) of ~" and "covering ~", it does not prevent the presence of spacers between components. For example, even if it is described as "B provided on (upper surface) of A" or "B covering A", there may be a case where another component C is provided between A and B. In addition, in the following description, terms such as "upper", "lower", "side", "bottom", "front" or "back" that indicate specific positions and directions are sometimes used, but these terms are appropriately used to make the content of the embodiments easy to understand and are not related to the actual implementation direction.

[0051] Furthermore, the drawings are schematic diagrams, and for ease of explanation, structural omissions or simplifications are appropriately made in the drawings. In addition, the mutual relationships of the sizes and positions of the structures etc. shown in different drawings are not necessarily correctly described and can be appropriately changed. Also, in drawings such as top views that are not cross-sectional views, hatching is sometimes added to make the content of the embodiments easy to understand.

[0052] In addition, in the following description, it is assumed that the same reference numerals are attached to the same components and shown, and their names and functions are also the same. Therefore, in order to avoid repetition, the detailed description of them is sometimes omitted.

[0053] In addition, in the following description, when it is described as "comprising", "including" or "having" a certain component etc., unless otherwise specified, it is not an exclusive expression excluding the existence of other components.

[0054] In addition, in the following description, there are also cases where ordinal numbers such as "first" or "second" are used. These terms are only examples appropriately used to make the content of the embodiments easy to understand and are not limited to the order etc. that can be generated by these ordinal numbers.

[0055] In addition, in the following description, expressions indicating an equal state, such as "identical", "equal", "uniform" or "homogeneous", etc., unless otherwise specified, include cases indicating a strictly equal state and cases where differences occur within the tolerance or within the range where the same degree of function can be obtained.

[0056] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, detailed features and the like are also shown for technical explanations, but these are examples, and not all of these are necessarily essential features for the embodiments to be implemented.

[0057] <Embodiment 1>

[0058] Hereinafter, the structure, operation, and manufacturing method of the semiconductor device of Embodiment 1 will be described.

[0059] <Regarding the structure of the semiconductor device>

[0060] Figure 1 FIG. is a partial cross-sectional view showing the structure of MOSFET 100 as the semiconductor device according to Embodiment 1. Figure 2 FIG. is a top view of MOSFET 100. In addition, Figure 2 the cross-sectional view in the arrow direction of line A-A in Figure 1 corresponds to Figure 2 In Figure 1 for ease of explanation, the surface protective film 6 (upper surface film) in the upper surface structure of MOSFET 100 is omitted. Also, in

[0061] In addition, Figure 3 FIG. is a cross-sectional view showing the structure of unit cell UC, which is the minimum unit structure of MOSFET 100, formed in the inner region RI of the active region shown in Figure 1 In the inner region RI of MOSFET 100, a plurality of Figure 3 the unit cells UC shown in Figure 1 are arranged, and the structure shown at the left end of

[0062] is the outermost peripheral unit cell UC in the inner region RI. Figure 1 As shown in

[0063] MOSFET 100 is formed on an epitaxial substrate 30 composed of a single-crystalline substrate 31 and an epitaxial layer 32 formed on the upper surface of the single-crystalline substrate 31. The single-crystalline substrate 31 is a semiconductor substrate made of n-type (first conductivity type) silicon carbide (SiC), and the epitaxial layer 32 is an n-type semiconductor layer made of SiC epitaxially grown on the upper surface of the single-crystalline substrate 31. That is, MOSFET 100 is a SiC-MOSFET. In addition, in this Embodiment 1, the epitaxial substrate 30 is a SiC substrate having a 4H polytype.In the upper part of the epitaxial layer 32 in the active region, i.e., the inner region RI, a p-type (second conductivity type) device well region 9 is selectively formed. Further, in the upper part of the device well region 9, an n-type source region 11 and a p-type contact region 19 having an impurity concentration higher than that of the device well region 9 are selectively formed, respectively.

[0064] In the upper part of the epitaxial layer 32 in the terminal region, i.e., the outer region RO surrounding the inner region RI, a p-type terminal well region 2 is selectively formed. The terminal well region 2 is a frame-shaped (ring-shaped) region surrounding the active region in a plan view and functions as a so-called guard ring.

[0065] In the upper part of the terminal well region 2, a p-type high-concentration region 20 having a relatively high impurity concentration is selectively formed so as to surround the active region. Here, the high-concentration region 20 is not limited to p-type and can also be set to n-type. By providing the high-concentration region 20, the contact resistance can be reduced.

[0066] The n-type region of the epitaxial layer 32 other than the above-described device well region 9, source region 11, contact region 19, and terminal well region 2 is a drift layer 1 through which current drifts.

[0067] The impurity concentration of the drift layer 1 is lower than the impurity concentration of the single crystal substrate 31. Therefore, the single crystal substrate 31 has a resistivity lower than that of the drift layer 1. Here, the impurity concentration of the drift layer 1 becomes, for example, 1×10 14 / cm 3 or more and 1×10 17 / cm 3 or less.

[0068] The terminal well region 2 is formed in the upper part of the epitaxial layer 32 so as to extend from the boundary between the inner region RI and the outer region RO to the outer region RO. Further, with the inner (inner peripheral side) end (inner peripheral end) of the terminal well region 2 as a boundary, the region inside it is defined as the inner region RI, and the region outside it is defined as the outer region RO.

[0069] In addition, as Figure 1 shown, on the upper surface S2 (second main surface) of the epitaxial substrate 30 in the active region, a gate insulating film 12 is formed so as to straddle the upper part of the source region 11, the device well region 9 sandwiched between the source region 11 and the drift layer 1, and the drift layer 1. Moreover, a gate electrode 3 is formed on the upper surface of the gate insulating film 12. The upper part of the device well region 9 covered with the gate insulating film 12 and the gate electrode 3, i.e., the part of the device well region 9 sandwiched between the source region 11 and the drift layer 1, is a channel region where an inversion channel is formed when the MOSFET 100 is in an on state.

[0070] In the active region, the gate electrode 3 is covered with the interlayer insulating film 14, and the source electrode 51 is formed on the upper surface of the interlayer insulating film 14. Therefore, the gate electrode 3 and the source electrode 51 are electrically insulated from each other by the interlayer insulating film 14. In addition, the interlayer insulating film 14 has an elemental composition of, for example, boron or phosphorus.

[0071] In addition, the gate insulating film 12 and the gate electrode 3 are also formed to straddle the terminal well region 2 in the outer region RO and the element well region 9 and the drift layer 1 that are sandwiched by the source region 11 and the drift layer 1 in the outermost peripheral unit cell UC in the inner region RI, and are led out to the outer region RO. The gate insulating film 12 and the gate electrode 3 are covered with the interlayer insulating film 14. The gate electrode 3 led out to the outer region RO is connected to the gate electrode 3 provided in the active region.

[0072] The interlayer insulating film 14 covers the field insulating film 4 so as to extend to the outside of the terminal well region 2.

[0073] In addition, as Figure 1 shown, on the upper surface S2 of the epitaxial substrate 30 in the terminal region, a field insulating film 4 having a film thickness thicker than that of the gate insulating film 12 is provided. The field insulating film 4 covers a part of the terminal well region 2 and extends beyond the outer peripheral end of the terminal well region 2 to the outside of the terminal well region 2. In addition, the field insulating film 4 is not provided in the inner region RI. In other words, the field insulating film 4 has an opening portion including the inner region RI in a plan view.

[0074] At the inner edge portion of the opening of the field insulating film 4, an outer peripheral wiring layer 13 is formed so as to be carried from the upper surface of the gate insulating film 12 to the upper surface of the field insulating film 4, and is disposed above the terminal well region 2 with the gate insulating film 12 or the field insulating film 4 interposed therebetween. The outer peripheral wiring layer 13 and the gate insulating film 12 are covered with the interlayer insulating film 14.

[0075] In addition, as Figure 1 shown, a part of the outer peripheral wiring layer 13 is formed to extend by 1 μm or more from below the outer peripheral edge portion of the source electrode 51 further outward.

[0076] Contact holes CH1 that penetrate the interlayer insulating film 14 and the gate insulating film 12 to reach the source region 11 and the contact region 19 and contact holes CH11 (first contact holes) that penetrate the interlayer insulating film 14 and the gate insulating film 12 to reach the high-concentration region 20 are provided. The source electrode 51 is connected to the source region 11 and the contact region 19 via the contact hole CH1, and is connected to the high-concentration region 20 via the contact hole CH11.

[0077] The source electrode 51 and the contact region 19 form an ohmic contact via the contact hole CH1. In addition, the source electrode 51 and the high-concentration region 20 form an ohmic contact or a Schottky contact via the contact hole CH11.

[0078] In addition, as Figure 1 shown, on the lower surface S1 (the first main surface) of the epitaxial substrate 30, a back electrode 8 that functions as a drain electrode is formed.

[0079] The outer peripheral wiring layer 13, as Figure 2 shown, extends further to the outer terminal region beyond the outer periphery of the source electrode 51 and substantially surrounds the source electrode 51. The source electrode 51 is arranged to extend from a slit portion provided on one side of the substantially rectangular source electrode 51 in a plan view to a position more than half of the source electrode 51, and the gate wiring 52w enters here. That is, a gate portion 52 is provided where the gate pad 52p enters a recess provided on one side of the source electrode 51 and the gate wiring 52w enters a slit portion continuous with the recess. The gate portion 52 is formed to be surrounded by the source electrode 51 except for a part in a plan view. In addition, the source electrode 51 and the gate portion 52 are collectively referred to as the surface electrode 50.

[0080] The gate wiring 52w is electrically connected to the gate electrode 3 led out from the active region via a contact hole (not shown), and supplies a gate control signal to the gate electrode 3 of the active region.

[0081] The gate portion 52, that is, the gate pad 52p and the gate wiring 52w function as electrodes that receive a gate control signal for controlling an electrical path between the source electrode 51 and the back electrode 8. The gate portion 52, as Figure 2 shown, is separated from the source electrode 51 and is also electrically insulated from the source electrode 51.

[0082] In addition, in Figure 1 , a surface protective film 6 is formed so as to cover the source electrode 51 and the interlayer insulating film 14 that is exposed without being covered by the source electrode 51. However, the surface protective film 6 has an opening portion at the upper part of the source electrode 51 and the gate portion 52 ( Figure 2 ), and has a structure that can electrically connect the source electrode 51 and the gate portion 52 to the outside.

[0083] <Modification 1>

[0084] Figure 4 is a cross-sectional view showing the structure of the MOSFET 101 as a modification of Embodiment 1. In addition, in Figure 4 , the same reference numerals are added to the same structures as those of the MOSFET 100 described using Figure 1 , and the repeated description is omitted.

[0085] As shown Figure 4 in FIG. 1, the MOSFET 101 has a p-type low-concentration well region 21 provided in an upper portion of a drift layer 1 on a more outer peripheral side than a terminal well region 2. The low-concentration well region 21 is provided as a multi-frame-shaped region surrounding the terminal well region 2 in a plan view, but is not limited to being multi-frame-shaped and can also be a single-frame-shaped region. The impurity concentration of the low-concentration well region 21 is equal to or lower than the impurity concentration of the terminal well region 2.

[0086] <Modified Example 2>

[0087] Figure 5 FIG. 2 is a cross-sectional view showing the structure of a MOSFET 102 as a modified example of Embodiment 1. In addition, in Figure 5 FIG. 2, the same reference numerals are assigned to the same structures as those of the MOSFET 100 described with reference to Figure 1 FIG. 1, and redundant descriptions are omitted.

[0088] As shown Figure 5 in FIG. 2, in the MOSFET 102, a field insulating film 4 is provided to extend near an inner edge portion of the terminal well region 2, and a gate electrode 3 led out to an outer region RO is formed to be carried on the inner edge portion of the field insulating film 4.

[0089] A source electrode 51 is connected in such a manner as to form an ohmic contact or a Schottky contact with a high-concentration region 20 through a contact hole CH12 that passes through an interlayer insulating film 14 and the field insulating film 4 and reaches the high-concentration region 20. An outer peripheral wiring layer 13 is provided on the field insulating film 4 on a more outer side than the contact hole CH12.

[0090] <Modified Example 3>

[0091] Figure 6 FIG. 3 is a cross-sectional view showing the structure of a MOSFET 103 as a modified example of Embodiment 1. In addition, in Figure 6 FIG. 3, the same reference numerals are assigned to the same structures as those of the MOSFET 100 described with reference to Figure 1 FIG. 1, and redundant descriptions are omitted.

[0092] As shown Figure 6 in FIG. 3, in the MOSFET 103, a field insulating film 4 is provided to extend near an inner edge portion of the terminal well region 2, and a gate electrode 3 led out to an outer region RO is formed to be carried on the field insulating film 4 and extend near the outer peripheral wiring layer 13.

[0093] The source electrode 51 is connected in such a manner as to form an ohmic contact or a Schottky contact with the high-concentration region 20 through a contact hole CH12 that reaches the high-concentration region 20 via the interlayer insulating film 14 and the field insulating film 4. On the field insulating film 4 outside the gate electrode 3 extending beyond the contact hole CH12, an outer peripheral wiring layer 13 is provided leaving the gate electrode 3.

[0094] <Modified Example 4>

[0095] Figure 7 This is a top view showing the structure of the MOSFET 104 as a modified example of Embodiment 1. In addition, in Figure 7 regards, the same structures as those of the MOSFET 100 described using Figure 2 are given the same reference numerals, and redundant descriptions are omitted.

[0096] As Figure 7 shown, in the MOSFET 104, the gate portion 52 composed of the gate pad 52p and the gate wiring 52w is provided so as to be surrounded entirely by the source electrode 51 in a top view, and the outer peripheral wiring layer 13 is provided so as to surround the outer periphery of the source electrode 51.

[0097] By adopting such a structure, it is possible to suppress the precipitation of insulating substances at the outer peripheral end portions of the source electrode 51 over the entire circumference of the terminal region, and it is possible to suppress the breakage and peeling of the source electrode 51 and the surface protective film 6, thereby improving the insulation reliability of the semiconductor device.

[0098] <Modified Example 5>

[0099] Figure 8 This is a cross-sectional view showing the structure of the MOSFET 105 as a modified example of Embodiment 1. In addition, in Figure 8 regards, the same structures as those of the MOSFET 100 described using Figure 1 are given the same reference numerals, and redundant descriptions are omitted.

[0100] As Figure 8 shown, in the MOSFET 105, a contact hole CH13 (second contact hole) that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 is provided above the outer peripheral wiring layer 13 on the field insulating film 4, and the source electrode 51 and the outer peripheral wiring layer 13 are connected via the contact hole CH13. In addition, the contact hole CH13 is not limited to one, and a plurality of them can be provided.

[0101] By adopting such a structure, by more effectively alleviating the electric field intensity at the outer peripheral end portions of the source electrode 51, the precipitation of insulating substances is suppressed, and it is possible to suppress the breakage and peeling of the source electrode and the upper surface film, thereby improving the insulation reliability of the semiconductor device.

[0102] <Modified Example 6>

[0103] Figure 9 This is a cross-sectional view showing the structure of the MOSFET 106 as a modified example of Embodiment 1. In addition, in Figure 9 , for the same structure as the MOSFET 100 described using Figure 1 , the same reference numerals are added, and repeated explanations are omitted.

[0104] As Figure 9 shown, in the MOSFET 106, a contact hole CH13 is formed that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 above the outer peripheral wiring layer 13 on the field insulating film 4, and the source electrode 51 and the outer peripheral wiring layer 13 are connected via the contact hole CH13. The contact hole CH13 is provided at the outermost peripheral portion of the source electrode 51, and the outermost periphery of the source electrode 51 and the outer peripheral wiring layer 13 are connected.

[0105] By adopting such a structure, by more effectively alleviating the electric field intensity at the outer peripheral end portion of the source electrode 51, the precipitation of the insulating substance is suppressed, the breakage and peeling of the source electrode and the upper surface film can be suppressed, and the insulation reliability of the semiconductor device can be improved.

[0106] <Operation of the semiconductor device>

[0107] Next, the operation of the MOSFET 100 of Embodiment 1 described using Figure 1 and Figure 2 will be described by dividing it into two states.

[0108] The first state is a state in which a positive voltage equal to or higher than the threshold value is applied to the gate electrode 3. Hereinafter, this state will be referred to as the "on state". When the MOSFET 100 is in the on state, an inversion channel is formed in the channel region. The inversion channel becomes a path for electrons as carriers to flow between the source region 11 and the drift layer 1. In the on state, when a high voltage is applied to the back electrode 8 with the potential of the source electrode 51 as a reference, a current flows through the single-crystalline substrate 31 and the drift layer 1. The voltage between the source electrode 51 and the back electrode 8 at this time is referred to as the "on voltage", and the current flowing between the source electrode 51 and the back electrode 8 is referred to as the "on current". The on current only flows through the active region where the channel exists and does not flow through the terminal region.

[0109] The second state is a state in which a voltage lower than the threshold value is applied to the gate electrode 3. Hereinafter, this state will be referred to as the "cut-off state". When the MOSFET 100 is in the cut-off state, an inversion channel is not formed in the channel region. Therefore, no conduction current flows. Therefore, when a high voltage is applied between the source electrode 51 and the back electrode 8, this high voltage is maintained. At this time, the voltage between the gate electrode 3 and the source electrode 51 is very small relative to the voltage between the source electrode 51 and the back electrode 8, so a high voltage is also applied between the gate electrode 3 and the back electrode 8.

[0110] In the cut-off state, even in the terminal region, a high voltage is applied between each of the source electrode 51, the gate part 52, and the gate electrode 3 and the back electrode 8. However, similarly to the electrical contact between the element well region 9 and the source electrode 51 formed in the active region, an electrical contact between the terminal well region 2 and the source electrode 51 is formed in the terminal region. Therefore, a high electric field is prevented from being applied to the gate insulating film 12, the field insulating film 4, and the interlayer insulating film 14.

[0111] When the MOSFET 100 is in the cut-off state, a high electric field is applied near the interface of the pn junction between the drift layer 1 and the element well region 9 and between the drift layer 1 and the terminal well region 2. The voltage to the back electrode 8 when this electric field reaches the critical electric field and causes avalanche breakdown is defined as the maximum voltage (avalanche voltage) of the MOSFET 100. Usually, the rated voltage is determined so that the MOSFET 100 is used in a voltage range where avalanche breakdown does not occur.

[0112] In the cut-off state of the MOSFET 100, the depletion layer is directed from the pn junction interface between the drift layer 1 and the element well region 9 and between the drift layer 1 and the terminal well region 2 toward the direction of the single crystal substrate 31, that is, Figure 1 the downward direction in Figure 1 and the direction toward the outer periphery of the drift layer 1, that is, from the

[0113] inner region RI to the outer region RO in

[0114] In a semiconductor device using, as a material, SiC or the like having a particularly high electric field strength in the off state, when the end of the electrode material is located at a region where the upper surface of the epitaxial layer 32 is depleted, applying a high electric field to the end of the electrode material may sometimes cause damage to the electrode material. Therefore, in the MOSFET 100 according to the first embodiment, the impurity concentration of the terminal well region 2 is set to an impurity concentration at which the upper surface of the terminal well region 2 under the source electrode 51 and the gate portion 52 is not depleted.

[0115] Here, consider the case where the MOSFET 100 is in the off state under high humidity. The sealing resin provided to cover the semiconductor chip may contain moisture. For example, when the surface protective film 6 (upper surface film) is made of a resin material having high water absorbency such as polyimide, the surface protective film 6 contains a large amount of moisture under high humidity, and there is a possibility that the moisture reaches the upper surfaces of the epitaxial layer 32 and the source electrode 51. In addition, when the surface protective film 6 is made of a material having high moisture resistance such as SiN, there is a possibility that cracks are likely to occur in the surface protective film 6 due to stress generated in the process, and the epitaxial layer 32 and the source electrode 51 are exposed to moisture through the cracks.

[0116] In such a state, by the voltage applied to the off-state MOSFET 100, at the terminal region, the end of the epitaxial layer 32 functions as an anode, and the source electrode 51 functions as a cathode. Near the source electrode 51 that becomes the cathode, due to moisture, the following oxygen reduction reaction represented by formula (1) and hydrogen generation reaction represented by formula (2) occur.

[0117] O2 + 2H2O + 4e - → 4OH - …(1)

[0118] H2O + e - → OH - + 1 / 2H2…(2)

[0119] Accompanying this, near the source electrode 51, the concentration of hydroxide ions increases. The hydroxide ions chemically react with the source electrode 51. For example, when the source electrode 51 is made of aluminum, aluminum sometimes becomes aluminum hydroxide through the above chemical reaction.

[0120] The reaction between aluminum and hydroxide ions is accelerated according to the surrounding electric field strength. Inside the semiconductor layer, a potential gradient is generated in the depleted region. Therefore, in the MOSFET 100 according to the first embodiment, in the region where the depletion layer reaches the upper surface of the epitaxial substrate 30, a potential gradient is generated along the upper surface S2.

[0121] Figure 10This is a diagram showing the region where the depletion layer reaches the upper surface of the epitaxial substrate 30, and equipotential lines are represented by dashed lines. In Figure 10 In the region where a potential difference is formed at the boundary between the epitaxial layer 32 and the field insulating film 4 is the region where the depletion layer reaches the upper surface of the epitaxial substrate 30, depending on whether the impurity concentration in the terminal well region 2 is closer to the inside or the outside.

[0122] As Figure 10 shown, equipotential lines are formed in a form substantially orthogonal to the interface between the epitaxial layer 32 and the field insulating film 4, so potential gradients are also formed in the field insulating film 4 and the interlayer insulating film 14, and an electric field is generated around the end of the source electrode 51. Thus, when the electric field strength at the end of the source electrode 51 becomes a certain level or more, a reaction for generating aluminum hydroxide is caused, and this reaction is accelerated as the electric field strength increases.

[0123] In addition, due to the resistance generated in the contact region between the source electrode 51 and the terminal well region 2, the sheet resistance of the terminal well region 2, and the diffusion potential of the pn junction formed by the high-concentration region 20 and the terminal well region 2 when the high-concentration region 20 is n-type, when the potential of the terminal well region 2 is higher than that of the source electrode 51, the electric field strength at the lower part of the source electrode 51 increases.

[0124] Furthermore, when the concentration in the terminal well region 2 is low and the depletion layer extending from the pn junction interface between the drift layer 1 and the terminal well region 2 reaches the upper surface S2 within the terminal well region 2, a potential gradient is generated along the upper surface S2 within the terminal well region 2. At this time, the region with a high potential on the upper surface S2 approaches the source electrode 51, and the electric field strength at the lower part of the source electrode 51 further increases.

[0125] In such a case, particularly at the outer peripheral end of the lower part of the source electrode 51, electric field concentration is likely to occur, and the generation of aluminum hydroxide is accelerated.

[0126] When the interlayer insulating film 14 contains boron (B) or phosphorus (P), as the concentration increases, the interlayer insulating film 14 is likely to absorb moisture. For example, when the concentration of boron exceeds 2% and the concentration of phosphorus exceeds 5%, this tendency becomes significant, and the generation of aluminum hydroxide is accelerated.

[0127] As described above, when aluminum hydroxide is generated on the surface of the source electrode 51, due to volume expansion, the source electrode 51 and the surface protective film 6 are broken or peeled off, and voids are formed on the upper surface of the interlayer insulating film 14. Since moisture enters these voids and an excessive leakage current flows or gas discharge occurs in these voids, there is a possibility of causing damage to the MOSFET 100.

[0128] In contrast, in the MOSFET 100 according to the first embodiment, asFigure 1 As shown in the cross-sectional view of , the outer peripheral end of the source electrode 51 is located further inward than the outer peripheral end of the termination well region 2 , so the electric field intensity around the source electrode 51 is relaxed.

[0129] Here, if the impurity concentration of the termination well region 2 is set to a certain level or above, the depletion layer in the termination well region 2 hardly expands, and the depletion layer can be effectively alleviated. Figure 2 The electric field strength around the gate pad 52p is shown. Therefore, the generation of aluminum hydroxide can be effectively suppressed.

[0130] Furthermore, if Figure 4 As shown, as in MOSFET101, by providing a low-concentration well region 21 in the upper portion of the drift layer 1 which is closer to the periphery than the terminal well region 2, the region on the upper surface S2 which becomes a high potential is further away from the source electrode 51, thereby effectively alleviating the electric field strength around the source electrode 51 and alleviating the electric field strength of the epitaxial layer 32 around the peripheral end of the terminal well region 2, thereby increasing the avalanche voltage of MOSFET101.

[0131] Furthermore, in the MOSFET 100 according to the first embodiment, as shown in FIG. Figure 1 As shown in the cross-sectional view of FIG, a peripheral wiring layer 13 is formed below the outer peripheral end of the source electrode 51. The peripheral wiring layer 13 establishes a potential between the source electrode 51 and the termination well region 2, and the region at this potential is positioned further outward from the source electrode 51. This mitigates the electric field concentration around the outer peripheral end of the source electrode 51 caused by the potential difference between the source electrode 51 and the termination well region 2.

[0132] Thus, in the MOSFET 100 according to the first embodiment, the peripheral wiring layer 13 exists below the peripheral end portion of the source electrode 51 where the electric field is easily concentrated, thereby alleviating the electric field concentration at the peripheral end portion below the source electrode 51 and suppressing the generation of aluminum hydroxide.

[0133] Furthermore, the peripheral wiring layer 13 is formed to extend 1 μm or more outward from the outer peripheral end of the source electrode 51 , thereby effectively alleviating electric field concentration around the outer peripheral end of the source electrode 51 and suppressing the generation of aluminum hydroxide.

[0134] Furthermore, when the peripheral wiring layer 13 is formed in the entire region below the outer peripheral end of the source electrode 51 , electric field concentration can be alleviated in the entire region below the outer peripheral end of the source electrode 51 , thereby suppressing the generation of aluminum hydroxide.

[0135] In addition, if Figure 8The MOSFET 105 shown can make the potential of the peripheral wiring layer 13 the same as that of the source electrode 51 by connecting the source electrode 51 and the peripheral wiring layer 13 through a contact hole CH13 that penetrates the interlayer insulating film 14 above the peripheral wiring layer 13. Thereby, the potential difference generated between the source electrode 51 and the terminal well region 2 is generated only inside the gate insulating film 12 and the field insulating film 4, and the potential difference in the interlayer insulating film 14 between the source electrode 51 and the peripheral wiring layer 13 can be reduced. Therefore, the electric field concentration at the lower part of the outer peripheral end of the source electrode 51 can be more effectively alleviated, and the generation of aluminum hydroxide can be suppressed.

[0136] In addition, as Figure 9 shown, the MOSFET 106 can sufficiently suppress the electric field concentration at the lower part of the outer peripheral end of the source electrode 51 and suppress the generation of aluminum hydroxide by connecting the source electrode 51 and the peripheral wiring layer 13 through a contact hole CH13 that penetrates the interlayer insulating film 14 at the outermost peripheral position of the source electrode 51.

[0137] As described above, in the MOSFET 100 according to the first embodiment and its modified examples, the generation of aluminum hydroxide at the outer peripheral end of the source electrode 51 is suppressed. As a result, an increase in leakage current and gas discharge caused by the breakage or peeling of the source electrode 51 and the surface protective film 6 can be suppressed, and the insulation reliability can be improved.

[0138] <Regarding the manufacturing method of a semiconductor device>

[0139] Next, the manufacturing method of the MOSFET 100 according to the first embodiment will be described using Figures 11 - 18 , which is a sectional view showing the manufacturing process in sequence. In addition, hereinafter, the description of the manufacturing method of the MOSFET 101 shown in Figure 4 will be used instead of the description of the manufacturing method of the MOSFET 100.

[0140] First, a low-resistance single-crystal substrate 31 containing n-type impurities at a relatively high concentration (n + ) is prepared. The single-crystal substrate 31 is a SiC substrate having a 4H polytype and has a deviation angle of 4 degrees or 8 degrees.

[0141] Next, on the single-crystal substrate 31, epitaxial growth of SiC is performed to form an n-type epitaxial layer 32 having an impurity concentration of 1×10 14 / cm 3 or more and 1×10 17 / cm 3 or less, thereby obtaining the Figure 11 shown epitaxial substrate 30.

[0142] Next, by combining the formation of a resist mask using a photolithography process and an ion implantation process in which the resist mask is used as an implantation mask, a process of repeatedly forming impurity regions in the upper portion of the epitaxial layer 32 is performed. As shown in Figure 11 FIG. 1, a terminal well region 2, an element well region 9, a contact region 19, a high-concentration region 20, a source region 11, and a low-concentration well region 21 are formed in the upper portion of the epitaxial layer 32.

[0143] In the ion implantation, N (nitrogen) or P is used as an n-type impurity, and Al or B is used as a p-type impurity. The element well region 9 and the terminal well region 2 can be formed together in the same ion implantation process. In addition, the high-concentration region 20 of the contact region 19 and the terminal well region 2 can be formed together in the same ion implantation process.

[0144] The impurity concentration of the element well region 9 becomes 1.0×10 18 / cm 3 or more and 1.0×10 20 / cm 3 or less.

[0145] The impurity concentration of the source region 11 and the impurity concentration of the contact region 19 are higher than the impurity concentration of the element well region 9, and are set to, for example, 1.0×10 19 / cm 3 or more and 1.0×10 21 / cm 3 or less.

[0146] In the terminal well region 2, in order to ensure the amount of impurities such that the depletion layer hardly extends into the terminal well region 2 in the cut-off state, the dose of the terminal well region 2 is preferably 2.0×10 13 / cm 2 or more, and is set to, for example, 5.0×10 13 / cm 2 .

[0147] The dose of the low-concentration well region 21 preferably becomes 0.5×10 13 / cm 2 or more and 5×10 13 [[ID=?]] / cm 2 or less, and is set to, for example, 1.0×10 13 / cm 2 .

[0148] The implantation energy of the ion implantation is, for example, 100 keV or more and 700 keV or less when the impurity is Al. In this case, the impurity concentration of the low-concentration well region 21 converted according to the above dose [cm -2 becomes 1×10 17 / cm 3 It should be noted that there seems to be a formatting issue in the original text where "5×10 13 [[ID=?]] / cm " has an unclear "?". The translation is done based on the best understanding of the context.Above and 1×10 19 / cm 3 Below. Additionally, when the impurity is N, the implantation energy of ion implantation is set to, for example, 20 keV or more and 300 keV or less.

[0149] After that, using a heat treatment apparatus, annealing treatment is performed at a temperature of 1500 °C or more. Thereby, the impurities added by ion implantation are activated.

[0150] Next, for example, by chemical vapor deposition (CVD: chemical vapor deposition) method, a SiO2 film with a thickness of 0.5 μm or more and 2 μm or less is formed on the upper surface S2 of the epitaxial substrate 30. Moreover, by patterning the SiO2 film using a photolithography process and an etching process, as Figure 12 shown, the field insulating film 4 is formed. At this time, the field insulating film 4 is patterned into a shape that covers a part of the terminal well region 2, extends beyond the end of the terminal well region 2, and reaches the outer peripheral side of the terminal well region 2.

[0151] Next, in the Figure 13 shown process, by thermally oxidizing the upper surface of the epitaxial layer 32 not covered by the field insulating film 4, a SiO2 film OX1 serving as the gate insulating film 12 is formed. Moreover, on the upper surface of the SiO2 film OX1, a conductive polysilicon film PS1 is formed by reduced-pressure CVD method.

[0152] Next, in the Figure 14 shown process, by patterning the polysilicon film PS1 using a photolithography process and an etching process, the gate electrode 3 is formed. At this time, by forming a resist mask according to a predetermined layout, the peripheral wiring layer 13 can be formed simultaneously in the terminal region. Next, a SiO2 film OX2 serving as the interlayer insulating film 14 is formed by CVD method.

[0153] The peripheral wiring layer 13 is formed in such a way that a part or all of it is carried onto the upper surface of the field insulating film 4, and the outer peripheral end of the peripheral wiring layer 13 is formed on the inner peripheral side relative to the outer peripheral end of the terminal well region 2.

[0154] In addition, the peripheral wiring layer 13 is not limited to a polysilicon film, and can be formed by sputtering method, evaporation method, etc. by forming a metal film such as Ti (titanium), Ni (nickel), Au (gold) with a lower ionization tendency than the source electrode 51 and patterning it.

[0155] Additionally, it is also possible as Figure 5 shown in the MOSFET102 and Figure 6The MOSFET 103 shown is provided with a field insulating film 4 in the vicinity of the edge portion extending to the inside of the terminal well region 2, and a gate electrode 3 leading to the outer region RO is formed in such a manner as to reach the edge portion inside the field insulating film 4.

[0156] Next, in Figure 15 the process shown, contact holes CH1 reaching the contact region 19 and the source region 11 and a contact hole CH11 reaching the high-concentration region 20 are formed through the photolithography process and the etching process to penetrate the SiO2 films OX2 and OX1. Thereby, the SiO2 film OX1 becomes the gate insulating film 12, and the SiO2 film OX2 becomes the interlayer insulating film 14.

[0157] In addition, by forming a contact hole CH13 penetrating the interlayer insulating film 14 and reaching the outer peripheral wiring layer 13 on the outer peripheral side of the contact hole CH11, Figure 8 and Figure 9 the MOSFETs 105 and 106 shown can be obtained.

[0158] The interlayer insulating film 14 can also be formed of BPSG (boron phosphorus silicate glass) in which B and P are doped into SiO2 or a multilayer film including SiO2, SiN, BPSG, etc. For example, by annealing treatment at 1000 °C, the shape of the step becomes smooth. Thereby, the embedding property of the electrode into the contact hole is improved, so that a fine structure can also be formed.

[0159] Next, in Figure 16 the process shown, a material layer ML1 of a surface electrode 50 such as a source electrode 51 and a gate portion 52 including a gate pad 52p and a gate wiring 52w is formed on the upper surface S2 of the epitaxial substrate 30 by a sputtering method, an evaporation method, or the like.

[0160] In addition, in Figure 17 the process shown, a material layer ML2 of a back electrode 8 is formed on the lower surface S1 of the epitaxial substrate 30 by the same method as the material layer ML1.

[0161] In the formation of the material layer ML1, for example, a metal containing any one or more of Ti (titanium), Ni (nickel), Al, Cu (copper), Au (gold) or an Al alloy such as Al-Si is used. In the formation of the material layer ML2, for example, a metal containing any one or more of Ti, Ni, Al, Cu, Au is used. In addition, a silicide film can be formed in advance by heat treatment at the portion where the material layer ML1 and the material layer ML2 are in contact with the epitaxial substrate 30. In addition, the formation of the back electrode 8 can also be performed at the end of all processes.

[0162] Next, in the process shown in Figure 18

[0162] , the material layer ML1 is patterned through a photolithography process and an etching process to separate the source electrode 51 and the gate portion 52 (including the gate pad 52p and the gate wiring 52w) to form the surface electrode 50.

[0163] At this time, as shown in the cross-sectional view of Figure 1 Figure 1 , the source electrode 51 is formed in such a manner that the outer peripheral wiring layer 13 is located below the outer peripheral end portion of the source electrode 51. In addition, not limited to the portion of the A-A line of Figure 2 Figure 2 , the outer peripheral wiring layer 13 can be formed in all regions below the outer peripheral end portion of the source electrode 51.

[0164] Finally, by forming the surface protective film 6 so as to cover at least a part of the end portion of the surface electrode 50 and the outer side region RO of the epitaxial substrate 30, the MOSFET101 shown in Figure 4 Figure 4 can be obtained. In addition, if the low-concentration well region 21 is not formed in the process described in Figure 11 Figure 11 , the MOSFET100 shown in Figure 1 Figure 1 can be obtained.

[0165] The surface protective film 6 is processed into a desired shape, for example, through a polyimide coating process, a photolithography process, and an etching process. In addition, the surface protective film 6 can also be formed by depositing a SiN film using the CVD method and performing a photolithography process and an etching process.

[0166] As described above, according to the MOSFET100 according to the first embodiment, generation of aluminum hydroxide at the end portion of the source electrode 51 in the terminal region can be suppressed, and breakage or peeling of the source electrode 51 and the surface protective film 6 is suppressed. As a result, an increase in leakage current and gas discharge caused by breakage or peeling of the source electrode 51 and the surface protective film 6 can be suppressed, and the insulation reliability of the MOSFET100 can be improved.

[0167] <Embodiment 2>

[0168] Hereinafter, the structure, operation, and manufacturing method of the semiconductor device according to the second embodiment will be described. In addition, in the following description, the same reference numerals are assigned to the same structures as those of the MOSFET100 according to the first embodiment, and repeated descriptions are omitted.

[0169] <Regarding the structure of the semiconductor device>

[0170] Figure 19 is a top view showing the structure of the MOSFET200 as the semiconductor device according to the second embodiment. In addition, Figure 20 is along Figure 19The cross-sectional view taken along the arrow direction of line B-B in []. In addition, in Figure 19 for ease of explanation, the surface protective film 6 (upper surface film) in the upper surface structure of the MOSFET 200 is omitted.

[0171] In the MOSFET 200 according to the second embodiment, as Figure 19 and Figure 20 shown, in the terminal region, that is, the outer region RO, a gate wiring 52w connected to the gate pad 52p is provided so as to surround the source pad 51p except for the portion where the gate pad 52p is formed in a plan view. In addition, a source wiring 51w connected to the source pad 51p is provided so as to surround the gate pad 52p and the gate wiring 52w in a plan view. The source electrode 51 is composed of the source pad 51p and the source wiring 51w, and the gate portion 52 is composed of the gate pad 52p and the gate wiring 52w.

[0172] As Figure 20 shown, the high-concentration region 20 of the terminal well region 2 is provided so as to extend below the source wiring 51w, and the source wiring 51w is connected in such a manner that an ohmic contact or a Schottky contact is formed with the high-concentration region 20 through a contact hole CH3 that reaches the high-concentration region 20 of the terminal well region 2 via the through-field insulating film 4 and the interlayer insulating film 14.

[0173] In addition, as Figure 20 shown, in the MOSFET 200, the field insulating film 4 is provided so as to extend near the inner edge portion of the terminal well region 2, the gate electrode 3 led out to the outer region RO is formed to bear on the inner edge portion of the field insulating film 4, and then extends to the outer peripheral side. The gate wiring 52w is connected in such a manner that an ohmic contact or a Schottky contact is formed with the gate electrode 3 through a contact hole CH2 that reaches the gate electrode 3 via the through-interlayer insulating film 14.

[0174] The gate pad 52p and the gate wiring 52w do not necessarily need to be directly connected. For example, they can also be electrically connected via the gate electrode 3. Similarly, the source pad 51p and the source wiring 51w do not necessarily need to be directly connected. For example, they can also be electrically connected via the outer peripheral wiring layer 13.

[0175] In the MOSFET 200 according to the second embodiment, as Figure 20 shown, an outer peripheral wiring layer 13 is formed below the outer peripheral end portion of the source wiring 51w. In addition, the outer peripheral wiring layer 13 is formed to extend 1 μm or more further outward from below the outer peripheral end portion of the source wiring 51w. In addition, the outer peripheral wiring layer 13 can be formed in all regions below the outer peripheral end portion of the source wiring 51w.

[0176] In addition, in the MOSFET 200 according to the second embodiment, asFigure 20 As shown, an outer peripheral wiring layer 13 is formed below the inner peripheral end portion of the source wiring 51w. Further, the outer peripheral wiring layer 13 is formed to extend 1 μm or more further inward from below the inner peripheral end portion of the source wiring 51w. In addition, the outer peripheral wiring layer 13 can be formed in all regions below the inner peripheral end portion of the source wiring 51w.

[0177] <Modified Example 1>

[0178] Figure 21 is a cross-sectional view showing the structure of the MOSFET 201 as a modified example of Embodiment 2. In addition, in Figure 21 Regarding the same structure as the MOSFET 200 described using Figure 20 the same reference numerals are added, and repeated descriptions are omitted.

[0179] As Figure 21 shown, the MOSFET 201 has a p-type low-concentration well region 21 provided in the upper portion of the drift layer 1 on the outer peripheral side of the terminal well region 2. The low-concentration well region 21 is provided in a multi-frame-shaped region that surrounds the terminal well region 2 in a plan view, but is not limited to multi-frame and can also be a single frame-shaped region. The impurity concentration of the low-concentration well region 21 is equal to or lower than the impurity concentration of the terminal well region 2.

[0180] <Modified Example 2>

[0181] In addition, it is also possible to use the MOSFET 105 as a modified example of Embodiment 1 as Figure 8 shown, and a structure is provided in which a contact hole CH13 that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 is provided on the upper portion of the outer peripheral wiring layer 13 on the field insulating film 4, and the source wiring 51w and the outer peripheral wiring layer 13 are connected via the contact hole CH13. In addition, the contact hole CH13 is not limited to one, and a plurality of contact holes can be provided.

[0182] By adopting such a structure, by more effectively alleviating the electric field intensity of the source wiring 51w, suppressing the precipitation of insulating substances, it is possible to suppress the breakage and peeling of the source wiring 51w and the surface protective film 6, and improve the insulation reliability of the semiconductor device.

[0183] In addition, it is also possible to use the MOSFET 106 as a modified example of Embodiment 1 as Figure 9 shown, and a structure is provided in which a contact hole CH13 that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 is provided on the upper portion of the outer peripheral wiring layer 13, and the outermost periphery of the source wiring 51w and the outer peripheral wiring layer 13 are connected via the contact hole CH13.

[0184] By adopting such a structure, the electric field intensity at the outermost periphery of the source wiring 51w can be more effectively alleviated, the precipitation of insulating substances can be suppressed, the breakage and peeling of the source wiring 51w and the surface protective film 6 can be suppressed, and the insulation reliability of the semiconductor device can be improved.

[0185] Figure 22 FIG. is a cross-sectional view showing the structure of the MOSFET 202 as a modified example of Embodiment 2. In addition, in Figure 22 regards the same structures as those of the MOSFET 200 described in Figure 20 the same reference numerals are attached, and repeated descriptions are omitted.

[0186] As Figure 22 shown, in the MOSFET 202, a contact hole CH4 (third contact hole) that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 is provided at the position of the inner peripheral end portion of the source wiring 51w, and the source wiring 51w and the outer peripheral wiring layer 13 are connected at the innermost periphery of the source wiring 51w.

[0187] By adopting such a structure, the electric field intensity at the inner peripheral end portion of the source wiring 51w can be more effectively alleviated, the precipitation of insulating substances can be suppressed, the breakage and peeling of the source electrode or the upper surface film can be suppressed, and the insulation reliability of the semiconductor device can be improved.

[0188] In addition, contact holes CH4 can also be provided at the positions of the inner peripheral end portion and the outer peripheral end portion of the source wiring 51w.

[0189] <Regarding the operation of the semiconductor device>

[0190] Next, the operation of the MOSFET 200 of Embodiment 2 described using Figure 19 and Figure 20 is described.

[0191] In the MOSFET 200 according to the present Embodiment 2, similar to the MOSFET of Embodiment 1, it operates by being divided into a "conducting state" in which a positive voltage equal to or higher than the threshold is applied to the gate electrode 3 and a "cut-off state" in which a voltage lower than the threshold is applied to the gate electrode 3.

[0192] In a semiconductor device using a material such as SiC in which the electric field intensity is particularly high in the cut-off state, when the end portion of the electrode material is located in the surface depletion region of the epitaxial layer 32, a high electric field is also generated at the end portion of the electrode material, which may cause damage to the electrode material. Therefore, in the MOSFET 200 according to the present Embodiment 2, the impurity concentration of the terminal well region 2 is set to an impurity concentration at which depletion does not occur inside the terminal well region 2 under the normal source electrode 51 and the gate portion 52.

[0193] Here, consider the case where the MOSFET 100 is in the cut-off state under high humidity. The sealing resin provided to cover the semiconductor chip may contain moisture. For example, when the surface protective film 6 (upper surface film) is made of a resin material with high water absorbency such as polyimide, the surface protective film 6 contains a large amount of moisture under high humidity, and there is a possibility that this moisture reaches the upper surfaces of the epitaxial layer 32 and the source electrode 51. In addition, when the surface protective film 6 is made of a material with high moisture resistance such as SiN, there is a possibility that cracks are likely to occur in the surface protective film 6 due to stress generated during the process, etc., and the epitaxial layer 32 and the source electrode 51 are exposed to moisture through these cracks.

[0194] In such a state, by the voltage applied to the cut-off state MOSFET 200, in the terminal region, the end portion of the epitaxial layer 32 functions as an anode, and the source electrode 51 functions as a cathode. Near the source electrode 51 that becomes the cathode, the concentration of hydroxide ions increases as described in Embodiment 1. These hydroxide ions chemically react with the source electrode 51. For example, when the source electrode 51 is made of aluminum, the aluminum sometimes becomes aluminum hydroxide.

[0195] In the MOSFET 200 according to the present Embodiment 2, the source wiring 51w is closer to the end portion of the epitaxial layer 32 that becomes the anode than the source pad 51p, and aluminum hydroxide is likely to be generated in the source wiring 51w.

[0196] The reaction between aluminum and hydroxide ions is accelerated according to the surrounding electric field intensity. Inside the semiconductor layer, a potential gradient is generated in the depleted region, so in the MOSFET 200, in the region where the depletion layer reaches the upper surface of the epitaxial substrate 30, a potential gradient along the upper surface S2 is generated. This potential gradient is also formed in the field insulating film 4 and the interlayer insulating film 14 formed on the upper surface S2 of the epitaxial layer 32, so an electric field is generated around the outer peripheral end portion of the source wiring 51w. Thus, when the electric field intensity at the outer peripheral end portion of the source wiring 51w becomes a certain level or more, the generation reaction of aluminum hydroxide is caused, and this reaction is accelerated as the electric field intensity increases.

[0197] In addition, due to the potential difference between the source wiring 51w and the terminal well region 2 and the potential difference between the source wiring 51w and the gate wiring 52w, an electric field is generated around the inner peripheral end portion of the source wiring 51w. Thus, when the electric field intensity at the inner peripheral end portion of the source wiring 51w becomes a certain level or more, the generation reaction of aluminum hydroxide is caused, and this reaction is accelerated as the electric field intensity increases.

[0198] As described above, when aluminum hydroxide is formed on the surface of the source wiring 51w, the source wiring 51w and the surface protective film 6 are broken or peeled off due to volume expansion, and voids are formed on the upper surface of the interlayer insulating film 14. Since moisture enters these voids, an excessive leakage current flows or gas discharge occurs in these voids, which may cause damage to the MOSFET 200.

[0199] In contrast, in the MOSFET 200 according to the second embodiment, as Figure 20 shown in the cross-sectional view, the outer peripheral end portion of the source wiring 51w is located more on the inner peripheral side than the outer peripheral end portion of the terminal well region 2, so the electric field intensity around the source wiring 51w is alleviated.

[0200] Here, if the impurity concentration of the terminal well region 2 is made a certain level or more, the depletion layer hardly expands inside the terminal well region 2, and the electric field intensity around the source wiring 51w can be effectively alleviated. Therefore, the generation of aluminum hydroxide can be effectively suppressed.

[0201] Furthermore, as Figure 21 shown in the MOSFET 201, by providing the low-concentration well region 21 at the outer peripheral portion of the terminal well region 2, the electric field intensity around the source wiring 51w can be effectively alleviated, and the electric field intensity of the epitaxial layer 32 around the outer peripheral end portion of the terminal well region 2 can be alleviated, and the avalanche voltage of the MOSFET 200 can be increased.

[0202] Furthermore, in the MOSFET 200 according to the second embodiment, as Figure 20 shown in the cross-sectional view, an outer peripheral wiring layer 13 is formed below the outer peripheral end portion of the source wiring 51w, and an outer peripheral wiring layer 13 is formed below the inner peripheral end portion of the source wiring 51w. The outer peripheral wiring layer 13 becomes the potential between the source wiring 51w and the terminal well region 2, and the region having this potential is separated further to the outer peripheral side than the outer peripheral end portion of the source wiring 51w and further to the inner peripheral side than the inner peripheral end portion, so that the electric field concentration caused by the potential difference between the source wiring 51w and the terminal well region 2 is alleviated around the outer peripheral end portion and the inner peripheral end portion of the source wiring 51w.

[0203] Thus, in the MOSFET 200 according to the second embodiment, by providing the outer peripheral wiring layer 13 below the outer peripheral end portion and the inner peripheral end portion of the source wiring 51w where the electric field is particularly likely to concentrate, it is possible to alleviate the electric field concentration at the lower portions of the outer peripheral end portion and the inner peripheral end portion of the source wiring 51w and suppress the generation of aluminum hydroxide. In addition, by forming the outer peripheral wiring layer 13 to extend more than 1 μm toward the outer peripheral side than the outer peripheral end portion of the source wiring 51w and more than 1 μm toward the inner peripheral side than the inner peripheral end portion, the electric field concentration is effectively alleviated around the outer peripheral end portion and the inner peripheral end portion of the source wiring 51w, and the generation of aluminum hydroxide can be suppressed.

[0204] In addition, by adopting a structure such as the MOSFET 105 which is a modified example of the first embodiment as Figure 8 shown, where a contact hole CH13 that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 is provided on the upper portion of the outer peripheral wiring layer 13 on the field insulating film 4, and the source wiring 51w and the outer peripheral wiring layer 13 are connected via the contact hole CH13, the potential of the outer peripheral wiring layer 13 can be made the same as the potential of the source electrode 51. As a result, the potential difference generated between the source wiring 51w and the terminal well region 2 is generated only inside the gate insulating film 12 and the field insulating film 4, and the potential difference in the interlayer insulating film 14 between the source wiring 51w and the outer peripheral wiring layer 13 can be reduced. Therefore, the electric field concentration at the outer peripheral end portion of the lower portion of the source wiring 51w can be alleviated more effectively, and the generation of aluminum hydroxide can be suppressed.

[0205] In addition, as Figure 9 shown in the MOSFET 106, by connecting the source electrode 51 and the outer peripheral wiring layer 13 via the contact hole CH13 that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 at the outermost peripheral position of the source wiring 51w, the electric field concentration at the lower portion of the outer peripheral end portion of the source electrode 51 can be sufficiently suppressed, and the generation of aluminum hydroxide can be suppressed.

[0206] As described above, in the MOSFET 100 according to the first embodiment and its modified examples, the generation of aluminum hydroxide at the outer peripheral end portion of the source electrode 51 is suppressed. As a result, an increase in leakage current and gas discharge caused by breakage or peeling of the source electrode 51 and the surface protection film 6 can be suppressed, and the insulation reliability can be improved.

[0207] In addition, it is also possible to adopt a structure such as the MOSFET 106 which is a modified example of the first embodiment as Figure 9 shown, where the outermost periphery of the source wiring 51w and the outer peripheral wiring layer 13 are connected via the contact hole CH13 that penetrates the interlayer insulating film 14 and reaches the outer peripheral wiring layer 13 on the upper portion of the outer peripheral wiring layer 13. It is also possible to combine this structure and as Figure 22A structure in which the source wiring 51w is connected to the outermost peripheral wiring layer 13 by a contact hole CH4 that penetrates the interlayer insulating film 14 at a position on the inner peripheral end portion of the source wiring 51w as in the MOSFET 202 which is a modified example of Embodiment 2, as shown.

[0208] Thus, by connecting the source wiring 51w and the outermost peripheral wiring layer 13 via the contact hole at the outermost periphery and the innermost periphery of the source wiring 51w, it is possible to sufficiently suppress the electric field concentration at the outer peripheral end portion and the inner peripheral end portion at the lower part of the source wiring 51w and suppress the generation of aluminum hydroxide.

[0209] As described above, in the MOSFET 200 according to the present Embodiment 2, the generation of aluminum hydroxide at the end portion of the source wiring 51w is suppressed. As a result, it is possible to suppress an increase in leakage current and gas discharge caused by breakage or peeling of the source wiring 51w and the surface protective film 6, and improve the insulation reliability.

[0210] <Regarding the manufacturing method of the semiconductor device>

[0211] Next, the manufacturing method of the MOSFET 200 of Embodiment 2 will be described using Figures 23 - 31 , which is a cross-sectional view showing the manufacturing process in sequence. In addition, hereinafter, the description of the manufacturing method of the MOSFET 201 shown in Figure 21 will be used instead of the description of the manufacturing method of the MOSFET 200. In addition, regarding the same processes as the manufacturing method of the MOSFET 100 of Embodiment 1 described using Figures 1 - 18 , the description will be appropriately omitted.

[0212] First, a low-resistance single-crystal substrate 31 containing n-type impurities at a relatively high concentration (n + ) is prepared, and SiC epitaxial growth is performed on the single-crystal substrate 31 to form an epitaxial layer 32, thereby obtaining Figure 23 the epitaxial substrate 30 shown.

[0213] After that, by combining the formation of a resist mask using a photolithography process and an ion implantation process using the resist mask as an implantation mask, the process of repeatedly forming impurity regions in the upper part of the epitaxial layer 32 is performed. As shown in Figure 23 , a terminal well region 2, an element well region 9, a contact region 19, a high-concentration region 20, a source region 11, and a low-concentration well region 21 are formed in the upper part of the epitaxial layer 32.

[0214] Next, an SiO2 film is formed on the upper surface S2 of the epitaxial substrate 30 by using the CVD method, and the SiO2 film is patterned by using a photolithography process and an etching process. As shown in Figure 24The field insulating film 4 is formed as shown. At this time, the field insulating film 4 is patterned to cover a part of the terminal well region 2 and extend beyond the end of the terminal well region 2 to the outer peripheral side of the terminal well region 2.

[0215] Next, in Figure 25 the process shown, by thermally oxidizing the upper surface of the epitaxial layer 32 not covered by the field insulating film 4, a SiO2 film OX1 serving as the gate insulating film 12 is formed. After that, on the upper surface of the SiO2 film OX1, a conductive polysilicon film PS1 is formed by reduced-pressure CVD method.

[0216] Next, in Figure 26 the process shown, the polysilicon film PS1 is patterned by using a photolithography process and an etching process to form the gate electrode 3. At this time, by forming a resist mask according to a predetermined layout, the outer peripheral wiring layer 13 is simultaneously formed in the terminal region. The outer peripheral wiring layer 13 is further disposed on the outer peripheral side than the gate electrode 3 formed in such a manner that a part thereof is carried onto the upper surface of the field insulating film 4, and the outer peripheral end is formed in such a manner that it is located on the inner peripheral side than the outer peripheral end of the terminal well region 2.

[0217] Next, in Figure 27 the process shown, a SiO2 film OX2 serving as the interlayer insulating film 14 is formed by CVD method.

[0218] Next, in Figure 28 the process shown, contact holes CH1 reaching the contact region 19 and the source region 11 and contact holes CH11 reaching the high-concentration region 20 are formed by a photolithography process and an etching process through the SiO2 films OX2 and OX1. At the same time, on the outer peripheral side than the contact holes CH11, contact holes CH2 reaching the gate electrode 3 through the interlayer insulating film 14 and contact holes CH3 reaching the high-concentration region 20 through the interlayer insulating film 14 and the field insulating film 4 are formed. Thus, the SiO2 film OX1 becomes the gate insulating film 12, and the SiO2 film OX2 becomes the interlayer insulating film 14.

[0219] Next, in Figure 29 the process shown, on the upper surface S2 of the epitaxial substrate 30, a material layer ML1 of the surface electrode 50 including a source electrode 51 including a source pad 51p and a source wiring 51w, a gate portion 52 including a gate pad 52p and a gate wiring 52w, etc. is formed by sputtering method or evaporation method or the like.

[0220] In addition, in Figure 30 the process shown, a material layer ML2 of the back electrode 8 is formed on the lower surface S1 of the epitaxial substrate 30 by the same method as the material layer ML1.

[0221] Next, inFigure 31 In the process shown, through a photolithography process and an etching process, the material layer ML1 is patterned to separate the source electrode 51 (including the source pad 51p and the source wiring 51w) and the gate portion 52 (including the gate pad 52p and the gate wiring 52w), thereby forming the surface electrode 50.

[0222] At this time, as Figure 20 shown in the cross-sectional view, the source wiring 51w is formed in such a manner that the outer peripheral wiring layer 13 is located below the outer peripheral end portion and the inner peripheral portion of the source wiring 51w. In addition, not limited to Figure 20 the portion of the B-B line shown, the outer peripheral wiring layer 13 can be formed in all regions below the outer peripheral end portion and the inner peripheral end portion of the source wiring 51w.

[0223] By adopting such a structure, precipitation of insulating substances at the outer peripheral end portion and the inner peripheral end portion of the source wiring 51w can be suppressed throughout the entire circumference of the terminal region, rupture and peeling of the source wiring 51w and the surface protective film 6 can be suppressed, and the insulation reliability of the semiconductor device can be improved.

[0224] Finally, by forming the surface protective film 6 so as to cover at least a part of the end portion of the surface electrode 50 and the outer side region RO of the epitaxial substrate 30, the Figure 21 MOSFET201 shown can be obtained. In addition, if the low-concentration well region 21 is not formed in the process described using Figure 23 , the Figure 20 MOSFET200 shown can be obtained.

[0225] As described above, according to the MOSFET200 according to the second embodiment, generation of aluminum hydroxide at the end portion of the source wiring 51w in the terminal region can be suppressed, and rupture or peeling of the source wiring 51w and the surface protective film 6 is suppressed. As a result, an increase in leakage current and gas discharge caused by rupture or peeling of the source wiring 51w and the surface protective film 6 can be suppressed, and the insulation reliability of the MOSFET200 can be improved.

[0226] <Other examples of the material of the semiconductor substrate>

[0227] In the semiconductor devices of the first and second embodiments described above, an example in which SiC is used as the material of the epitaxial substrate 30 is shown, but not limited thereto. As the material of the epitaxial substrate 30, other wide-bandgap semiconductors such as gallium nitride (GaN) can also be used.

[0228] In addition, although a MOSFET is exemplified as the semiconductor device of Embodiments 1 and 2, the present disclosure is not limited thereto, and can also be applied to transistors other than MOSFETs, such as JFETs (Junction FETs) or IGBTs (Insulated Gate Bipolar Transistors).

[0229] <Other examples of transistors>

[0230] In addition, regarding the MOSFET 100 of Embodiment 1 and the MOSFET 200 of Embodiment 2, although planar transistors are exemplified, the present disclosure can also be applied to trench transistors.

[0231] <Embodiment 3>

[0232] A power conversion device and a method for manufacturing the power conversion device according to Embodiment 3 will be described. Embodiment 3 is an example in which the semiconductor devices according to Embodiments 1 and 2 described above are applied to a power conversion device. In the following description, the same reference numerals are assigned to the same components as those described in Embodiments 1 and 2, and the detailed description thereof will be appropriately omitted.

[0233] <Regarding the structure of the power conversion device>

[0234] The power conversion device to which the present disclosure is applied is not limited to a specific use, but hereinafter, the case of applying it to a three-phase inverter will be described.

[0235] Figure 32 FIG. is a block diagram schematically showing the structure of a power conversion system including the power conversion device 2200 according to Embodiment 3.

[0236] Figure 32 The shown power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply that supplies DC power to the power conversion device 2200. The power supply 2100 can be constituted by various examples, such as a DC system, a solar cell, or a storage battery. In addition, the power supply 2100 can also be constituted by a rectifier circuit or an AC-DC converter connected to an AC system. In addition, the power supply 2100 can also be constituted by a DC-DC converter that converts the DC power output from the DC system into predetermined power.

[0237] The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts the DC power supplied from the power supply 2100 into AC power and supplies the AC power to the load 2300.

[0238] In addition, as shown in Figure 32 , the power conversion device 2200 includes: a conversion circuit 2201 that converts DC power into AC power and outputs it; a drive circuit 2202 that outputs drive signals for driving respective switching elements of the conversion circuit 2201; and a control circuit 2203 that outputs control signals for controlling the drive circuit 2202 to the drive circuit 2202. Figure 32 As shown, it has: a conversion circuit 2201 that converts DC power into AC power and outputs it; a drive circuit 2202 that outputs drive signals for driving respective switching elements of the conversion circuit 2201; and a control circuit 2203 that outputs control signals for controlling the drive circuit 2202 to the drive circuit 2202.

[0239] The load 2300 is a three-phase motor driven by the AC power supplied from the power conversion device 2200. In addition, the load 2300 is not limited to a specific use, and is a motor mounted on various electrical devices, for example, used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0240] Hereinafter, the power conversion device 2200 will be described in detail. The conversion circuit 2201 includes switching elements and freewheeling diodes (not shown). Moreover, by performing switching operations of the switching elements, the DC power supplied from the power supply 2100 is converted into AC power and then supplied to the load 2300.

[0241] Specific circuit configurations of the conversion circuit 2201 have various examples, but the conversion circuit 2201 according to the third embodiment is a two-level three-phase full-bridge circuit, and can be composed of six switching elements and six freewheeling diodes connected in anti-parallel with respective switching elements.

[0242] Among the respective switching elements in the conversion circuit 2201, any of the semiconductor devices in the above-described first and second embodiments is applied. Regarding the six switching elements, every two switching elements are connected in series to form upper and lower branches, and respective upper and lower branches form respective phases (U phase, V phase, and W phase) of the full-bridge circuit. Moreover, output terminals of respective upper and lower branches, that is, three output terminals of the conversion circuit 2201 are connected to the load 2300.

[0243] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201 and supplies the drive signals to control electrodes of the switching elements of the conversion circuit 2201. Specifically, according to control signals output from the control circuit 2203 described later, drive signals that make the switching elements in an on state and drive signals that make the switching elements in an off state are output to the control electrodes of respective switching elements.

[0244] When the switching element is maintained in an on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in an off state, the drive signal becomes a voltage signal (off signal) less than the threshold voltage of the switching element.

[0245] The control circuit 2203 controls the switching elements of the conversion circuit 2201 in such a manner as to supply desired power to the load 2300. Specifically, based on the power to be supplied to the load 2300, the time (on-time) during which each switching element of the conversion circuit 2201 should be in the on-state is calculated. For example, the conversion circuit 2201 can be controlled by pulse width modulation (PWM: Pulse Width Modulation) that modulates the on-time of the switching elements according to the voltage to be output.

[0246] Moreover, the control circuit 2203 outputs a control command (control signal) to the drive circuit 2202 in such a manner that an on-signal is output to the switching elements that should be in the on-state at each time point, and an off-signal is output to the switching elements that should be in the off-state. The drive circuit 2202 outputs an on-signal or an off-signal as a drive signal to the control electrodes of the respective switching elements according to this control signal.

[0247] In the power conversion device 2200 according to the present Embodiment 3, any of the semiconductor devices in the above-described Embodiments 1 and 2 is applied as the switching element of the conversion circuit 2201, so that the on-resistance after the conduction cycle can be stabilized.

[0248] In the case where the semiconductor devices according to Embodiments 1 and 2 are applied to the power conversion device 2200 in this way, the semiconductor devices are usually embedded in a gel, resin, or the like for use. However, since these materials cannot completely cut off moisture, the insulation protection of the semiconductor devices is maintained by the structures shown in Embodiments 1 and 2. That is, by applying the semiconductor devices having the structures shown in Embodiments 1 and 2, the reliability of the power conversion device 2200 can be improved.

[0249] In addition, in the present Embodiment 3, an example in which the semiconductor devices of Embodiments 1 and 2 are applied to a two-level three-phase inverter has been described. However, the application examples of the semiconductor devices of Embodiments 1 and 2 are not limited thereto, and the semiconductor devices of Embodiments 1 and 2 can be applied to various power conversion devices.

[0250] In addition, in the present Embodiment 3, a two-level power conversion device has been described. However, the semiconductor devices of Embodiments 1 and 2 can be applied to a three-level or multi-level power conversion device. In addition, in the case of supplying power to a single-phase load, the semiconductor devices of Embodiments 1 and 2 can be applied to a single-phase inverter.

[0251] In addition, in the case of supplying power to a DC load or the like, the semiconductor devices of Embodiments 1 and 2 can also be applied to a DC-DC converter or an AC-DC converter.

[0252] In addition, the power conversion device of the semiconductor device according to Application Embodiments 1 and 2 is not limited to the case where the load is a motor as described above. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system. In addition, the power conversion device of the semiconductor device according to Application Embodiments 1 and 2 can also be used as a power conditioner in a solar power generation system or a power storage system, etc.

[0253] <Method of manufacturing a power conversion device>

[0254] Next, a method of manufacturing the power conversion device according to Embodiment 3 will be described. First, a semiconductor device is manufactured by the manufacturing methods described in Embodiments 1 and 2. Then, the conversion circuit 2201 having the semiconductor device is incorporated into the power conversion device 2200. The conversion circuit 2201 is a circuit for converting the input power and outputting it.

[0255] Moreover, the drive circuit 2202 is incorporated into the power conversion device 2200. The drive circuit 2202 is a circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device. Moreover, the control circuit 2203 is incorporated into the power conversion device 2200. The control circuit 2203 is a circuit for outputting a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

[0256] Regarding the semiconductor device described in Embodiments 1 and 2, that is, the semiconductor switching element, an example of being composed of a SiC semiconductor is shown, but a switching element composed of a wide bandgap semiconductor other than the SiC semiconductor can be used.

[0257] As wide bandgap semiconductors other than Si semiconductors, there are also gallium nitride-based materials or diamond, etc. The switching element composed of a wide bandgap semiconductor can also be used in a high voltage region where unipolar operation is difficult in a Si semiconductor, and the switching loss generated during the switching operation can be greatly reduced. Therefore, the power loss can be greatly reduced.

[0258] In addition, the switching element composed of a wide bandgap semiconductor has small power loss and high heat resistance. Therefore, when forming a power module equipped with a cooling unit, the heat sink fins of the radiator can be miniaturized, so the semiconductor module can be further miniaturized.

[0259] In addition, the switching element composed of a wide bandgap semiconductor is suitable for high-frequency switching operation. Therefore, when applied to a converter circuit with a large requirement for high frequency, the reactor or capacitor connected to the converter circuit can also be miniaturized by increasing the switching frequency.

[0260] In the above-described embodiments, the physical properties, materials, dimensions, shapes, relative arrangement relationships, or implementation conditions of the respective constituent elements are sometimes also described, but they are illustrative in all respects, and the present disclosure is not limited to the described content. Therefore, countless variations not illustrated are envisioned within the scope of the present disclosure.

[0261] For example, it includes cases where any constituent element is deformed, added, or omitted, and cases where at least one constituent element in at least one embodiment is extracted and combined with the constituent elements of other embodiments.

[0262] In addition, as long as there is no contradiction, a constituent element described as having "one" in the above-described embodiments may also have "more than one". Furthermore, the constituent elements constituting the present disclosure are conceptual units, and one constituent element may include a plurality of structures, and one constituent element may also correspond to a part of a certain structure. In addition, among the respective constituent elements of the present disclosure, as long as they perform the same function, structures having other structures or shapes are included.

[0263] In addition, the present disclosure can freely combine the respective embodiments or appropriately deform and omit the respective embodiments within the scope of this disclosure.

[0264] Although the present disclosure has been described in detail, the above description is illustrative in all respects, and the present disclosure is not limited thereto. It should be understood that countless variations not illustrated are envisioned without departing from the scope of the present disclosure. In addition, the description in this specification is an example referred to for all purposes of the present disclosure, and should not be considered as the prior art unless otherwise specifically stated.

Claims

1. A semiconductor device having an active region through which a main current flows in the thickness direction of a semiconductor substrate, wherein, the semiconductor substrate is divided into an inner region provided with the active region and an outer region surrounding the inner region, the semiconductor device includes: a semiconductor layer of a first conductivity type; a terminal well region of a second conductivity type having a conductivity type different from that of the first conductivity type, selectively provided in an upper portion of the semiconductor layer so as to surround the inner region in a plan view; an impurity region of the first conductivity type or the second conductivity type, selectively provided in an upper portion of the terminal well region; a surface electrode provided on a second main surface side opposite to a first main surface of the semiconductor substrate; a back electrode provided on the first main surface; an insulating film provided so as to partially cover an upper portion of the terminal well region; an outer peripheral wiring layer, at least a part of which is provided on an upper portion of the insulating film and surrounds the inner region in a plan view; and an interlayer insulating film covering at least the insulating film and the outer peripheral wiring layer, the terminal well region extends from a boundary between the inner region and the outer region toward the outer region, the surface electrode is provided from the inner region to an upper portion of the interlayer insulating film and is connected to the impurity region through a first contact hole penetrating the interlayer insulating film and reaching the impurity region, the outer peripheral wiring layer is separated from a gate electrode provided in the inner region and led out to the outer region, the outer peripheral wiring layer is provided such that: in a plan view, an outer peripheral end portion on an outer peripheral side, which is a side opposite to the inner region, is located more inward than an outer peripheral end portion of the terminal well region on a side opposite to the inner region, and is located more outward than below an end portion of the surface electrode on an upper portion of the interlayer insulating film.

2. The semiconductor device according to claim 1, wherein, the outer peripheral wiring layer is provided such that: in an entire circumference surrounding the inner region, the outer peripheral end portion is located more outward than below the end portion of the surface electrode on an upper portion of the interlayer insulating film.

3. The semiconductor device according to claim 1, wherein, the outer peripheral wiring layer is provided such that: the outer peripheral end portion is located more outward than below the end portion of the surface electrode on an upper portion of the interlayer insulating film by at least 1 μm.

4. The semiconductor device according to claim 1, wherein, the surface electrode is connected to the outer peripheral wiring layer through a second contact hole penetrating the interlayer insulating film and reaching the outer peripheral wiring layer.

5. The semiconductor device according to claim 4, wherein, the surface electrode is connected to the outer peripheral wiring layer through the second contact hole at an end portion on an upper portion of the interlayer insulating film.

6. A semiconductor device having an active region through which a main current flows in the thickness direction of a semiconductor substrate, wherein, the semiconductor substrate is divided into an inner region provided with the active region and an outer region surrounding the inner region, the semiconductor device includes: a semiconductor layer of a first conductivity type; A terminal well region of a second conductivity type different from the first conductivity type is selectively provided in an upper portion of the semiconductor layer so as to surround the inner region in a plan view; An impurity region of the first conductivity type or the second conductivity type is selectively provided in an upper portion of the terminal well region; A surface electrode is provided on a second main surface side of the semiconductor substrate opposite to the first main surface; A back electrode is provided on the first main surface; An insulating film is provided so as to partially cover an upper portion of the terminal well region; An outer peripheral wiring layer is provided at least partially on an upper portion of the insulating film; And An interlayer insulating film covers at least the insulating film and the outer peripheral wiring layer, The terminal well region extends from a boundary between the inner region and the outer region toward the outer region, The inner region is configured with a minimum unit structure of a plurality of transistors to form the active region, The surface electrode has: A gate portion electrically connected to a gate electrode of the transistor; And A source electrode electrically connected to a source region electrode of the transistor, At least a part of the gate electrode is provided on an upper portion of the insulating film, The source electrode includes: A source pad provided on an upper portion from the inner region to the interlayer insulating film and connected to the impurity region through a first contact hole penetrating the interlayer insulating film; and a source wiring connected to the source pad, The gate portion includes: A gate wiring provided on an upper portion of the interlayer insulating film so as to surround the source pad in a plan view while leaving the source pad, and connected to the gate electrode through a second contact hole penetrating the interlayer insulating film and reaching the upper portion of the insulating film; and a gate pad connected to the gate wiring, The source wiring is provided on an upper portion of the interlayer insulating film so as to surround the gate wiring while leaving the gate wiring in a plan view, The outer peripheral wiring layer is provided on the insulating film so as to surround the gate electrode in a plan view, The outer peripheral wiring layer is provided such that an outer peripheral end portion on the outer peripheral side, which is opposite to the inner region, is located more inward than an outer peripheral end portion of the terminal well region on the side opposite to the inner region in a plan view, and is located more outward from below the outer peripheral end portion of the source wiring, and is located more inward from below the inner peripheral end portion of the source wiring.

7. The semiconductor device according to claim 6, wherein The outer peripheral wiring layer is provided such that, on the entire circumference surrounding the gate electrode, the outer peripheral end portion is located more outward from below the outer peripheral end portion of the source wiring, and is located more inward from below the inner peripheral end portion of the source wiring.

8. The semiconductor device according to claim 6, wherein The outer peripheral wiring layer is provided such that the outer peripheral end portion is located more outward from below the outer peripheral end portion of the source wiring by at least 1 μm, and is located more inward from below the inner peripheral end portion of the source wiring by at least 1 μm.

9. The semiconductor device according to claim 6, wherein The source wiring is connected to the outer peripheral wiring layer through a third contact hole that penetrates the interlayer insulating film and reaches the outer peripheral wiring layer.

10. The semiconductor device according to claim 9, wherein the source wiring is connected to the outer peripheral wiring layer through the third contact hole at the outer peripheral end of the source wiring.

11. The semiconductor device according to claim 9, wherein the source wiring is connected to the outer peripheral wiring layer through the third contact hole at the inner peripheral end of the source wiring.

12. The semiconductor device according to claim 1 or 6, wherein the semiconductor layer is a silicon carbide semiconductor layer.

13. The semiconductor device according to claim 1 or 6, wherein the interlayer insulating film has an elemental composition of boron or phosphorus.

14. The semiconductor device according to claim 1 or 6, wherein The impurity concentration per unit area of the terminal well region is 2×10 13 cm -2 or more.

15. The semiconductor device according to claim 1 or 6, wherein the semiconductor substrate has: a well region of a second conductivity type selectively provided in an upper portion of the semiconductor layer, and the well region has an impurity concentration lower than the impurity concentration of the terminal well region.

16. A power conversion device, comprising: a conversion circuit having the semiconductor device according to any one of claims 1 to 15, the conversion circuit converting input power and outputting it; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

Images