Display panel, display device, display motherboard and manufacturing method thereof

Abstract

The present application provides a display panel, the display panel includes a display area and a binding area, the display panel includes an array substrate, and the array substrate includes a first substrate. The display panel also includes a test trace and a first resistor element, the test trace is arranged on one side of the first substrate and is located in the binding area, the first resistor element partially covers the test trace on the first substrate, the first resistor element, the test trace and the first substrate are surrounded to form a first groove, and the opening of the first groove faces the side of the binding area facing away from the display area. The first groove is used to fill a conductive solution, and after the display panel is formed, the conductive solution in the first groove flows out. Therefore, due to the presence of the first groove, the conductive tape will not contact the surface of the test trace exposed from the first groove, and then the test trace will not be short-circuited, thereby avoiding poor display of the display panel and improving the reliability of the display panel. The present application also provides a display device, a display motherboard and a method for manufacturing a display motherboard.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a display device having the display panel, a display motherboard having the display panel, and a method for manufacturing the display motherboard. Background Art

[0002] Liquid crystal display devices have been widely used in people's lives and work due to their advantages of thin body, low power consumption, low price, etc. Liquid crystal display devices usually include a display panel and a backlight module, and the display panel is formed by cutting a display motherboard.

[0003] In the design of display panels, the non-display area of ​​the display panel is usually provided with multiple test traces for testing the circuit conductivity of each display panel on the display motherboard. When the display motherboard is cut to form multiple display panels, the test traces will be exposed from the sides of the display panels. In subsequent processes, conductive tape will be attached to the sides of the display panels. The conductive tape is easily electrically connected to the exposed test traces, causing the test traces to short-circuit, which in turn causes poor display of the display panel.

[0004] Therefore, how to solve the problem of display defects caused by short circuits of exposed test traces on the display panel in the prior art is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a display panel, a display device having the display panel, a display motherboard having the display panel and a method for manufacturing the display motherboard, aiming to solve the problem of short circuit of the exposed test lines of the display panel causing poor display in the prior art.

[0006] In order to solve the above technical problems, an embodiment of the present application provides a display panel, the display panel includes a display area and a binding area arranged on one side of the display area, the display panel includes an array substrate, the array substrate includes a first substrate, and a portion of the first substrate is located in the binding area. The display panel also includes a plurality of test traces and a plurality of first resistor elements, the test traces are arranged on one side of the first substrate and located in the binding area, and are electrically connected to the array substrate, the first resistor element partially covers the test traces on the first substrate, the first resistor element, the test traces and the first substrate are surrounded to form a first groove, the opening of the first groove faces the side of the binding area facing away from the display area. Wherein, the first groove is used to fill a conductive solution, and after the display panel is formed, the conductive solution in the first groove flows out.

[0007] In summary, the display panel provided by the embodiment of the present application is retracted in the side of the binding area facing away from the display area through the test trace, and the conductive tape will not contact the surface of the plurality of test traces exposed in the first groove, and thus the test trace will not be short-circuited, thereby avoiding poor display of the display panel and improving the reliability of the display panel. Moreover, the display panel is not cut, and the test trace is electrically connected to the test component through the conductive solution, and thus the test component can provide the test electrical signal to the display panel to test the display panel.

[0008] In an exemplary embodiment, the display panel further includes a plurality of insulating elements, wherein the insulating elements are filled in the first groove to insulate a surface of the test trace facing away from the display area and to support the first resistance element.

[0009] In an exemplary embodiment, the first resistor element further includes a chamfered end, which is an end of the first resistor element facing away from the display area. In the direction in which the test line points to the first resistor element, the chamfered end is inclined toward the direction in which the display area is located; or in the direction in which the first resistor element points to the test line, the chamfered end is inclined toward the direction in which the display area is located.

[0010] In an exemplary embodiment, the binding area further includes a first flat area and a plurality of first recessed areas, wherein the plurality of first recessed areas are arranged at intervals, a portion of the circumference of each first recessed area is wrapped by the first flat area, and a side of the first recessed area facing away from the display area exposes the first flat area. The first groove is located in the first recessed area, and the highest point of the sidewall of the first groove is less than or equal to the height of the surface of the first substrate facing the test trace located in the first flat area.

[0011] Based on the same inventive concept, an embodiment of the present application further provides a display device, which includes a backlight module and the above-mentioned display panel, and the display panel is arranged on the light-emitting side of the backlight module.

[0012] In summary, the display device provided in the embodiment of the present application includes a backlight module and a display panel, the display panel is retracted inwardly on the side of the binding area facing away from the display area through the test trace, the conductive tape will not contact the surface of the plurality of test traces exposed in the first groove, and thus the test traces will not be short-circuited, thereby avoiding poor display of the display panel and improving the reliability of the display panel. Moreover, the display panel is not cut, the test traces are electrically connected to the test component through the conductive solution, and thus the test component can provide the test electrical signal to the display panel to test the display panel.

[0013] Based on the same inventive concept, the embodiment of the present application also provides a display motherboard, the display motherboard includes a test component and the above-mentioned display panel, the test component includes a second substrate, a plurality of conductive traces and a plurality of second resistor elements, wherein the second substrate is connected to the first substrate and arranged in the same layer, the conductive traces are in the same layer as the test traces and are arranged at intervals, the second resistor element partially covers the conductive traces on the second substrate, and is connected to the first resistor element and arranged in the same layer; the second substrate, the conductive traces and the second resistor element surround each other to form a second groove, the opening of the second groove faces the opening of the first groove, and is connected to the first groove. The first groove and the second groove are filled with a conductive solution, and the conductive solution contacts the test traces and the conductive traces respectively to electrically connect the test traces with the conductive traces.

[0014] In summary, the display motherboard provided in the embodiment of the present application includes a test module and a display panel, the display panel is retracted inwardly on the side of the binding area facing away from the display area through the test trace, the conductive tape will not contact the surface of the plurality of test traces exposed in the first groove, and thus the test traces will not be short-circuited, thereby avoiding poor display of the display panel and improving the reliability of the display panel. Moreover, the display panel is not cut, the test traces are electrically connected to the test component through the conductive solution, and thus the test component can provide the test electrical signal to the display panel to test the display panel.

[0015] In an exemplary embodiment, the binding area further includes a first flat area and a plurality of first recessed areas, wherein the plurality of first recessed areas are arranged at intervals, a portion of the circumference of each first recessed area is wrapped by the first flat area, and a side of the first recessed area facing away from the display area exposes the first flat area. The first groove is located in the first recessed area, and the highest point of the sidewall of the first groove is less than or equal to the height of the surface of the first substrate facing the test trace located in the first flat area.

[0016] In an exemplary embodiment, the test assembly further includes a second flat area and a plurality of second recessed areas, the plurality of second recessed areas are arranged at intervals, a portion of the circumference of each second recessed area is wrapped by the second flat area, and one side of the second recessed area is connected to the exposed side of the first recessed area. The second groove is located in the second recessed area, and the highest point of the sidewall of the second groove is less than or equal to the height of the surface of the second substrate facing the conductive trace located in the second flat area.

[0017] In an exemplary embodiment, the conductive solution includes 90% to 98% by mass of a conductive material and 2% to 10% by mass of an auxiliary material, wherein the conductive material is used for conducting electricity and the auxiliary material is used for increasing fluidity of the conductive solution.

[0018] Based on the same inventive concept, an embodiment of the present application further provides a method for manufacturing a display motherboard, wherein the method for manufacturing a display motherboard is used to manufacture the above-mentioned display motherboard, and the method for manufacturing a display motherboard comprises:

[0019] An array substrate assembly is provided, wherein the array substrate assembly comprises a first substrate and a second substrate;

[0020] forming a conductive layer on the first substrate and the second substrate;

[0021] The conductive layer is formed into a plurality of test traces and a plurality of conductive traces, and a containing space is formed between the test traces and the conductive traces, wherein the containing space comprises a first groove and a second groove, the test traces and the first groove are located on the first substrate, and the conductive traces and the second groove are located on the second substrate;

[0022] Filling the containing space with a conductive solution;

[0023] At least a partial resistance component is formed on the side of the test trace facing away from the first substrate and on the side of the conductive trace facing away from the second substrate, so that the resistance component covers the conductive solution, wherein the resistance component includes a first resistance element and a second resistance element, the first resistance element is located on the test trace, and the second resistance element is located on the conductive trace.

[0024] In summary, the display motherboard formed by the manufacturing method of the display motherboard provided in the embodiment of the present application includes a test module and a display panel, the display panel is retracted inwardly at the side of the binding area facing away from the display area through the test trace, the conductive tape will not contact the surface of the plurality of test traces exposed in the first groove, and thus the test traces will not be short-circuited, thereby avoiding poor display of the display panel and improving the reliability of the display panel. Moreover, the display panel is not cut, the test traces are electrically connected to the test component through the conductive solution, and thus the test component can provide the test electrical signal to the display panel to test the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of the structure of a display motherboard disclosed in the first embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a display panel disclosed in the second embodiment of the present application;

[0028] Figure 3 This is a schematic diagram of a first layer structure of a display panel disclosed in the second embodiment of the present application;

[0029] Figure 4 for Figure 1 A schematic diagram of a first partial layer structure of a display motherboard is shown;

[0030] Figure 5 This is a schematic diagram of a second layer structure of a display panel disclosed in the second embodiment of the present application;

[0031] Figure 6 This is a schematic diagram of a third layer structure of a display panel disclosed in the second embodiment of the present application;

[0032] Figure 7 for Figure 6 The enlarged schematic diagram of structure VII in the display panel shown;

[0033] Figure 8 This is a schematic diagram of a fourth layer structure of a display panel disclosed in the third embodiment of the present application;

[0034] Fig. 9 for Figure 8 A schematic diagram of the planar structure corresponding to the display panel shown;

[0035] Fig.10 for Figure 8 An enlarged schematic diagram of structure X in the display panel is shown;

[0036] Fig.11 for Figure 8 A schematic diagram of a three-dimensional structure corresponding to a binding area of ​​a display panel shown;

[0037] Fig.12 for Figure 1 A schematic diagram of a second partial layer structure of a display motherboard is shown;

[0038] Fig.13 for Fig.12The schematic diagram of the planar structure of the display motherboard shown;

[0039] Fig.14 for Fig.12 An enlarged schematic diagram of structure XIIII in the display motherboard described in;

[0040] Fig.15 A schematic diagram of the layer structure of a display device disclosed in the third embodiment of the present application;

[0041] Fig.16 A schematic flow chart of a method for manufacturing a display motherboard disclosed in a third embodiment of the present application;

[0042] Fig.17 It is a structural schematic diagram corresponding to step S20a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0043] Fig.18 It is a flowchart of step S30a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0044] Fig.19 It is a structural schematic diagram corresponding to step S31a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0045] Fig. 20 It is a structural schematic diagram corresponding to step S32a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0046] Fig.21 It is a structural schematic diagram corresponding to step S40a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0047] Fig. 22 It is a structural schematic diagram corresponding to step S20b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0048] Fig.23 It is a structural schematic diagram corresponding to step S30b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0049] Fig.24 It is a structural schematic diagram corresponding to step S40b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application;

[0050] Fig.25 It is a structural schematic diagram corresponding to step S50b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application.

[0051] Description of reference numerals:

[0052] 1-display area; 2-non-display area; 4-test wiring; 6-insulating element; 10-display panel; 10a-display panel; 10b-display panel; 10c-display panel; 11-array substrate; 13-liquid crystal layer; 15-color film substrate; 16-sealing glue; 17-shielding layer; 18-first resistor element; 18a-chamfered end; 19-conductive gel; 20-test component; 20a-second flat area; 20b-second recessed area; 21-test element; 23-second substrate; 24-conductive Electrical trace; 26-second resistor element; 40-test trace assembly; 41-conductive solution; 60-conductive layer; 70-resistance assembly; 80-accommodation space; 100-display motherboard; 100a-display motherboard; 100b-display motherboard; 111-first substrate; 113-driving circuit layer; 115-insulating layer; 131-liquid crystal molecules; 200-display device; 201-binding area; 201a-first flat area; 201b-first recessed area; a-first groove; b-second groove. S10-S50-steps of the method for manufacturing the display motherboard; S10a-S50a-steps of the method for manufacturing the display motherboard; S31a-S32a-steps of step S30a; S10b-S50b-steps of the method for manufacturing the display motherboard. DETAILED DESCRIPTION

[0053] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0054] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0055] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including", "may include", "include", or "may include" used in this application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "including" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. It should also be understood that "at least one" described herein means one or more, such as one, two or three, etc., and "plurality" means at least two, such as two or three, etc., unless otherwise clearly defined.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0057] See also Figure 1 , Figure 1 The structure diagram of the display motherboard disclosed in the first embodiment of the present application. In the embodiment of the present application, the display motherboard 100 includes a plurality of display panels 10 and at least one test component 20, wherein the test component 20 is connected between two adjacent display panels 10, and the test component 20 is electrically connected to the two adjacent display panels 10, and the test component 20 is used to provide a test electrical signal to the display panel 10 to test the display panel 10. Among them, testing the display panel 10 refers to: testing the circuit conduction condition of the display panel 10 and testing the luminescence condition of the display panel 10.

[0058] In the implementation mode of this application, please refer to Figure 1 and Figure 2 , Figure 2The structure diagram of the display panel disclosed in the second embodiment of the present application is shown in FIG. The display panel 10 includes a display area 1 and a non-display area 2 surrounding the display area 1. The display area 1 is used to perform image display, and the non-display area 2 is used to set other auxiliary display components or modules and signal lines.

[0059] In an exemplary embodiment, the display area 1 of the display panel 10 includes a plurality of pixel units (not shown) distributed in an array, and the plurality of pixel units are used to perform image display.

[0060] In the implementation mode of this application, please refer to Figure 1 The display motherboard 100 further includes a plurality of test wiring assemblies 40, and the plurality of test wiring assemblies 40 are located in the non-display area 2 of the display panel 10 and in the area where the test assembly 20 is located. The test assembly 20 includes a test element 21, and the test element 21 is electrically connected to the plurality of test wiring assemblies 40, and the test element 21 is used to provide the test electrical signal to the display panel 10 through the test wiring assembly 40.

[0061] In an exemplary embodiment, the plurality of test wiring assemblies 40 located on one display panel 10 are arranged at intervals and parallel to each other, and the plurality of test wiring assemblies 40 are insulated from each other.

[0062] In an exemplary embodiment, the test element 21 may be a plurality of traces. The test assembly 20 further includes a connection line, which is electrically connected to the test element 21 to electrically connect the test element 21 to an external electronic element or component.

[0063] In an exemplary embodiment, along Figure 1 The display mother panel 100 is cut along the cutting line Q shown in FIG. Figure 2 The multiple display panels 10 shown in the figure further include multiple test traces 4, which are parts of the test trace assembly 40 and are located in the non-display area 2. The multiple test traces 4 can be arranged in parallel and spaced apart from each other, and the multiple test traces 4 are insulated from each other. The non-display area 2 further includes a binding area 201, which is arranged on one side of the display area 1. When the display panel 10 is not cut, the binding area 201 is connected to the area where the test assembly 20 is located. The cutting direction of the cutting line Q is perpendicular to the extension direction of the test trace 4.

[0064] In the related art, a display panel formed by cutting has a side surface of a test line exposed on a side of the binding area facing away from the display area, and the exposed side surface of the test line is aligned with a surface of the binding area facing away from the display area.

[0065] In the implementation mode of this application, please refer to Figure 3 , Figure 3 The first layer structure schematic diagram of the display panel disclosed in the second embodiment of the present application. The display panel 10 includes an array substrate 11, a liquid crystal layer 13, a color filter substrate 15 and a sealant 16. The array substrate 11 and the color filter substrate 15 are arranged opposite to each other and spaced apart, and the liquid crystal layer 13 is arranged between the array substrate 11 and the color filter substrate 15. The liquid crystal layer 13 is located in the display area 1, and the sealant 16 is arranged in the non-display area 2, and is located between the array substrate 11 and the color filter substrate 15 and on the periphery of the liquid crystal layer 13. The liquid crystal layer 13 includes a plurality of liquid crystal molecules 131, and the array substrate 11 and the color filter substrate 15 are used to form a preset electric field, and the preset electric field is used to drive the plurality of liquid crystal molecules 131 to deflect, so that the display panel 10 displays different grayscales. The sealant 16 is used to seal the liquid crystal layer 13 between the array substrate 11 and the color filter substrate 15 and to bond the array substrate 11 and the color filter substrate 15.

[0066] In the implementation mode of this application, please refer to Figure 3 , the array substrate 11 includes a first substrate 111, a driving circuit layer 113 and an insulating layer 115. The first substrate 111 is arranged on the side of the liquid crystal layer 13 facing away from the color filter substrate 15, and is spaced from the liquid crystal layer 13. The first substrate 111 is located in the display area 1 and the non-display area 2. The driving circuit layer 113 is arranged on the side of the first substrate 111 facing the liquid crystal layer 13, and is located in the display area 1 and the non-display area 2. The insulating layer 115 is arranged on the side of the driving circuit layer 113 facing away from the first substrate 111, and is connected to the frame sealant 16. The insulating layer 115 is used to insulate the liquid crystal layer 13 and the driving circuit layer 113.

[0067] In an exemplary embodiment, the driving circuit layer 113 includes at least a plurality of scan lines and a plurality of data lines, wherein the data lines transmit data signals for display to the plurality of pixel units located in the display area 1, and the scan lines transmit scan signals for controlling when the pixel units receive the data signals.

[0068] In an exemplary embodiment, see Figure 3, part of the first substrate 111 is located in the binding area 201, and the test trace 4 is located on the side of the first substrate 111 where the drive circuit layer 113 is disposed, and is located in the binding area 201. That is, the test trace 4 and the drive circuit layer 113 are disposed on the same side of the first substrate 111, and the drive circuit layer 113 is not located in the binding area 201, and the test trace 4 is located in the binding area 201. The test trace 4 is electrically connected to the drive circuit layer 113, and the test trace 4 can be electrically connected to the scan line of the drive circuit layer 113 to transmit a test electrical signal to the scan line.

[0069] In the implementation mode of this application, please refer to Figure 3 The display panel 10 further includes a shielding layer 17, which is disposed on the side of the color filter substrate 15 facing away from the liquid crystal layer 13, and is used to shield the external electric field and release static electricity. It is understandable that the external electric field will affect the preset electric field, thereby affecting the deflection of the liquid crystal molecules 131, resulting in poor display of the display panel 10. Moreover, if the shielding layer 17 carries static electricity, the shielding layer 17 will form an interference electric field with the array substrate 11, and the interference electric field will affect the deflection of the liquid crystal molecules 131, resulting in poor display of the display panel 10.

[0070] In the implementation mode of this application, please refer to Figure 3 The display panel 10 further includes a plurality of first resistor elements 18 and a plurality of conductive gels 19. The first resistor element 18 partially covers the test trace 4 on the first substrate 111 and is located in the binding area 201. The conductive gel 19 is disposed on a side of the first resistor element 18 that is away from the test trace 4 and is located in the binding area 201. The conductive gel 19 is respectively connected to the shielding layer 17 and the first resistor element 18 to electrically connect the shielding layer 17 to the first resistor element 18.

[0071] In an exemplary embodiment, the first resistor element 18 may be connected to the insulating layer 115 or may be separated from the insulating layer 115, and this application does not impose any specific restrictions on this. The conductive gel 19 may be connected to the color filter substrate 15 and to the frame sealant 16, or may be separated from the color filter substrate 15 and to the frame sealant 16, and this application does not impose any specific restrictions on this.

[0072] In an exemplary embodiment, the material of the first resistor element 18 may be indium tin oxide (ITO), which has a relatively weak conductivity. Compared with the test trace 4, the conductivity of the first resistor element 18 is relatively weak, that is, the first resistor element 18 is an insulator compared with the test trace 4. Therefore, when the display panel 10 is tested, the test trace 4 is not electrically connected to the first resistor element 18 to prevent the test electrical signal from being transmitted to the first resistor element 18. Moreover, the first resistor element 18 has a relatively weak conductivity, which can conduct away the static electricity on the shielding layer 17. Among them, the material of the test trace 4 may include any one or more of metal materials such as platinum, gold, aluminum, copper, titanium, silver, chromium, nickel, etc., and the present application does not impose specific restrictions on this.

[0073] In an exemplary embodiment, the display panel 10 further includes a conductive tape (not shown), which is attached to the first resistor element 18 and the circuit board to electrically connect the first resistor element 18 to the circuit board, and further the shielding layer 17 to the circuit board to conduct away static electricity on the shielding layer 17. However, in the related art, the conductive tape is easily in contact with the exposed surfaces of the plurality of test traces 4, causing the test traces 4 to short-circuit, thereby causing the display panel 10 to display poorly.

[0074] In the embodiment of the present application, the first resistor element 18 partially covers the test trace 4 on the first substrate 111, and the first resistor element 18 and the first substrate 111 extend out of the side of the test trace 4 facing away from the drive circuit layer 113, then the first resistor element 18, the test trace 4 and the first substrate 111 surround each other to form a first groove a, wherein the first resistor element 18 and the first substrate 111 form the sidewalls of the first groove a, the side of the test trace 4 facing away from the drive circuit layer 113 forms the bottom surface of the first groove a, and the opening of the first groove a faces the side of the binding area 201 facing away from the display area 1. That is, in the direction from the display area 1 to the binding area 201, the portion of the first substrate 111 located in the binding area 201 is longer than the test trace 4, and the portion of the first resistor element 18 located in the binding area 201 is also longer than the test trace 4, thereby forming the first groove a, and the side of the test trace 4 facing away from the drive circuit layer 113 is the bottom surface of the first groove a. The display panel 10 is not cut, and the first groove a is filled with a conductive solution; after the display panel 10 is cut, the conductive solution in the first groove a flows out. In other words, the first groove a is used to fill the conductive solution, and after the display panel 10 is formed, the conductive solution in the first groove a flows out.

[0075] It can be understood that the test trace 4 is arranged between the first substrate 111 and the first resistor element 18, and forms the bottom wall of the first groove a, that is, the test trace 4 is spaced apart from the side of the binding area 201 facing away from the display area 1 by a spacing of the first groove a, and the conductive tape will not contact the surfaces of the plurality of test traces 4 exposed from the first groove a, that is, the conductive tape will not extend into the bottom surface of the first groove a to contact the test trace 4, and thus the test trace 4 will not be short-circuited, thus avoiding poor display of the display panel 10 and improving the reliability of the display panel 10. Moreover, when the display panel 10 is not cut, the test trace 4 is electrically connected to the test component 20 through the conductive solution, and thus the test component 20 can provide the test electrical signal to the display panel 10 to test the display panel 10.

[0076] In an exemplary embodiment, the display panel 10 may be a twisted nematic (TN) display panel, a vertical alignment (VA) display panel, an in-plane switching (IPS) display panel, or a fringe field switching (FFS) display panel, and the present application does not impose any specific restrictions on this.

[0077] In summary, the display panel 10 provided in the embodiment of the present application includes a display area 1 and a binding area 201 arranged on one side of the display area 1. The display panel 10 includes an array substrate 11, and the array substrate 11 includes a first substrate 111, and a portion of the first substrate 111 is located in the binding area 201. The display panel 10 also includes a test trace 4 and a first resistor element 18, the test trace 4 is arranged on one side of the first substrate 111 and is located in the binding area 201, and the first resistor element 18 partially covers the test trace 4 on the first substrate 111 and is located in the binding area 201. The test trace 4 is used to be electrically connected to the array substrate 11 to transmit a test electrical signal to the array substrate 11. The first resistor element 18, the test trace 4, and the first substrate 111 surround each other to form a first groove a, and the opening of the first groove a faces the side of the binding area 201 facing away from the display area 1. When the display panel 10 is not cut, the first groove a is filled with a conductive solution; after the display panel 10 is cut, the conductive solution in the first groove a flows out. Therefore, the test trace 4 is retracted to the side of the binding area 201 facing away from the display area 1, and the conductive tape will not contact the surface of the plurality of test traces 4 exposed in the first groove a, and thus the test trace 4 will not be short-circuited, thereby avoiding poor display of the display panel 10 and improving the reliability of the display panel 10. Moreover, when the display panel 10 is not cut, the test trace 4 is electrically connected to the test component 20 through the conductive solution, and thus the test component 20 can provide the test electrical signal to the display panel 10 to test the display panel 10.

[0078] In the embodiments of this application, please refer to Figure 1 and Figure 4 , Figure 4 for Figure 1 The first partial layer structure schematic diagram of the display motherboard shown. The test component 20 is arranged on the side of the binding area 201 facing away from the display area 1. The test component 20 also includes a second substrate 23, a plurality of conductive traces 24 and a plurality of second resistance elements 26. Among them, the second substrate 23 is arranged in the same layer and connected with the first substrate 111. The conductive trace 24 is arranged on the side of the test trace 4 facing away from the driving circuit layer 113, and is spaced from the test trace 4, and is connected to the second substrate 23, that is, the conductive trace 24 is arranged in the same layer and spaced from the test trace 4. The second resistance element 26 partially covers the conductive trace 24 on the second substrate 23, and is connected to the first resistance element 18 and arranged in the same layer. The conductive trace 24 is used to be electrically connected to the test element 21.

[0079] In an exemplary embodiment, the material of the second resistor element 26 may be indium tin oxide (ITO), which has weaker conductivity. Compared with the conductive trace 24, the conductivity of the second resistor element 26 is weaker, that is, the second resistor element 26 is an insulator compared to the conductive trace 24. Therefore, when the display panel 10 is tested, the conductive trace 24 is not electrically connected to the second resistor element 26 to prevent the test electrical signal from being transmitted to the second resistor element 26. The material of the conductive trace 24 may include, but is not limited to, any one or more of metal materials such as platinum, gold, aluminum, copper, titanium, silver, chromium, and nickel, and the present application does not impose specific restrictions on this.

[0080] In the implementation mode of this application, please refer to Figure 4 , the second substrate 23, the conductive trace 24 and the second resistor element 26 are surrounded to form a second groove b, the opening of the second groove b faces the opening of the first groove a and is connected to the first groove a. The display panel 10 is not cut, and the second groove b is filled with a conductive solution 41; after the display panel 10 is cut, the conductive solution 41 in the second groove b flows out. That is, the first groove a and the second groove b of the display motherboard 100 are filled with the conductive solution 41. The conductive solution 41 contacts the test trace 4 and the conductive trace 24 respectively to electrically connect the test trace 4 with the conductive trace 24.

[0081] In an embodiment of the present application, the conductive solution 41 includes a conductive material with a mass percentage of 90% to 98%, for example, 90%, 92%, 95%, 97%, 98%, or other values, and the present application does not impose specific restrictions on this. Among them, the conductive solution 41 can be one or more materials such as aluminum silver plating, copper silver plating, glass silver plating, and graphite nickel plating. The conductive solution 41 also includes auxiliary materials with a mass percentage of 2% to 10%, for example, 2%, 3%, 5%, 8%, 10%, or other values, and the present application does not impose specific restrictions on this. Among them, the auxiliary material can be rubber silicon.

[0082] It can be understood that the conductive material is used for conducting electricity, and the auxiliary material is used for increasing the fluidity of the conductive solution 41 to facilitate the conductive solution 41 to flow out of the first groove a and the second groove b.

[0083] In an exemplary embodiment, in the direction where the test component 20 points to the binding area 201, the second substrate 23 is longer than the conductive trace 24, and the second resistor element 26 is longer than the test trace 4, thereby forming the second groove b, and the side of the conductive trace 24 facing the test trace 4 is the bottom surface of the second groove b.

[0084] In an exemplary embodiment, the test trace 4 , the conductive solution 41 , and the conductive trace 24 constitute the test trace assembly 40 .

[0085] In an exemplary embodiment, the distance between the bottom surface of the first groove a and the bottom surface of the second groove b is 50um to 1000um, that is, the distance between the surfaces of the test trace 4 and the conductive trace 24 facing each other is 50um to 1000um, for example, 50um, 200um, 410um, 500um, 700um, 730um, 870um, 1000um, or other values, and the present application does not impose any specific limitation on this.

[0086] In an exemplary embodiment, the depth of the first groove a is 15um to 350um, for example, 15um, 50um, 150um, 230um, 300um, 320um, 350um, or other values, which are not specifically limited in the present application. The depth of the first groove a refers to the distance between the bottom surface of the first groove a and the opening of the first groove a.

[0087] It is understandable that in order to avoid the first groove a being too large, causing the first resistor element 18 to be unable to support its own weight and break, the size of the first groove a should be as small as possible, so the depth of the first groove a is set to 15um to 350um.

[0088] Based on the same inventive concept, please refer to Figure 5 , Figure 5 Schematic diagram of the second layer structure of the display panel disclosed in the second embodiment of the present application. The difference between the display panel 10a of the second layer structure and the display panel 10 of the first layer structure is that the display panel 10a of the second layer structure also includes a plurality of insulating elements. For the description of the similarities between the display panel 10a of the second layer structure and the display panel 10 of the first layer structure, please refer to the relevant description of the display panel 10 of the first layer structure, which will not be repeated here.

[0089] Specifically, in the embodiment of the present application, the display panel 10a includes a plurality of insulating elements 6, and the insulating elements 6 are filled in the first groove a to insulate the surface of the test trace 4 facing away from the display area 1, and the insulating elements 6 are also used to support the first resistor element 18 to prevent the resistor element 18 from breaking due to lack of support. The surface of the test trace 4 facing away from the display area 1 is also the surface of the test trace 4 facing away from the drive circuit layer 113.

[0090] In an exemplary embodiment, the material of the insulating element 6 may be ultraviolet (UV) glue or other insulating materials, and the present application does not impose any specific limitation on this.

[0091] Based on the same inventive concept, please refer to Figure 6 , Figure 6 This is a schematic diagram of the third layer structure of the display panel disclosed in the second embodiment of the present application. The difference between the display panel 10b with the third layer structure and the display panel 10a with the second layer structure is that the first resistor element 18 of the display panel 10b with the third layer structure also includes a chamfered end. For the description of the similarities between the display panel 10b with the third layer structure and the display panel 10a with the second layer structure, please refer to the relevant description of the display panel 10a with the second layer structure, which will not be repeated here.

[0092] Specifically, in the implementation mode of this application, please refer to Figure 6 and Figure 7 , Figure 7 for Figure 6 The enlarged schematic diagram of structure VII in the display panel shown. The first resistor element 18 also includes a chamfered end 18a, which is the end of the first resistor element 18 facing away from the driving circuit layer 113, that is, the chamfered end 18a is the end of the first resistor element 18 facing away from the display area 1. In the direction from the display area 1 to the binding area 201, the length of the first substrate 111 located in the binding area 201 is longer than the length of the first resistor element 18, and the length of the first resistor element 18 is longer than the length of the test trace 4.

[0093] In one embodiment of the present application, in the direction in which the test line 4 points to the first resistor element 18, the inclined surface of the chamfered end 18a is inclined toward the direction in which the display area 1 is located. In other embodiments of the present application, in the direction in which the first resistor element 18 points to the test line 4, the inclined surface of the chamfered end 18a is inclined toward the direction in which the display area 1 is located. The present application does not specifically limit the inclined direction of the inclined surface of the chamfered end 18a.

[0094] In an exemplary embodiment, the insulating element 6 is also filled onto the inclined surface of the chamfered end 18a, that is, the insulating element 6 is also disposed on the inclined surface of the chamfered end 18a. Further, the surface of the insulating element 6 facing away from the test trace 4 is flush with the surface of the insulating element 6 facing away from the chamfered end 18a.

[0095] In an exemplary embodiment, the chamfered end 18a may also be formed by cutting.

[0096] It can be understood that by forming the chamfered end 18a at the end of the first resistor element 18 facing away from the display area 1, the mass of the first resistor element 18 is reduced, which can further prevent the first resistor element 18 from being unable to support its own mass and breaking. At the same time, the chamfered end 18a can prevent the first resistor element 18 from contacting the conductive tape. Moreover, under the action of the inclined surface of the chamfered end 18a, the insulating material is more likely to flow into the first groove a, so that the insulating element 6 formed by the insulating material can fill the entire first groove a, which is conducive to improving the insulating function and supporting function of the insulating element 6.

[0097] Based on the same inventive concept, please refer to Figure 8 , Figure 8 This is a schematic diagram of the fourth layer structure of the display panel disclosed in the third embodiment of the present application. The difference between the display panel 10c of the fourth layer structure and the display panel 10a of the second layer structure is that the binding area 201 of the display panel 10c of the fourth layer structure also includes a first flat area and a first recessed area. For the description of the similarities between the display panel 10c of the fourth layer structure and the display panel 10a of the second layer structure, please refer to the relevant description of the display panel 10a of the second layer structure, which will not be repeated here.

[0098] For details, please refer to Fig. 9 , Fig. 9 for Figure 8 The schematic diagram of the planar structure corresponding to the display panel shown. In the embodiment of the present application, the binding area 201 of the display panel 10c of the fourth layer structure further includes a first flat area 201a and a plurality of first recessed areas 201b, wherein the plurality of first recessed areas 201b are arranged at intervals, a portion of the circumference of each first recessed area 201b is wrapped by the first flat area 201a, and the first flat area 201a is exposed on the side of the first recessed area 201b facing away from the display area 1.

[0099] In an exemplary embodiment, the plane shape of the first recessed area 201b may be a rectangle, three sides of the first recessed area 201b are wrapped by the first flat area 201a, and one side of the first recessed area 201b exposes the first flat area 201a. The number of the first recessed areas 201b is determined by the number of the test traces 4, and the present application does not impose any specific restrictions on this.

[0100] In the implementation mode of this application, please refer to Fig.10 , Fig.10 for Figure 8An enlarged schematic diagram of the structure X in the display panel is shown. A portion of the first substrate 111 located in the binding area 201 is located in the first flat area 201a, and another portion is located in the first recessed area 201b. A portion of the test trace 4 is located in the first flat area 201a, and another portion is located in the first recessed area 201b. A portion of the first resistor element 18 is located in the first flat area 201a, and another portion is located in the first recessed area 201b.

[0101] In the implementation mode of this application, please refer to Fig.10 , the first groove a is located in the first concave area 201b, and the highest point of the side wall of the first groove a is less than or equal to the height of the surface of the first substrate 111 located in the first flat area 201a facing the test line 4. That is, the entire first groove a is below the surface of the first substrate 111 located in the first flat area 201a facing the test line 4, that is, the first groove a is formed in the first substrate 111. The height refers to: the distance from the reference plane (the surface of the first substrate 111 facing away from the test line 4 is the reference plane) to the first substrate 111 facing the first resistor 18.

[0102] Understandably, see Fig.11 , Fig.11 for Figure 8 The schematic diagram of the three-dimensional structure corresponding to the binding area of ​​the display panel shown. By forming the first groove a in the first substrate 111, when an external force acts near the first groove a, the surface of the first substrate 111 located in the first flat area 201a facing the test trace 4 can also play a supporting role, further avoiding the risk of the first resistor element 18 located in the first recessed area 201b being broken due to lack of support. Moreover, by forming the first groove a in the first substrate 111, there is no need to form the first resistor element 18 on the side of the first groove a, and the conductive solution 41 can be directly injected into the first groove a, which simplifies the manufacturing process of the display motherboard.

[0103] In an exemplary embodiment, a surface of the first resistor element 18 located in the first recessed area 201 b facing away from the first groove a is aligned with a surface of the first substrate 111 located in the first flat area 201 a facing the test trace 4 .

[0104] In an exemplary embodiment, the height of the surface of the first substrate 111 located in the first flat area 201a facing the test trace 4 is higher than the height of the surface of the first substrate 111 located in the first recessed area 201b facing the test trace 4, that is, the thickness of the first substrate 111 located in the first flat area 201a is greater than the thickness of the first substrate 111 located in the first recessed area 201b, so that the height of the test trace 4 located in the first flat area 201a is higher than the height of the test trace 4 located in the first recessed area 201b, and the height of the first resistor element 18 located in the first flat area 201a is higher than the height of the first resistor element 18 located in the first recessed area 201b, and thus the first groove a is formed in the first substrate 111.

[0105] In an exemplary embodiment, see Fig. 9 As shown, the width W of the first groove a can be 200um to 1500um, for example, 200um, 300um, 500um, 800um, 1000um, 1300um, 1500um, or other values, which are not specifically limited in the present application. The width of the first groove a refers to the distance between the side of the first groove a facing the other first groove a and the side facing away from the other first groove a.

[0106] In an exemplary embodiment, the distance between the surface of the first substrate 111 located in the first flat area 201a facing the test trace 4 and the surface of the first substrate 111 located in the first recessed area 201b facing the test trace 4 may be 1 to 100um, that is, the height difference between the first substrate 111 located in the first flat area 201a and the first substrate 111 located in the first recessed area 201b may be 1 to 100um, for example, 1um, 20um, 50um, 70um, 80um, 100um, or other values, and the present application does not impose any specific limitation on this.

[0107] In an exemplary embodiment, the first resistor element 18 of the display panel 10c with the fourth layer structure may also include a chamfered end 18a, and the inclined surface of the chamfered end 18a may also be filled with the insulating element 6, which is not specifically limited in the present application.

[0108] It can be understood that the sidewall of the first groove a of the display panel 10 of the first layer structure may include four sidewalls, wherein one sidewall is formed by the first substrate 111, and the other three sidewalls are formed by the first resistor element 18. The sidewall of the first groove a of the display panel 10c of the fourth layer structure may include four sidewalls, wherein three sidewalls are formed by the first substrate 111, and the other sidewall is formed by the first resistor element 18.

[0109] In summary, the display panel 10a provided in the embodiment of the present application is not cut, and the first groove a is filled with a conductive solution 41; after the display panel 10 is cut, the conductive solution 41 in the first groove a flows out. Therefore, the test trace 4 is retracted to the side of the binding area 201 facing away from the display area 1, and the conductive tape will not contact the surface of the plurality of test traces 4 exposed in the first groove a, and thus the test trace 4 will not be short-circuited, thereby avoiding poor display of the display panel 10 and improving the reliability of the display panel 10. Moreover, the display panel 10 is not cut, and the test trace 4 is electrically connected to the test component 20 through the conductive solution 41, and thus the test component 20 can provide the test electrical signal to the display panel 10 to test the display panel 10.

[0110] Based on the same inventive concept, please refer to Fig.12 , Fig.12 for Figure 1 The second partial layer structure diagram of the display motherboard is shown in FIG. The second layer structure of the display motherboard 100b and Figure 4 The difference between the display motherboard 100a of the first layer structure shown is that the display motherboard 100b of the second layer structure further includes a first flat area, a first recessed area, a second flat area and a second recessed area. For the description of the similarities between the display motherboard 100b of the second layer structure and the display motherboard 100a of the first layer structure, please refer to the relevant description of the display motherboard 100a of the first layer structure, and for the relevant description of the first flat area 201a and the first recessed area 201b, please refer to the relevant description of the display panel 10c of the fourth layer structure, which will not be repeated here.

[0111] For details, please refer to Fig.13 , Fig.13 for Fig.12The schematic diagram of the planar structure of the display motherboard shown in FIG. In the embodiment of the present application, the test assembly 20 further includes a second flat area 20a and a plurality of second recessed areas 20b, wherein the plurality of second recessed areas 20b are arranged at intervals, and a portion of the circumference of each second recessed area 20b is wrapped by the second flat area 20a. One side of the second recessed area 20b is connected to the exposed side of the first recessed area 201b, that is, the side of the second recessed area 20b connected to the first recessed area 201b is not wrapped by the second flat area 20a.

[0112] In an exemplary embodiment, the planar shape of the second recessed area 20b may be a rectangle, three sides of the second recessed area 20b are wrapped by the second flat area 20a, one side of the second recessed area 20b exposes the second flat area 20a and is connected to the side of the first recessed area 201b that exposes the first flat area 201a. The number of the second recessed areas 20b is determined by the number of the conductive traces 24, and the present application does not impose any specific restrictions on this.

[0113] In the implementation mode of this application, please refer to Fig.14 , Fig.14 for Fig.12 1 is an enlarged schematic diagram of the structure XIIII in the display motherboard described in . A portion of the second substrate 23 is located in the second flat area 20a, and another portion is located in the second recessed area 20b. A portion of the conductive trace 24 is located in the second flat area 20a, and another portion is located in the second recessed area 20b. A portion of the second resistor element 26 is located in the second flat area 20a, and another portion is located in the second recessed area 20b.

[0114] In the implementation mode of this application, please refer to Fig.12 , the second groove b is located in the second concave area 20b, and the highest point of the side wall of the second groove b is less than or equal to the height of the surface of the second substrate 23 located in the second flat area 20a facing the conductive trace 24. That is, the entire second groove b is below the surface of the second substrate 23 located in the second flat area 20a facing the conductive trace 24, that is, the second groove b is formed in the second substrate 23. The height refers to the distance from the reference plane (the surface of the second substrate 23 facing away from the conductive trace 24 is the reference plane) to the second substrate 23 facing the second resistor 26.

[0115] It is understandable that by forming the second groove b in the second substrate 23, there is no need to form the second resistor element 26 on the side of the second groove b, and the conductive solution 41 can be directly injected into the second groove b, thereby simplifying the manufacturing process of the display motherboard.

[0116] In an exemplary embodiment, a surface of the second resistor element 26 located in the second recessed area 20 b facing away from the second groove b is aligned with a surface of the second substrate 23 located in the second flat area 20 a facing the conductive trace 24 .

[0117] In an exemplary embodiment, the height of the surface of the second substrate 23 located in the second flat area 20a facing the conductive trace 24 is higher than the height of the surface of the second substrate 23 located in the second recessed area 20b facing the conductive trace 24, that is, the thickness of the second substrate 23 located in the second flat area 20a is greater than the thickness of the second substrate 23 located in the second recessed area 20b, so that the height of the conductive trace 24 located in the second flat area 20a is higher than the height of the conductive trace 24 located in the second recessed area 20b, and the height of the second resistor element 26 located in the second flat area 20a is higher than the height of the second resistor element 26 located in the second recessed area 20b, and thus the second groove b is formed in the second substrate 23.

[0118] It can be understood that the sidewall of the second groove b of the display motherboard 100a of the first layer structure may include four sidewalls, wherein one sidewall is formed by the second substrate 23, and the other three sidewalls are formed by the second resistor element 26. The sidewall of the second groove b of the display motherboard 100b of the second layer structure may include four sidewalls, wherein three sidewalls are formed by the second substrate 23, and the other sidewall is formed by the second resistor element 26.

[0119] See also Fig.15 , Fig.15 Schematic diagram of the layer structure of the display device disclosed in the third embodiment of the present application. In the embodiment of the present application, the display device 200 may include a stacked display panel and a backlight module, the display panel is arranged on the light-emitting side of the backlight module, and the display panel is used to display an image under the backlight provided by the backlight module.

[0120] In the implementation manner of the present application, the backlight module may be an edge-lit backlight module or a direct-lit backlight module, and the present application does not impose any specific limitation on this.

[0121] It can be understood that the display device can be used in electronic devices including but not limited to tablet computers, laptop computers, desktop computers, mobile phones, car displays, etc. According to the embodiment of the present invention, the specific type of the display device is not particularly limited, and those skilled in the art can design it accordingly according to the specific use requirements of the display device, which will not be repeated here.

[0122] In an exemplary embodiment, the display device may also include other necessary components and parts such as a driving board, a power board, a high-voltage board, and a key control board. Those skilled in the art may make corresponding supplements based on the specific type and actual functions of the display device, which will not be repeated here.

[0123] In summary, the display device provided in the embodiment of the present application includes a display panel and a backlight module, the display panel 10a is not cut, and the first groove a is filled with a conductive solution 41; after the display panel 10 is cut, the conductive solution 41 in the first groove a flows out. Therefore, the test trace 4 is retracted to the side of the binding area 201 facing away from the display area 1, and the conductive tape will not contact the surface of the plurality of test traces 4 exposed in the first groove a, and thus the test trace 4 will not be short-circuited, thereby avoiding poor display of the display panel 10 and improving the reliability of the display panel 10. Moreover, the display panel 10 is not cut, and the test trace 4 is electrically connected to the test component 20 through the conductive solution 41, and thus the test component 20 can provide the test electrical signal to the display panel 10 to test the display panel 10.

[0124] Based on the same inventive concept, the third embodiment of the present application also provides a method for manufacturing a display motherboard, for manufacturing Figure 4 and Fig.12 For the display motherboard related contents involved in the display motherboard manufacturing method provided in the third embodiment of the present application, please refer to the relevant description of the display motherboard in the above embodiment, which will not be repeated here. Fig.16 , Fig.16 This is a schematic flow chart of a method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The method for manufacturing a display motherboard may include the following steps.

[0125] S10 , providing an array substrate assembly, wherein the array substrate assembly includes a first substrate 111 and a second substrate 23 .

[0126] S20 , forming a conductive layer on the first substrate 111 and the second substrate 23 .

[0127] S30, forming the conductive layer into a plurality of test traces 4 and a plurality of conductive traces 24, and forming an accommodation space between the test traces 4 and the conductive traces 24, wherein the accommodation space includes a first groove a and a second groove b, the test traces 4 and the first groove a are located on the first substrate 111, and the conductive traces 24 and the second groove b are located on the second substrate 23.

[0128] S40, filling the containing space with a conductive solution 41.

[0129] S50, forming at least a partial resistance component on the side of the test trace 4 facing away from the first substrate 111 and on the side of the conductive trace 24 facing away from the second substrate 23, so that the resistance component covers the conductive solution 41, wherein the resistance component includes a first resistance element 18 and a second resistance element 26, the first resistance element 18 is located on the test trace 4, and the second resistance element 26 is located on the conductive trace 24.

[0130] It can be understood that in step S10, the provided array substrate assembly has a color film substrate assembly, that is, the array substrate assembly and the color film substrate assembly have been aligned; or, after step S50, the array substrate assembly and the color film substrate assembly are aligned, and the present application does not impose specific restrictions on this. Among them, the color film substrate assembly includes a plurality of color film substrates, and the alignment refers to the process of aligning the array substrate assembly with the color film substrate assembly, and bonding the array substrate assembly and the color film substrate assembly together by means of a sealing adhesive. In step S10, the provided array substrate assembly has a test element 21 formed thereon; or, in step S30, the test element 21 can be formed by the conductive layer 60 through a photolithography process, and the present application does not impose specific restrictions on this.

[0131] In a specific embodiment of the present application, the method for manufacturing the display motherboard is used to form Figure 4 The display motherboard 100a shown in the figure, the manufacturing method of the display motherboard may include the following steps.

[0132] S10a, providing an array substrate assembly, wherein the array substrate assembly includes a first substrate 111 and a second substrate 23 .

[0133] Specifically, an array substrate assembly is provided, the array substrate assembly includes a plurality of array substrates, the array substrate includes a first substrate 111, a driving circuit layer 113 and an insulating layer 115 which are stacked in sequence. The array substrate assembly also includes a second substrate 23, the first substrate 111 and the second substrate 23 are arranged in the same layer and connected, and a portion of the first substrate 111 is exposed and at least a portion of the second substrate 23 is exposed.

[0134] In an exemplary embodiment, the first substrate 111 and the second substrate 23 are integrally formed.

[0135] S20a, forming a conductive layer 60 on the first substrate 111 and the second substrate 23 .

[0136] For details, please refer to Fig.17 , Fig.17The conductive layer 60 is formed on the side of the first substrate 111 where the first driving circuit layer 113 is formed, and the conductive layer 60 also covers the second substrate 23 .

[0137] In an exemplary embodiment, the material of the conductive layer 60 may include, but is not limited to, any one or more of metal materials such as platinum, gold, aluminum, copper, titanium, silver, chromium, and nickel, and the present application does not impose any specific limitation on this.

[0138] S30a, forming the conductive layer into multiple test traces 4 and multiple conductive traces 24, and forming an accommodation space between the test traces 4 and the conductive traces 24, wherein the accommodation space includes a first groove a and a second groove b, the test traces 4 and the first groove a are located on the first substrate 111, and the conductive traces 24 and the second groove b are located on the second substrate 23.

[0139] In the implementation mode of this application, please refer to Fig.18 , Fig.18 This is a flow chart of step S30a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. Step S30a may specifically include the following steps.

[0140] S31a, forming the conductive layer 60 into a plurality of the test traces 4 and a plurality of the conductive traces 24 .

[0141] For details, please refer to Fig.19 , Fig.19 The schematic diagram is a structural diagram corresponding to step S31a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. The conductive layer 60 is formed into a plurality of the test traces 4 and a plurality of the conductive traces 24 by a photolithography process. The photolithography process includes processes such as exposure and development.

[0142] In an exemplary embodiment, the plurality of test traces 4 on the first substrate 111 are arranged at intervals, and the plurality of conductive traces 24 on the second substrate 23 are arranged at intervals. One test trace 4 is arranged opposite to one conductive trace 24, and the plurality of test traces 4 and the plurality of conductive traces 24 may be distributed along the cutting line Q in an axisymmetric manner.

[0143] S32a, forming part of the resistor component 70 on the side of the first substrate 111 where the test trace 4 is formed and on the side of the second substrate 23 where the conductive trace 24 is formed, the test trace 4, the conductive trace 24 and the resistor component 70 surround each other to form the accommodating space 80.

[0144] For details, please refer to Fig. 20 , Fig. 20 The structure diagram corresponding to step S32a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application is shown in FIG. A portion of the resistor assembly 70 is formed on the side of the first substrate 111 where the test trace 4 is formed and on the side of the second substrate 23 where the conductive trace 24 is formed. The resistor assembly 70 includes a plurality of first resistor elements 18 and a plurality of second resistor elements 26. The test trace 4, the conductive trace 24, a portion of the first resistor elements 18, and a portion of the second resistor elements 26 are surrounded to form the accommodation space 80.

[0145] In an exemplary embodiment, parts of two first resistance elements 18 and the test trace 4 form the first groove a, and parts of two second resistance elements 26 and the conductive trace 24 form the second groove b.

[0146] In an exemplary embodiment, there may be a plurality of accommodating spaces 80 .

[0147] S40a, filling the containing space 80 with a conductive solution 41 .

[0148] For details, please refer to Fig.21 , Fig.21 The structure diagram corresponding to step S40a of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application is as follows: a conductive solution 41 is filled in the accommodation space 80, and the conductive solution 41 is connected to the test trace 4 and the conductive trace 24 respectively, so as to electrically connect the test trace 4 with the conductive trace 24.

[0149] S50a, forming a portion of the resistor component 70 on the side of the conductive solution 41 facing away from the first substrate 111 and the side facing away from the second substrate 23.

[0150] For details, please refer to Figure 4 The resistor component 70 includes a plurality of first resistor elements 18 and a plurality of second resistor elements 26. Part of the first resistor elements 18 are formed on a side of the conductive solution 41 facing away from the first substrate 111, and part of the second resistor elements 26 are formed on a side of the conductive solution 41 facing away from the second substrate 23.

[0151] It can be understood that the part of the resistance assembly 70 formed in step S30a and the part of the resistance assembly 70 formed in step 50a constitute the complete resistance assembly 70. Accordingly, the part of the first resistance element 18 formed in step S30a and the part of the first resistance element 18 formed in step 50a constitute the complete first resistance element 18, and the part of the second resistance element 26 formed in step S30a and the part of the second resistance element 26 formed in step 50a constitute the complete second resistance element 26.

[0152] In another specific embodiment of the present application, the method for manufacturing the display motherboard is used to form Fig.12 The display motherboard 100b shown in the figure, the manufacturing method of the display motherboard may include the following steps.

[0153] S10b, providing an array substrate assembly, the array substrate assembly comprising a first substrate 111 and a second substrate 23. Part of the first substrate 111 is located in the first flat area 201a, and part of the first substrate 111 is located in the first recessed area 201b, and the thickness of the first substrate 111 located in the first flat area 201a is greater than the thickness of the first substrate 111 located in the first recessed area 201b. Part of the second substrate 23 is located in the second flat area 20a, and another part of the second substrate 23 is located in the second recessed area 20b, and the thickness of the second substrate 23 located in the second flat area 20a is greater than the thickness of the second substrate 23 located in the second recessed area 20b.

[0154] S20b, forming a conductive layer 60 on the first substrate 111 and the second substrate 23 .

[0155] Specifically, Fig. 22 This is a structural schematic diagram corresponding to step S20b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application. A conductive layer 60 is formed on the first substrate 111 and the second substrate 23, wherein a portion of the conductive layer 60 is located in the first flat area 201a and the second flat area 20a, and another portion is located in the first recessed area 201b and the second recessed area 20b, and the height of the conductive layer 60 located in the first recessed area 201b and the second recessed area 20b is lower than the height of the conductive layer 60 located in the first flat area 201a and the second flat area 20a.

[0156] S30b, forming the conductive layer 60 into a plurality of test traces 4 and a plurality of conductive traces 24, and forming an accommodation space 80 between the first substrate 111, the second substrate 23, the test traces 4 and the conductive traces 24, wherein the accommodation space 80 includes a first groove a and a second groove b, the test traces 4 and the first groove a are located on the first substrate 111, and the conductive traces 24 and the second groove b are located on the second substrate 23.

[0157] Specifically, Fig.23 The schematic diagram of the structure corresponding to step S30b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application is as follows: the conductive layer 60 is formed into a plurality of the test traces 4 and a plurality of the conductive traces 24 by a photolithography process, the first substrate 111 and the test traces 4 form the first groove a, and the second substrate 23 and the conductive traces 24 form the second groove b.

[0158] In an exemplary embodiment, part of the test traces 4 are located in the first flat area 201a, and another part of the test traces 4 are located in the first recessed area 201b, and the height of the test traces 4 located in the first flat area 201a is higher than the height of the test traces 4 located in the first recessed area 201b. Part of the conductive traces 24 are located in the second flat area 20a, and another part of the conductive traces 24 are located in the second recessed area 20b, and the height of the conductive traces 24 located in the second flat area 20a is higher than the height of the conductive traces 24 located in the second recessed area 20b.

[0159] In an exemplary embodiment, the first groove a is located in the first recessed area 201 b , and the second groove b is located in the second recessed area 20 b .

[0160] S40b, filling the containing space 80 with a conductive solution 41 .

[0161] Specifically, Fig.24 The structure diagram corresponding to step S40b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application is as follows: a conductive solution 41 is filled in the accommodating space 80, and the conductive solution 41 is connected to the test trace 4 and the conductive trace 24 respectively, so as to electrically connect the test trace 4 with the conductive trace 24.

[0162] In an exemplary embodiment, the conductive solution 41 is located in the first recessed area 201 b and the second recessed area 20 b .

[0163] S50b, forming all the resistor components 70 on the side of the conductive solution 41 facing away from the first substrate 111 and the second substrate.

[0164] Specifically, Fig.25 The structure diagram corresponding to step S50b of the method for manufacturing a display motherboard disclosed in the third embodiment of the present application is shown in FIG. The resistor assembly 70 includes a plurality of first resistor elements 18 and a plurality of second resistor elements 26. The first resistor elements 18 are formed on the side of the conductive solution 41 facing away from the first substrate 111 and the side of the test trace 4 facing away from the first substrate 111. The second resistor elements 26 are formed on the side of the conductive solution 41 facing away from the second substrate 23 and the side of the conductive trace 24 facing away from the second substrate 23.

[0165] In an exemplary embodiment, part of the first resistor element 18 is located in the first flat area 201a, another part of the first resistor element 18 is located in the first recessed area 201b, and the height of the first resistor element 18 located in the first flat area 201a is higher than the height of the first resistor element 18 located in the first recessed area 201b. Part of the second resistor element 26 is located in the second flat area 20a, another part of the second resistor element 26 is located in the second recessed area 20b, and the height of the second resistor element 26 located in the second flat area 20a is higher than the height of the second resistor element 26 located in the second recessed area 20b.

[0166] In an exemplary embodiment, the first resistor element 18 and the second resistor element 26 are integrally formed.

[0167] In summary, the manufacturing method of the display motherboard provided in the embodiment of the present application includes: providing an array substrate assembly, the array substrate assembly includes a first substrate 111 and a second substrate 23; forming a plurality of test traces 4 and a plurality of conductive traces 24 from the conductive layer, and forming a containing space between the test traces 4 and the conductive traces 24; filling the containing space with a conductive solution 41; forming a partial resistor component or a resistor component on the side of the test traces 4 facing away from the first substrate 111 and the side of the conductive traces 24 facing away from the second substrate 23, and the resistor component covers the conductive solution 41. Therefore, by filling the containing space with the conductive solution 41, when the display motherboard is cut, the conductive solution 41 in the containing space flows out, the test traces 4 shrink in the first substrate 111, the conductive tape will not be connected to the plurality of test traces 4, and thus the test traces 4 will not be short-circuited, thereby avoiding the display failure of the display panel and improving the reliability of the display panel. Moreover, when the display motherboard is not cut, the test trace 4 is electrically connected to the conductive trace 24 through the conductive solution 41, so that the test trace can receive a test electrical signal to test the display panel.

[0168] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0169] It should be understood that the application of this application is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this application. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments are implemented, and equivalent changes made according to the claims of this application still fall within the scope covered by this application.

Claims

1. A display panel, comprising a display area and a binding area arranged on one side of the display area, characterized in that: The display panel comprises an array substrate, the array substrate comprises a first substrate, a portion of the first substrate is located in the binding area; The display panel further includes a plurality of test traces and a plurality of first resistor elements, wherein the test traces are arranged on one side of the first substrate and located in the binding area and are electrically connected to the array substrate, the first resistor element partially covers the test traces on the first substrate, the first resistor element, the test traces and the first substrate are surrounded to form a first groove, and the opening of the first groove faces the side of the binding area facing away from the display area; wherein, The first groove is used to fill a conductive solution. After the display panel is formed, the conductive solution in the first groove flows out.

2. The display panel according to claim 1, wherein: The display panel further includes a plurality of insulating elements, and the insulating elements are filled in the first groove to insulate the surface of the test wiring facing away from the display area and to support the first resistance element.

3. The display panel according to claim 1, wherein: The first resistor element further includes a chamfered end, and the chamfered end is an end of the first resistor element facing away from the display area; wherein, In the direction in which the test line points to the first resistor element, the inclined surface of the chamfered end is inclined toward the direction in which the display area is located; or, In the direction in which the first resistance element points to the test wiring, the inclined surface of the chamfered end is inclined toward the direction in which the display area is located.

4. The display panel according to claim 1, wherein: The binding area further includes a first flat area and a plurality of first recessed areas, the area where the first groove is located is the first recessed area, wherein the plurality of first recessed areas are arranged at intervals, and a portion of the circumference of each first recessed area is wrapped by the first flat area; The first groove is located in the first recessed area, and the highest point of the sidewall of the first groove is less than or equal to the height of the surface of the first substrate located in the first flat area facing the test trace.

5. A display device, characterized in that: It comprises a backlight module and a display panel as claimed in any one of claims 1 to 4, wherein the display panel is arranged on the light emitting side of the backlight module.

6. A display motherboard, characterized in that: The invention comprises a test component and a plurality of display panels as claimed in any one of claims 1 to 4, wherein the test component comprises a second substrate, a plurality of conductive traces and a plurality of second resistance elements, wherein the second substrate is connected to the first substrate and arranged in the same layer, the conductive traces and the test traces are arranged in the same layer and spaced apart, the second resistance element partially covers the conductive traces on the second substrate, and is connected to the first resistance element and arranged in the same layer; the second substrate, the conductive traces and the second resistance elements are surrounded to form a second groove, the opening of the second groove faces the opening of the first groove and is connected to the first groove; wherein, The first groove and the second groove are filled with a conductive solution, and the conductive solution is in contact with the test trace and the conductive trace respectively, so as to electrically connect the test trace and the conductive trace.

7. The display motherboard according to claim 6, characterized in that: The binding area further includes a first flat area and a plurality of first recessed areas, the area where the first groove is located is the first recessed area, wherein the plurality of first recessed areas are arranged at intervals, and a portion of the circumference of each first recessed area is wrapped by the first flat area; The first groove is located in the first recessed area, and the highest point of the sidewall of the first groove is less than or equal to the height of the surface of the first substrate located in the first flat area facing the test trace.

8. The display motherboard according to claim 7, characterized in that: The test assembly further includes a second flat area and a plurality of second recessed areas, the area where the second groove is located is the second recessed area, the plurality of second recessed areas are arranged at intervals, a portion of the circumference of each second recessed area is wrapped by the second flat area, and one side of the second recessed area is connected to one side of the first recessed area; The second groove is located in the second recessed area, and the highest point of the sidewall of the second groove is less than or equal to the height of the surface of the second substrate located in the second flat area facing the conductive trace.

9. The display motherboard according to any one of claims 6 to 8, characterized in that: The conductive solution includes 90% to 98% by weight of a conductive material and 2% to 10% by weight of an auxiliary material, wherein the conductive material is used for conducting electricity, and the auxiliary material is used for increasing the fluidity of the conductive solution.

10. A method for manufacturing a display motherboard, characterized in that: Used to manufacture the display motherboard according to any one of claims 6 to 9, the manufacturing method of the display motherboard comprising: An array substrate assembly is provided, wherein the array substrate assembly comprises a first substrate and a second substrate; forming a conductive layer on the first substrate and the second substrate; The conductive layer is formed into a plurality of test traces and a plurality of conductive traces, and a containing space is formed between the test traces and the conductive traces, wherein the containing space comprises a first groove and a second groove, the test traces and the first groove are located on the first substrate, and the conductive traces and the second groove are located on the second substrate; Filling the containing space with a conductive solution; At least a partial resistance component is formed on the side of the test trace facing away from the first substrate and on the side of the conductive trace facing away from the second substrate, so that the resistance component covers the conductive solution, wherein the resistance component includes a first resistance element and a second resistance element, the first resistance element is located on the test trace, and the second resistance element is located on the conductive trace.

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