Clock swing increasing circuit, on-chip high voltage generating circuit and electronic device

Abstract

Disclosed are a clock swing increasing circuit, an on-chip high-voltage generating circuit and an electronic device. The clock swing increasing circuit includes: an input terminal, receiving a first clock signal; an output terminal; a capacitor, a first end receiving a second clock signal with a falling edge delay, and a second end connected to the output terminal; a first NMOS transistor, a source connected to the ground, a drain connected to the output terminal, and a gate receiving a third clock signal; a second switch connected between the power supply terminal and the output terminal; wherein, when the first and second clock signals are high, the first NMOS transistor is disconnected and the second switch is turned on, when the first clock is low and the second clock is high, the first NMOS transistor is turned on and the second switch is disconnected, when the first and second clock signals are low, the second switch is disconnected, and the first NMOS transistor is used as a diode with a gate-source short-circuited circuit. The present invention provides a clock signal with an increased swing range by combining a capacitor with an NMOS tube with a source-drain short-circuited circuit in a specific period of time, for example, a swing of -V TH to V DD clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a clock swing increasing circuit, an on-chip high-voltage generating circuit, and an electronic device. Background Art

[0002] Common integrated circuit chip power supply voltages include 3V, 1.8V, and 1.2V. However, some specialized chips, such as flash memory chips, require internal operations at a voltage higher than the power supply voltage. In these cases, a voltage conversion circuit is built into the chip to generate a higher voltage. Another example is a display panel, where driving its pixel array also requires a voltage higher than the power supply voltage.

[0003] Since inductors are not easy to implement and integrate on a chip, MOS capacitors, MOS switches, and other components that can be easily integrated on a chip are usually used to implement DC-DC conversion circuits, such as charge pumps. Figure 1 This figure shows an example of a charge pump used in an integrated circuit chip. In this four-stage Dickson charge pump, MOS transistors (MD1-MD5) are connected in series between the input and output terminals and diode-connected. Capacitors C1-C4 are connected to the clock and inverted clock (φ1 and φ2), respectively. Cf acts as a current limiter.

[0004] In actual operation, the input terminal is connected to the power supply voltage V DD The voltage of the odd-numbered capacitors and the even-numbered capacitors increases and decreases in different half-clock cycles, and under the unidirectional conduction of the diode, a high level V is output at the output end. HH .

[0005] As semiconductor process nodes continue to improve, the power supply voltage of integrated circuit chips has gradually decreased, while the high voltage inside the chip, such as that used for flash memory programming and erasing, has remained basically unchanged. This makes the charge pump circuit less efficient at low power supply voltages.

[0006] Therefore, a solution is needed to improve the working efficiency of the charge pump inside the chip. Summary of the Invention

[0007] A technical problem to be solved by the present disclosure is to provide a clock swing increasing circuit, which can provide a clock signal with an increased swing range by combining a capacitor with an NMOS transistor whose source and drain are shorted in a specific period of time, for example, a swing of -V TH to V DD This enables a more efficient on-chip high-voltage generation circuit.

[0008] According to a first aspect of the present disclosure, a clock swing increasing circuit is provided, comprising: an input terminal for receiving a first clock signal; an output terminal; a capacitor, wherein a first end of the capacitor receives a second clock signal and a second end is connected to the output terminal, the second clock signal and the first clock signal having the same rising edge, and a falling edge of the second clock signal being delayed compared to the falling edge of the first clock signal; a first NMOS transistor, wherein a source of the first NMOS transistor is grounded, a drain is connected to the output terminal, and a gate receives a third clock signal, the third clock signal being at a low level when the first clock signal and the second clock signal are at the same level, and at a high level when the levels are different; and a second switch connected between a power supply terminal and the output terminal; wherein, when the first clock signal and the second clock signal are both at a high level, the first NMOS transistor is turned off and the second switch is turned on; when the first clock signal is at a low level and the second clock signal is at a high level, the first NMOS transistor is turned on and the second switch is turned off; and when the first clock signal and the second clock signal are both at a low level, the second switch is turned off, and the first NMOS transistor functions as a diode with a gate-source short circuit.

[0009] Optionally, the second switch is a first PMOS transistor, a source of the first PMOS transistor is connected to the power terminal, a drain is connected to the output terminal, and a gate is connected to the inverse signal of the first clock signal.

[0010] Optionally, the clock swing increasing circuit further includes: a second PMOS transistor, wherein the source and drain of the second PMOS transistor are connected between the source of the first PMOS transistor and the power terminal, the gate of the second PMOS transistor is grounded, and the substrate receives the second clock signal.

[0011] Optionally, the first PMOS transistor M2 and the second PMOS transistor M3 are arranged in different N-wells, and the N-well of the second PMOS transistor M3 receives the second clock signal.

[0012] Optionally, the clock swing increasing circuit further includes: a buffer, a first end of the buffer receives the second clock signal, and a second end of the buffer is connected to the first end of the capacitor.

[0013] Optionally, the clock swing increasing circuit further includes: a falling edge delay circuit, wherein an input end of the falling edge delay circuit receives the first clock signal, and an output end of the falling edge delay circuit outputs the second clock signal.

[0014] Optionally, the clock swing increase circuit also includes: a logic gate circuit for generating the third clock signal based on the first clock signal and the second clock signal, and including: receiving the first clock signal as a first input, the inverted signal of the second clock signal as a second output, and outputting an exclusive OR result as the third clock signal, or receiving the inverted signal of the first clock signal as a first input, the second clock signal as a second output, and outputting an AND result as the third clock signal.

[0015] According to a second aspect of the present disclosure, an on-chip high-voltage generation circuit is provided, comprising: a clock swing increasing circuit as described in the first aspect, wherein the clock swing increasing circuit outputs a low-value clock signal lower than the ground voltage; and a charge pump circuit, which obtains the high-value boosted clock signal as a clock signal of the charge pump circuit.

[0016] According to a third aspect of the present disclosure, there is provided an on-chip high-voltage generating circuit according to the second aspect.

[0017] Optionally, the electronic device is a memory or a display device.

[0018] Therefore, the clock swing increase circuit controls the diode conduction of the NMOS tube when the capacitor is discharged through the clock signal, the falling delayed clock signal, and the signal that changes only during the delay period, thereby pulling the low value of the clock down to -V TH , in order to provide a clock with a larger swing, thereby enabling a more efficient on-chip high-value boost circuit and improving the performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0020] Figure 1 An example of a charge pump used in an integrated circuit chip is shown.

[0021] Figure 2 FIG. 4 is a circuit diagram showing a clock swing increasing circuit according to an embodiment of the present invention.

[0022] Figure 3 FIG. 4 is a circuit diagram showing a clock swing increasing circuit according to an embodiment of the present invention.

[0023] Figure 4 Shown Figure 2 and Figure 3 The timing diagram of the clock swing increase circuit when it is working is shown.

[0024] Figure 5 FIG. 4 is a circuit diagram showing a clock swing increasing circuit according to an embodiment of the present invention.

[0025] Figure 6 An example of the configuration of a falling edge delay circuit is shown.

[0026] Figure 7 FIG. 4 is a circuit diagram showing a clock swing increasing circuit according to an embodiment of the present invention.

[0027] Figure 8 Shown Figure 7 The timing diagram of the clock swing increase circuit when it is working is shown.

[0028] Figure 9 FIG. 1 shows a configuration example of an on-chip high-voltage generating circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the specified features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0032] The disclosure below provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, these are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0033] As mentioned earlier, certain types of integrated circuit chips require high voltage levels for their internal operations. For example, flash memory chips require a relatively constant high voltage for programming and erasing even when the power supply voltage decreases. The generation of this high voltage relies on on-chip high-voltage circuitry.

[0034] When the chip voltage gradually decreases and the high voltage demand inside the chip remains basically unchanged (i.e., V DD Lower, V HH The existing high-voltage generation circuit requires more levels of charge pumps and has low working efficiency.

[0035] In order to better improve the swing of the high-voltage charge pump in a special integrated circuit chip (for example, a flash memory chip), the present invention proposes a driving circuit, which can be used as a clock swing increase circuit, connected after the oscillator circuit for providing a clock signal, and improves the efficiency of the power supply voltage conversion charge pump by providing a lower clock signal, thereby reducing power consumption.

[0036] Figure 2 FIG. 4 is a circuit diagram showing a clock swing increasing circuit according to an embodiment of the present invention.

[0037] The input terminal of the clock swing increasing circuit can receive a clock signal CLK as a circuit input. Here, the clock signal CLK can be a rectangular wave signal generated by an oscillator, for example, the high level is equal to the power supply voltage V DD , low level equal to V SS (For example, V SS A rectangular wave signal having the same duration of high and low levels as 0 may be referred to as a "first clock signal" hereinafter. In this article, an inverted signal of the clock signal CLK may also be used, and the inverted signal may be represented as an inverted clock signal CLK B , and can be obtained by connecting the clock signal CLK to the inverter (NOT gate). It should be understood that in the inverted clock signal CLK B Switching is performed under the control of the clock signal CLK, which can also be regarded as switching under the control of the clock signal CLK, except that the high and low levels of the control are in opposite directions.

[0038] Figure 2The circuit also uses CLK D Here, CLK D It can be a falling edge delayed clock signal. Here, the falling edge delayed clock signal refers to a clock signal whose high level starting position is the same as CLK, but the low level starting position is slightly delayed. When the clock signal CLK is low level 0V and high level V DD When the high and low level durations are the same, the falling edge delayed clock signal CLK D Similarly, the low level can be 0V and the high level can be V DD The rectangular wave signal is a bit delayed, but the high level duration is longer than the low level duration due to the slight delay of the low level transition. D It is called the "second clock signal". In this article, the clock signal CLK with a falling edge delay can also be used. D The inverted signal can be expressed as an inverted falling edge delayed clock signal CLK DB , and can be clocked by the clock signal CLK D It should be understood that the clock signal CLK delayed by the falling edge of the inverted DB Switching is controlled by the clock signal CLK, which can also be seen as a clock signal delayed by the falling edge. D The switch is controlled by , but the high and low levels are controlled in opposite directions.

[0039] Figure 2 The circuit also uses the clock signal CLK A Here, CLK A It can be the clock signal CLK with falling edge delay as described above. D The clock signal CLK is obtained through a specific logic gate. In the following, the clock signal CLK A It is called the "third clock signal". The clock signal CLK A When the first and second clock signal levels are the same, it is a low level, and when the first and second clock signal levels are different, it is a high level. In other words, the clock signal CLK A The first clock signal may be at a high level during a small period when the first clock signal jumps to a low level and the second clock signal still remains at a high level due to a falling edge delay, and may be at a low level during the remaining periods.

[0040] Figure 2 The clock swing increasing circuit 1 shown may include an input terminal for receiving a first clock signal CLK. Although the input of CLK is not directly shown in the figure, it can be understood that the CLK in the figure B , CLK D and CLK AThey are all obtained after a specific logic transformation is performed on the first clock signal.

[0041] As shown in the figure, the clock swing increasing circuit 1 may include an output terminal OUT, a capacitor C, a first transistor M1 (implemented as an NMOS transistor) and a second switch S2. A The second switch S2 is controlled by the clock signal CLK B Control, capacitor C is directly affected by the clock signal CLK D control.

[0042] Specifically, the first terminal of the capacitor C receives the second clock signal CLK D The source of the first NMOS transistor M1 is grounded, the drain is connected to the output terminal OUT, and the gate receives the third clock signal CLK A The second switch S2 is connected between the power supply terminal and the output terminal OUT, and is driven by the first clock signal CLK (actually the inverted CLK). B control).

[0043] When the first clock signal and the second clock signal are both high, the first NMOS transistor M1 is turned off and the second switch S2 is turned on. When the first clock signal is low and the second clock signal is high, the first NMOS transistor M1 is turned on and the second switch S2 is turned off. When the first clock signal and the second clock signal are both low, the second switch S2 is turned off, and the first NMOS transistor M1 functions as a diode with a gate-source short circuit.

[0044] In one embodiment, the second switch S2 may be implemented as a first PMOS transistor M2 . Figure 3 FIG. 1 shows a circuit diagram of a clock swing increasing circuit according to an embodiment of the present invention. Figure 3 middle, Figure 2 The switch S2 shown is embodied as a PMOS transistor M2. Specifically, the source of the PMOS transistor M2 is connected to the power supply terminal, the drain is connected to the output terminal OUT, and the gate is connected to the inverted signal of the first clock signal, that is, the clock signal CLK B .

[0045] Figure 4 Shown Figure 2 and Figure 3 The following is a timing diagram of the clock swing amplification circuit during operation. For ease of explanation, the diagram indicates phases I, II, and III within a clock cycle. It should be understood that each clock cycle may include phases I, II, and III.

[0046] The following will be combined Figure 4The components and working principle of the clock swing increasing circuit 1 are further described.

[0047] Specifically, the input terminal of the clock swing increasing circuit 1 receives the first clock signal CLK, and the first terminal of the capacitor C of the clock swing increasing circuit 1 receives the delayed second clock signal CLK D Among them, the second clock signal CLK D The second clock signal CLK has the same rising edge as the first clock signal CLK. D The falling edge of the first clock signal CLK is delayed, as shown in FIG. Figure 4 As shown, the first clock signal CLK and the second clock signal CLK D The second clock signal CLK has the same period. D The falling edge of the first clock signal CLK is delayed by a certain time (e.g., the time length of the phase II in the figure is a delay of Tdelay) than the falling edge of the first clock signal CLK. In each cycle, the low level of the first clock signal CLK and the second clock signal CLK D The high level starting position of the second clock signal CLK D The low level start position of the first clock signal CLK is later than the low level start position of the first clock signal CLK. The low level of the first clock signal CLK and the second clock signal CLK D The low level of the first clock signal CLK and the low level of the second clock signal CLK have the same magnitude, for example, 0V. D The high levels have the same amplitude, for example, they are all power supply voltage V DD For example, a first clock signal CLK is generated by an oscillator, and a second clock signal CLK is generated based on the first clock signal CLK by a falling edge delay circuit. D .

[0048] Accordingly, the third clock signal CLK for controlling the NMOS transistor M1 A Based on the first clock signal CLK and the second clock signal CLK D In each cycle, the third clock signal CLK A The high level starting position of the third clock signal CLK is the same as the low level starting position of the first clock signal CLK. A The high level end position and the second clock signal CLK D In other words, the low level starting position of the third clock signal CLK A The third clock signal CLK has a high level only during the period when the second clock signal is delayed and falls (ie, the subsequent phase II), and has a low level in other periods. A The low level of the first clock signal CLK and the low level of the second clock signal CLKD The low level of the third clock signal CLK has the same magnitude, for example, 0V. A The high level of the first clock signal CLK and the high level of the second clock signal CLK D The high levels have the same amplitude, for example, they are all power supply voltage V DD .

[0049] like Figure 4 As shown, the first clock signal CLK and the second clock signal CLK D and the third clock signal CLK A The cycle can be divided into three stages. In stage I, the first clock signal CLK and the second clock signal CLK D Both are high level, the third clock signal CLK A In phase II, the first clock signal CLK is at a low level, and the second clock signal CLK D is high level, the third clock signal CLK A In phase III, the first clock signal CLK and the second clock signal CLK D and the third clock signal CLK A Both are low level.

[0050] The following will focus on combining Figure 3 (ie, the second switch S2 is implemented as an instance of the PMOS transistor M2) to describe the circuit states at different stages.

[0051] At time t0, the first clock signal CLK jumps to a high level. Correspondingly, the inverted signal CLK of the first clock signal CLK B jumps to a low level, and the third clock signal CLK A At this time, the PMOS transistor M2 is connected to the power supply voltage (for example, V DD ), the gate is connected to the clock signal CLK B is low (e.g., 0V), so M2’s V GS =-V DD , M2 is turned on. The source of NMOS transistor M1 is grounded, and the gate is connected to the third clock signal CLK A is low (e.g., 0V), so V GS =0, M1 is disconnected. So in phase I, the voltage at the output terminal OUT is V DD Since the second clock signal CLK D is high (for example, V DD ), so there is no voltage difference between the two ends of capacitor C, both are V DD .

[0052] At time t1, the first clock signal CLK changes to a low level. Accordingly, the inverted signal CLK of the first clock signal CLK B jumps to a low level, and the third clock signal CLK A The second clock signal CLK D Maintained at a high level. Since the gate receives the clock signal CLK B It jumps to low level, so M2 is disconnected. And M1 is disconnected due to the clock signal CLK received by its gate. A It jumps to high level, so M1 is turned on. Thus, the level of the output terminal OUT is pulled down to the ground voltage V SS (For example, 0V). Then in phase II, the output terminal OUT voltage is V SS Since the second clock signal CLK D Keep it high (for example, V DD ), so there is a voltage difference across the capacitor C, which is equal to V DD -V SS . In V SS =0V, the voltage difference can be considered as V DD .

[0053] At time t2, the first clock signal CLK remains at a low level. Accordingly, the inverted signal CLK of the first clock signal CLK B remains at a low level, and the third clock signal CLK A The second clock signal CLK D Jump to low level. Because the gate receives the clock signal CLK B is still low, so M2 remains off. At this time, M1 receives the clock signal CLK A The voltage of the output terminal OUT is V DD In the phase III, due to the second clock signal CLK D The voltage level of the capacitor C is changed to a low level (eg, 0), and the voltage difference (eg, V DD ), so the capacitor C will pull the voltage of the output terminal OUT to a negative value (for example, -V DD ), since this negative value is greater than the threshold voltage V TH , so that the diode formed by the gate-source short of M1 can be turned on, thereby stabilizing the voltage of the output terminal OUT to the threshold voltage of M1 -V TH .

[0054] At time t3, the circuit can repeat the operation of phase I. Thus, the circuit provides a reverse conduction voltage to the NMOS transistor short-circuited to form a diode through the capacitor, causing the diode to conduct and pull the voltage down to -V TH , thereby achieving a swing from V DD To -V TH clock circuit.

[0055] Since the voltage of the output terminal OUT will be pulled to a negative value at time t2, in a preferred embodiment, a second PMOS transistor M3 can be additionally added to protect the first PMOS transistor M2. Specifically, the first PMOS transistor M2 and the second PMOS transistor M3 need to be arranged in different N-wells, and the N-well of the second PMOS transistor M3 is connected to the second clock signal CLK. D The first PMOS transistor M2 is connected to avoid being damaged due to a large voltage difference between the first PMOS transistor M2 and the output terminal OUT when the output terminal OUT jumps to a negative value.

[0056] Figure 5 FIG. 1 shows a circuit diagram of a clock swing increasing circuit according to an embodiment of the present invention. Figure 5 In this example, a second PMOS transistor M3 is added between the first PMOS transistor M2 and the output terminal OUT.

[0057] The substrate of the second PMOS transistor M3 is not connected to the source. Since the source and drain of a field effect transistor can be used interchangeably when the source is not connected to the substrate, and the characteristics do not change much, the connection relationship of M3 can be described as the source and drain of the second PMOS transistor M3 being connected between the source of the first PMOS transistor M2 and the power supply terminal OUT. Furthermore, the gate of the second PMOS transistor M3 is grounded, and the substrate (e.g., N-well) is connected to the second clock signal CLK D The introduction of the second PMOS transistor M3 has no effect on the on and off states of the MOS transistors M1 and M2 in phases I, II and III, but since the N well of M3 is connected to the second clock signal CLK D , so at time t2, the N-well voltage can be DD Pull it down to 0, so as to avoid the voltage difference between the N well and the output terminal OUT being too large due to the need to maintain the voltage difference of the capacitor C. For example, when the transistor M3 is not set, the voltage difference can reach 2V at time t2. DD , which can easily cause damage to M2.

[0058] Furthermore, since it is necessary to prevent the voltage difference between the N-well and the output terminal OUT from being too large, it is necessary to ensure that the N-well voltage first increases from V DDThe voltage of the output terminal OUT at the second end of the capacitor C jumps again. To this end, the circuit shown in the figure may include a buffer implemented as two inverters 15 and 16 connected in series. The first end of the buffer receives the second clock signal CLK D , and the second end of the buffer is connected to the first end of the capacitor. Thus, the second clock signal CLK is also received D The N well of the P transistor M3 can be D When it jumps to low level, the N-well voltage is first increased from V DD Pulled low to 0. The N-well voltage is from V DD After being pulled down to 0, the second clock signal CLK is buffered by two inverters 15 and 16. D The low-level transition will cause the voltage at the output terminal OUT at the second end of capacitor C to jump to a negative value, causing the diode of the first NMOS transistor M1 to turn on. However, since the N-well voltage has already been pulled down to 0, there is no risk of breakdown of the first PMOS transistor M2. It should be understood that the buffer is not equivalent to a delay circuit that significantly delays the signal. Its function is simply to make the voltage transition of the output terminal OUT slightly later than the N-well voltage transition of the second PMOS transistor M3.

[0059] Furthermore, the figure also shows that the reverse signal CLK is generated from the first clock signal CLK B and the second clock signal CLK D and the third clock signal CLK A A specific circuit implementation.

[0060] like Figure 5 As shown, the input terminal can receive the first clock signal CLK. The circuit shown in the figure can include a falling edge delay circuit 11. The input end of the falling edge delay circuit 11 receives the first clock signal CLK and outputs a second clock signal CLK from the output end. D The second clock signal CLK D The voltage may be directly provided to the N-well of the second PMOS transistor M3 , and may be provided to the first end of the capacitor C after being buffered by the inverters 15 and 16 .

[0061] Reverse signal CLK B It can be obtained by sending the first clock signal CLK into the inverter 12. As for the third clock signal CLK A , can be realized using a logic gate implemented as an XOR gate 14. The logic gate 14 receives the first clock signal CLK as a first input and receives the second clock signal CLK D The inverted signal (for example, via the inverter 13) is used as the second output, and the XOR result is output to obtain the third clock signal CLKA It should be understood by those skilled in the art that other logical connections may also be used to implement the third clock signal CLK A For example, an AND gate may be used to receive the inverted signal of the first clock signal as a first input, the second clock signal as a second output, and output an AND result as the third clock signal.

[0062] The falling edge delay circuit 11 can be implemented by a combination of logic gates and capacitors. Figure 6 An exemplary falling edge delay circuit 11 is shown. The falling edge delay circuit 11 may include: an inverter 111, an inverter 112, a capacitor C11, a capacitor C12, a NOR gate circuit 114, and an inverter 113. The input end of the inverter 111 receives the first clock signal CLK, and the output end of the inverter 111 is respectively connected to the first end of the capacitor C11 and the input end of the inverter 112. The second end of the capacitor C11 is grounded. The output end of the inverter 112 is respectively connected to the first end of the capacitor C12 and the first input end of the NOR gate circuit 114. The second end of the capacitor C12 is grounded. The second input end of the NOR gate circuit 114 receives the first clock signal CLK, and the output end of the NOR gate circuit 114 is connected to the input end of the inverter 113. The output end of the inverter 113 outputs the second clock signal CLK D It is understood that the implementation of the falling edge delay circuit 11 is not limited to Figure 6 The circuit shown.

[0063] The clock swing increasing circuit of the present invention can also use other logic gate connection methods to realize the control of the MOS tube and the capacitor C by each clock. Figure 7 FIG. 4 is a circuit diagram showing a clock swing increasing circuit according to an embodiment of the present invention. Figure 8 Shown Figure 7 The timing diagram of the clock swing increase circuit when it is working is shown.

[0064] like Figure 7 As shown, the input terminal obtains the first clock signal CLK. The first clock signal CLK is delayed by the falling edge delay circuit 11, and the delayed clock signal is obtained at point B. The signal is obtained at point A through the combination of the inverter 13 and the NOR gate 14 (the other input of the NOR gate 14 is the clock signal CLK) to obtain the third clock signal CLK A The third clock signal CLK obtained at point A A Used to control the on and off of the first NMOS transistor M1.

[0065] The third clock signal CLK obtained at point A A Then, the delayed clock signal obtained at point B can be fed into the AND gate to obtain the delayed clock signal at point E. This delayed signal can be regarded as the second clock signal CLKD , and sent to the N well of the second PMOS transistor M3.

[0066] The second clock signal CLK at point E D The delayed clock signal at point G can then be obtained through the buffering of two inverters 15 and 16 (actually also using the delay of the logic gate). The delayed clock signal at point G can be used to control the voltage jump across capacitor C (thereby indirectly controlling the output terminal OUT). The delayed clock signal at point G can then be fed into the NAND gate 12, thereby obtaining the clock signal at point D together with the clock signal CLK, i.e., the inverted signal CLK. B .

[0067] From this it is clear that in Figure 7 In the circuit implementation shown, at each transition moment t0, t1, t2, and t3, the order in which the states of MOS transistors M1, M2, M3, and capacitor C change slightly varies due to the order in which the logic gates are connected. MOS transistor M1 changes state before MOS transistor M3, and then capacitor C and MOS transistor M2.

[0068] The following will be combined Figure 8 right Figure 7 It should be understood that although the operation of the circuit shown is Figure 8 It is shown that point B, point E and point G have exactly the same waveform and can correspond to the second clock signal CLK D However, in fact, at each jump moment (such as t0, t1, t2 and t3), the jump of point B will be slightly earlier than that of point E, and the jump of point E will be slightly earlier than that of point G.

[0069] At time t0, the NMOS transistor M1 is continuously turned off because the gate voltage of point A remains at 0. Subsequently, the N-well voltage of the second PMOS transistor M3 jumps from 0 to V DD , the first PMOS transistor M2 becomes conductive due to the gate voltage jump to 0, and the second PMOS transistor M3 becomes conductive due to VGS=-V DD (The end of the second PMOS transistor M3 connected to the drain of the first PMOS transistor M2 can be regarded as the source) and turned on. At this time, the voltage of the output terminal OUT is V DD , the voltage at point G on the left side of capacitor C is also V DD Therefore, in phase I, there is no voltage difference between the two sides of capacitor C, NMOS transistor M1 is turned off, and PMOS transistors M2 and M3 are turned on, so that the output terminal OUT voltage remains at V DD .

[0070] At time t1, the NMOS transistor M1 turns on because the gate voltage of point A jumps to 1. At this time, the voltage of the output terminal OUT can be directly pulled down to V SS , for example, pulled down to 0V. Due to the delay of the falling edge, the N-well voltage of the second PMOS transistor M3 remains at V DD , the first PMOS transistor M2 is turned off because the gate voltage of point D jumps to 1, and the second PMOS transistor M3 is also turned off. The voltage at point G on the left side of the capacitor is still V DD , so that there is a voltage difference V on both sides of the capacitor C DD Therefore, in phase II, the NMOS transistor M1 is turned on, and the PMOS transistors M2 and M3 are turned off, so that the output terminal OUT voltage remains at V SS , for example, is 0V.

[0071] At time t2, the gate voltage of the NMOS transistor M1 at point A jumps to 0, and the gate-source connection can be regarded as a diode connection with the gate being grounded. DD jumps to 0, causing the N-well voltage of the PMOS transistor M2 to rise from V DD Switch to 0. Then, point G is switched by V DD Jump to 0 and the capacitor C has to maintain the voltage difference V DD The voltage of the output terminal OUT is pulled down to a negative value, because the negative value is greater than the threshold voltage V of the diode formed by M1. TH , so the transistor M1 is turned on in the form of a diode, thereby stabilizing the voltage of the output terminal OUT to -V TH .

[0072] At time t3, the circuit can repeat the operation of phase I. Thus, the circuit first lowers the N-well voltage of the PMOS transistor to damage the PMOS transistor M2, and then uses the capacitor to provide a reverse conduction voltage to the NMOS transistor that shorts the diode to turn on the diode and pull the voltage down to -V TH , thereby achieving a swing from V DD To -V TH clock circuit.

[0073] The output OUT of the clock swing enlargement circuit can then be used as the clock input of the charge pump. Since the charge pump requires a pair of clocks with opposite phases, a non-overlapping clock generation circuit can also be used to generate a clock based on the output OUT of the clock swing enlargement circuit. Figure 1 φ1 and φ2 are shown.

[0074] The charge pump is only a part of the on-chip high-voltage generating circuit. Therefore, the present invention can also be implemented as an on-chip high-voltage generating circuit, including the clock swing increasing circuit described above, and a charge pump that obtains the output of the clock swing increasing circuit as a clock input.

[0075] Figure 9 FIG. 1 shows a configuration example of an on-chip high-voltage generating circuit according to an embodiment of the present invention.

[0076] like Figure 9 As shown, in addition to the charge pump, the high voltage generating circuit also includes a reference voltage generating circuit (Reference), a regulator (Regulator), an oscillator (Oscillator), a voltage level converter (LevelShifter), and the clock swing increasing circuit of the present invention.

[0077] The reference voltage generation circuit usually uses a bandgap reference to provide a reference voltage V that is independent of the power supply voltage and temperature. REF .

[0078] The regulator includes, for example, a voltage divider resistor and a comparator. The voltage divider resistor includes a first resistor disposed between the output terminal of a charge pump and a feedback node, and a second resistor disposed between the feedback node and ground. The feedback node is connected to a first input terminal of the comparator for providing a voltage that is equal to the output voltage V of the charge pump. PP Proportional feedback voltage V MON The second input terminal of the comparator receives the reference voltage V REF The comparator responds to the feedback voltage V MON With reference voltage V REF For comparison, if V MON Greater than V REF (V PP is greater than the target voltage), the charge pump is turned off. MON Less than V REF (V PP The oscillator is used to provide a clock signal for the charge pump. The oscillator receives the power supply voltage V DD , generates a clock signal, the high value (amplitude) of the clock signal is up to the power supply voltage V DD .

[0079] The charge pump is the main body of the high voltage generation circuit and can be realized by a variety of circuit structures. Figure 1The Dickson charge pump shown is a commonly used type. The Dickson charge pump uses a pair of non-overlapping clock signals. In other embodiments, the charge pump can use two pairs of non-overlapping clock signals. A voltage level converter is a switch used to connect the charge pump to the load. The load can be a capacitor, a resistor, or a combination of both.

[0080] Different from the prior art which directly uses the oscillator to generate a high value up to the power supply voltage V DD The clock voltage of the charge pump is used as the input clock of the charge pump. The on-chip high-voltage generating circuit of the present invention can be connected after the oscillator and combined with the clock swing increasing circuit described in the present invention to obtain a clock signal with an increased swing, for example, a swing from -V TH to V DD clock signal.

[0081] Furthermore, the present invention can also be implemented as an electronic device including the on-chip high-voltage generation circuit described above. The electronic device can particularly be a memory or a display device. The memory can be a non-volatile memory, such as a flash memory. The memory can also be a volatile memory. The display device can be, for example, a liquid crystal display, an organic light-emitting diode display, or the like.

[0082] The clock swing amplification circuit and corresponding on-chip high-voltage generation circuit and electronic device according to the present invention have been described in detail above with reference to the accompanying drawings. The clock swing amplification circuit of the present invention first lowers the N-well voltage of the PMOS transistor to damage the PMOS transistor M2, then uses a capacitor to provide a reverse conduction voltage to the NMOS transistor that shorts the diode, causing the diode to conduct and lower the voltage to -V. TH , thereby achieving a swing from V DD To -V TH This makes it possible to realize a more efficient on-chip high-value boost circuit and electronic device.

[0083] While various embodiments of the present invention have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A clock swing increasing circuit, comprising: An input terminal for receiving a first clock signal; Output terminals; a capacitor, wherein a first end of the capacitor receives a second clock signal, and a second end of the capacitor is connected to the output terminal, the second clock signal and the first clock signal have the same rising edge, and a falling edge of the second clock signal is delayed than a falling edge of the first clock signal; a first NMOS transistor, wherein a source of the first NMOS transistor is grounded, a drain is connected to the output terminal, and a gate receives a third clock signal, wherein the third clock signal is at a low level when the first clock signal and the second clock signal are at the same level, and is at a high level when the levels are different; a second switch connected between the power terminal and the output terminal; When the first clock signal and the second clock signal are both high, the first NMOS transistor is turned off and the second switch is turned on; when the first clock signal is low and the second clock signal is high, the first NMOS transistor is turned on and the second switch is turned off; when the first clock signal and the second clock signal are both low, the second switch is turned off, and the first NMOS transistor acts as a diode with a gate-source short circuit.

2. The clock swing increasing circuit according to claim 1, wherein: The second switch is a first PMOS transistor, a source of the first PMOS transistor is connected to the power terminal, a drain is connected to the output terminal, and a gate is connected to the inverse signal of the first clock signal.

3. The clock swing increasing circuit according to claim 1 , further comprising: A second PMOS transistor has a source and a drain connected between the source of the first PMOS transistor and the power supply terminal, a gate of the second PMOS transistor is grounded, and a substrate receives the second clock signal.

4. The clock swing increasing circuit according to claim 3, wherein: The first PMOS transistor M2 and the second PMOS transistor M3 are arranged in different N-wells, and the N-well of the second PMOS transistor M3 receives the second clock signal.

5. The clock swing increasing circuit according to claim 1 , further comprising: A buffer is provided, wherein a first terminal of the buffer receives the second clock signal, and a second terminal of the buffer is connected to the first terminal of the capacitor.

6. The clock swing increasing circuit according to claim 1 , comprising: A falling edge delay circuit, wherein an input end of the falling edge delay circuit receives the first clock signal, and an output end of the falling edge delay circuit outputs the second clock signal.

7. The clock swing increasing circuit according to claim 6, comprising: a logic gate circuit, configured to generate the third clock signal based on the first clock signal and the second clock signal, and comprising: receiving the first clock signal as a first input, an inverted signal of the second clock signal as a second output, and outputting an XOR result as the third clock signal, or An inverted signal of the first clock signal is received as a first input, the second clock signal is received as a second output, and a result thereof is output as the third clock signal.

8. An on-chip high-voltage generation circuit, comprising: The clock swing increasing circuit according to any one of claims 1 to 7, wherein the clock swing increasing circuit outputs a clock signal having a low value lower than a ground voltage; as well as The charge pump circuit obtains a high-value boosted clock signal as a clock signal of the charge pump circuit.

9. An electronic device comprising the on-chip high voltage generating circuit according to claim 8.

10. The electronic device according to claim 9, wherein: The electronic device is a memory or a display device.

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