Configurable input of an amplifier

Abstract

This application relates to configurable inputs for amplifiers. In some instances, a circuit can be configured to operate based on a signal having a first voltage profile or a second voltage profile. For example, the first voltage profile can be associated with a voltage range based on a temperature of an associated memory chip, and the second voltage profile can be associated with a voltage that is not associated with the temperature of the memory chip. The circuit can include one or more transistors and switches that are activated based on the voltage profile and a particular control signal received by the switches. In some examples, the control signal can be received based on values stored to one or more non-volatile memory elements.

Description

[0001] CROSS REFERENCE

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 647,151, titled “CONFIGURABLE INPUT FOR AN AMPLIFIER” and filed on January 5, 2022 for XUE et al., assigned to the assignee of the present application, and expressly incorporated herein by reference. TECHNICAL FIELD

[0003] The technical field relates to configurable input for an amplifier. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communications devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells can be programmed to one of two supported states, often represented by a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, and the like. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain a stored logic state for a long period of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0006] A device is described. The device can include circuitry comprising: a first transistor of a first type coupled with a first node and having a gate coupled with a first signal; a second transistor of a second type coupled with the first node and having a gate coupled with the first signal; a first switch coupled with the first transistor and a second node, wherein a first control signal of the first switch activates the first switch based at least in part on the first signal having a first voltage distribution within a range of a condition; and a second switch coupled with the second transistor and the second node, wherein a second control signal of the second switch activates the second switch based at least in part on the first signal having a second voltage distribution within the range of the condition.

[0007] A method is described. The method can include receiving a first signal at a gate of a first transistor of a first type of a circuit, wherein the first transistor of the first type is coupled with a first node; receiving the first signal at a gate of a second transistor of a second type of the circuit, wherein the second transistor of the second type is coupled with the first node, wherein the first signal comprises a first voltage distribution within a range of a condition or a second voltage distribution within the range of the condition; activating a first switch coupled with the first transistor and a second node based at least in part on the first switch receiving a first control signal and the first signal having the first voltage distribution within the range of the condition; maintaining a second switch coupled with the second transistor and the second node in a deactivated state based at least in part on activating the first switch.

[0008] A device is described. The device can include an amplifier comprising a first input stage and a second input stage, wherein the first input stage comprises: a first transistor of a first type coupled with a first node and having a gate coupled with a first signal; a second transistor of a second type coupled with the first node and having a gate coupled with the first signal; a first switch coupled with the first transistor and a second node and configured to receive a first control signal; and a second switch coupled with the second transistor and the second node and configured to receive a second control signal, wherein the first input stage of the amplifier is configured to switch between activating the first transistor of the first type and activating the second transistor of the second type, wherein the first transistor of the first type is configured to be activated based at least in part on the first switch receiving the first control signal and the first signal having a first voltage distribution within a range of a condition, and wherein the second transistor of the second type is configured to be activated based at least in part on the second switch receiving the second control signal and the first signal having a second voltage distribution within the range of the condition. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system supporting configurable inputs of amplifiers is shown in accordance with examples disclosed herein.

[0010] Figure 2 An example of a memory die supporting configurable inputs of amplifiers is shown in accordance with examples disclosed herein.

[0011] Figure 3 An example of a circuit supporting configurable inputs of amplifiers is shown in accordance with examples disclosed herein.

[0012] Figure 4 An example of a temperature slope of a reference signal supporting configurable inputs of amplifiers is shown in accordance with examples disclosed herein.

[0013] Figure 5A And 5B A circuit supporting configurable inputs of amplifiers is shown in accordance with examples disclosed herein.

[0014] Figure 6 A flowchart showing one or more methods supporting configurable inputs of amplifiers is shown in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0015] Semiconductor manufacturing is subject to variations in manufacturing parameters used to apply integrated circuit designs to semiconductor wafers. Process corners represent extremes of these parameter variations, generally encompassing a range in which circuits manufactured on a wafer should function properly. Circuits running on devices manufactured at these process corners can run slower or faster than under nominal process conditions, and are expected to run within a specified temperature and voltage range.

[0016] In some examples, a first process corner (e.g., fast-slow (FS) corner) can refer to certain transistors (e.g., NMOS) having characteristics (e.g., threshold voltage, transconductance) for fast operation, while other transistors (e.g., PMOS) have characteristics for slow operation. In other corners, the transistor types can both be fast (e.g., fast-fast (FF)) or slow (e.g., slow-slow (SS)), or the speed difference can be reversed (e.g., slow-fast (SF)). Generally, using a fixed reference voltage for amplifiers and comparators across all process corners, and within a specified temperature and supply voltage range, can result in degraded performance or operational failure. For example, using a fixed reference voltage when the threshold voltage (e.g., Vt) of a transistor is high can cause the transistor to operate in the sub-threshold region. As a result, the circuit can not function properly when operating in such conditions.

[0017] In some cases, a circuit can use a fixed reference voltage under some process conditions and a variable reference voltage under other process conditions. For example, the circuit can receive a voltage that is based on a temperature of an associated device under some process conditions. That is, the voltage can be higher when the temperature of the memory chip is relatively low and vice versa. However, when operating under certain conditions that use a variable reference voltage, the drain-source voltage (e.g., Vds) of the transistor can be extremely low. Thus, the circuit can not function properly when operating under such conditions. Accordingly, in some cases, even though a fixed reference voltage is used for certain process corners and a variable reference voltage is used for other process corners, satisfactory operation can not be provided over a specified temperature and voltage range.

[0018] In some examples, the manufacturing process can include different types of transistors. For example, different types of transistors can have different characteristics (e.g., gate oxide thickness) for different circuits or having different voltages. As described herein, a circuit can include different types of transistors that can be selected under different process corners to mitigate or eliminate problems caused by operation in an extremely low Vds or sub-threshold region. For example, a circuit can include a first type of transistor coupled with a first switch and a second type of transistor coupled with a second switch. The types and characteristics of the transistors can be selected such that the first switch and the first transistor can be activated when the circuit receives a voltage that is based on a temperature of an associated memory chip. Further, the second switch and the second transistor can be activated when the circuit receives a voltage that is not based on a temperature of an associated memory chip.

[0019] Accordingly, the Vds of the first transistor can be high enough to allow the circuit to function properly when receiving a temperature-dependent voltage. Further, when the second transistor receives a non-temperature-dependent voltage, the voltage it receives can be high enough above its Vt and can not operate in a sub-threshold region. Thus, by including different types of transistors under different process corners, the circuit can mitigate or eliminate problems caused by an extremely low Vds or a gate voltage that is close to or below Vt that would otherwise cause the transistor to operate in a sub-threshold region.

[0020] Features of the present disclosure are first described in the context of a system and die described with reference to Figure 1 and 2 Features of the present disclosure are described in the context of a circuit and temperature gradient of a reference signal described with reference to Figures 3-5B These and other features of the present disclosure are further illustrated by a flowchart described with reference to Figure 6 involving a configurable input of an amplifier described with reference to a flowchart.

[0021] Figure 1An example of a system 100 that supports configurable inputs of amplifiers in accordance with examples disclosed herein is shown. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. The system 100 can include one or more memory devices 110, although aspects of the one or more memory devices 110 can be described in the context of a single memory device (e.g., the memory device 110).

[0022] The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a notebook computer, a tablet computer, a smart phone, a mobile phone, a wearable device, an Internet-connected device, a vehicle controller, and so forth. The memory device 110 can be a component of a system that can be used to store data for one or more other components of the system 100.

[0023] At least portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor or other circuitry within a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a notebook computer, a tablet computer, a smart phone, a mobile phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host or host device 105.

[0024] The memory device 110 can be a standalone device or component that can be used to provide physical memory addresses / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configured to function with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 can be used to support one or more of a modulation scheme that modulates signals, various pin configurations for communicating signals, various form factors for physical packaging of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

[0025] Memory device 110 can be used to store data for components of host device 105. In some examples, memory device 110 can act as a secondary or dependent device of host device 105 (e.g., by external memory controller 120 responding to and executing commands provided by host device 105). Such commands can include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0026] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. Components of host device 105 can be coupled with each other using bus 135.

[0027] Processor 125 can be used to provide control or other functionality to at least portions of system 100 or at least portions of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by processor 125 or can be part of the processor.

[0028] BIOS component 130 can be a software component that includes a BIOS operating as firmware that can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0029] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) where each memory cell can be used to store at least one data bit. A memory device 110 including two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0030] Device memory controller 155 can include circuitry, logic, or components that can be used to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations and can be used to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be used to communicate with one or more of external memory controller 120, the one or more memory dies 160, or processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in conjunction with local memory controllers 165 of memory dies 160.

[0031] The local memory controller 165 (e.g., local to the memory die 160) can include circuitry, logic, or components that can be used to control operations of the memory die 160. In some examples, the local memory controller 165 can be used to communicate (e.g., receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155, and the local memory controller 165 or the external memory controller 120 can perform various functions described herein. As such, the local memory controller 165 can be used to communicate with the device memory controller 155, other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers that can be used to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0032] The external memory controller 120 can be used to enable communication of one or more of information, data, or commands between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can translate or interpret communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105 or functions described herein can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software or some combination thereof implemented by the processor 125 or other components of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or functions described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0033] The components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be used to support communication between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. A signal path can be an example of an electrically conductive path that can be used to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be used to function as part of a channel.

[0034] The channels 115 (and associated signal paths and terminals) can be dedicated for use in communicating one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be communicated over the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0035] In some examples, the memory device 110 can include circuitry configured to function as a comparator or an amplifier. The circuitry can include one or more transistors and one or more switches, and can be configured to operate based on receiving a voltage having a first voltage distribution or a second voltage distribution. In some instances, the first voltage distribution can be associated with a temperature of the memory device 110, while the second voltage distribution can be independent (e.g., relatively independent) of the temperature of the memory device.

[0036] The circuit can include at least two transistors configured in parallel and each coupled with at least one switch. The switches can each be coupled with a respective control signal configured to be activated based on a voltage profile being associated with (or not associated with) a temperature of the memory device 110. For example, a first switch can receive a first control signal and a first transistor, when selected, can receive a voltage related to a temperature of the memory device 110. In other examples, a second switch can receive a second control signal and a second transistor, when selected, can receive a voltage not related to a temperature of the memory device 110. In some examples, the voltage related to temperature can vary by more than a threshold amount over an operating temperature range, where the threshold amount can be 50mV, lOOmV, or 200mV. In some examples, the voltage not related to a temperature of the memory device 110 can be constant, fixed, or can be substantially invariant (e.g., over an operating temperature range can have a variation less than a threshold amount, where the threshold amount can be 2mV, 5mV, lOmV, 25mV, or 50mV).

[0037] When operating as a comparator, the circuit can compare an input voltage to a temperature-related or non-temperature-related voltage received by a respective transistor. Additionally or alternatively, when operating as an amplifier, the circuit can receive an input voltage and output an equal, divided (e.g., less than the input voltage), or amplified (e.g., greater than the input voltage) voltage.

[0038] In either example, the Vds of the transistors included in the circuit can be high enough to allow the circuit to function properly when receiving a temperature-related voltage. Further, when the transistors of the circuit receive a non-temperature-related voltage, the voltage can be high enough above the Vt of the transistors, so the transistors can not operate in the sub-threshold region. By including different types of transistors under different process corners of the circuit, the circuit can mitigate or eliminate issues caused by very low Vds or operation in the sub-threshold region.

[0039] Figure 2 An example of a memory die 200 supporting configurable inputs of an amplifier in accordance with examples disclosed herein is shown. The memory die 200 can be the memory die 200 described with reference to FIG. 1. The memory die 200 includes a first transistor 202 and a second transistor 204. The first transistor 202 and the second transistor 204 can be configured in parallel. The first transistor 202 and the second transistor 204 can each be coupled with a respective switch 206, 208. The switches 206, 208 can each be coupled with a respective control signal 210, 212. The control signals 210, 212 can be configured to be activated based on a voltage profile being associated with (or not associated with) a temperature of the memory device 110. For example, the first switch 206 can receive a first control signal 210 and the first transistor 202, when selected, can receive a voltage related to a temperature of the memory device 110. In other examples, the second switch 208 can receive a second control signal 212 and the second transistor 204, when selected, can receive a voltage not related to a temperature of the memory device 110. In some examples, the voltage related to temperature can vary by more than a threshold amount over an operating temperature range, where the threshold amount can be 50mV, lOOmV, or 200mV. In some examples, the voltage not related to a temperature of the memory device 110 can be constant, fixed, or can be substantially invariant (e.g., over an operating temperature range can have a variation less than a threshold amount, where the threshold amount can be 2mV, 5mV, lOmV, 25mV, or 50mV). Figure 1An example of a memory die 160 is depicted. In some examples, the memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 can include one or more memory cells 205 that can each be programmable to store a different logical state (e.g., programmed to one of a set of two or more possible states). For example, a memory cell 205 can be used to store one bit of information (e.g., a logical 0 or a logical 1) at a time. In some examples, a memory cell 205 (e.g., a multi-level memory cell) can be used to store more than one bit of information at a time (e.g., logical 00, logical 01, logical 10, logical 11). In some examples, the memory cells 205 can be arranged in an array, such as described with reference to FIG. 1. Figure 1 A memory array 170 is depicted.

[0040] A memory cell 205 can store a charge representing a programmable state in a capacitor. DRAM architectures can include a capacitor that includes a dielectric material for storing a charge representing a programmable state. Other storage devices and components are possible in other memory architectures. For example, a non-linear dielectric material can be employed. A memory cell 205 can include a logical storage component, such as a capacitor 230, and a switching component 235. The capacitor 230 can be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor 230 can be coupled with a voltage source 240, which can be a cell plate reference voltage, such as Vpl, or can be ground, such as Vss.

[0041] A memory die 200 can include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215) arranged in a pattern, such as a grid-like pattern. An access line can be an electrically conductive line coupled with a memory cell 205 and can be used to perform an access operation on the memory cell 205. In some examples, a word line 210 can be referred to as a row line. In some examples, a digit line 215 can be referred to as a column line or a bit line. References to an access line, a row line, a column line, a word line, a digit line, or a bit line, or the like, are interchangeable without affecting understanding or operation. A memory cell 205 can be positioned at an intersection of a word line 210 and a digit line 215.

[0042] An operation, such as a read and a write, can be performed on a memory cell 205 by activating or selecting an access line (e.g., one or more of a word line 210 or a digit line 215). By biasing a word line 210 and a digit line 215 (e.g., applying a voltage to a word line 210 or a digit line 215), a single memory cell 205 located at their intersection can be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as an address of a memory cell 205.

[0043] Accessing memory cells 205 can be controlled by row decoder 220 or column decoder 225. For example, row decoder 220 can receive a row address from local memory controller 260 and activate a word line 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and activate a digit line 215 based on the received column address.

[0044] Selecting or deselecting a memory cell 205 can be accomplished by activating or deactivating a switch component 235 using word line 210. Capacitor 230 can be coupled with digit line 215 using switch component 235. For example, capacitor 230 can be isolated from digit line 215 when switch component 235 is deactivated, and capacitor 230 can be coupled with digit line 215 when switch component 235 is activated.

[0045] Sensing component 245 can be used to detect a state (e.g., a charge) stored on capacitor 230 of memory cell 205 and determine a logic state of memory cell 205 based on the stored state. Sensing component 245 can include one or more sense amplifiers to amplify or otherwise convert a signal generated by accessing memory cell 205. Sensing component 245 can compare the detected signal from memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 245 (e.g., to input / output 255) and can be indicated to another component of a memory device including memory die 200.

[0046] Local memory controller 260 can control access of memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). Local memory controller 260 can be a reference Figure 1An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be used to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate a target word line 210 and a target digit line 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein can vary and can be different for the various operations discussed in operating the memory die 200.

[0047] The local memory controller 260 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations can include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations can be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 can be used to perform other access operations or other operations related to operation of the memory die 200 (not directly related to accessing the memory cells 205) not listed here.

[0048] In some examples, the memory die 200 can include a circuit configured to function as a comparator or an amplifier. The circuit can include one or more transistors and one or more switches, and can be configured to operate based on receiving a voltage having a first voltage profile or a second voltage profile. In some examples, the first voltage profile can be related to a temperature of the memory die 200, while the second voltage profile can be substantially independent of the temperature of the memory device.

[0049] The circuit can include at least two transistors configured in parallel and each coupled with at least one switch. The switches can each be coupled with a respective control signal configured to be activated based on a voltage profile being related to a temperature of the memory die 200 or being unrelated to the temperature of the memory die 200. For example, a first switch can receive a first control signal and a first transistor, when selected, can receive a voltage based on a temperature of the memory die 200. In other examples, a second switch can receive a second control signal and a second transistor, when selected, can receive a voltage that is not associated with a temperature of the memory die 200. In some examples, the voltage that is not associated with a temperature of the memory die 200 can be constant, fixed, or can not vary based on a temperature of the memory device (e.g., vary by more than a threshold amount).

[0050] When operating as a comparator, the circuit can compare an input voltage to a temperature-related or non-temperature-related voltage received by a respective transistor. Additionally or alternatively, when operating as an amplifier, the circuit can receive an input voltage and output a voltage that is less than, equal to, or greater than the input voltage. The selection of which transistor to activate for the comparator can be based on one or more of the activated switches.

[0051] In either example, the Vds of the transistors included in the circuit can be high enough to allow the circuit to function properly when receiving a temperature-related voltage. Further, when the transistors of the circuit receive a non-temperature-related voltage, the voltage can be high enough above the Vt of the transistors, so the transistors can not operate in the sub-threshold region. By including different types of transistors at different process corners of the circuit, the circuit can mitigate or eliminate issues caused by very low Vds or sub-threshold region operation.

[0052] Figure 3 An example of a circuit 300 that supports configurable inputs for an amplifier is shown in accordance with examples disclosed herein. The circuit 300 can include various transistors that are activated based on a voltage profile of a control signal and a signal (e.g., a first signal, a reference signal) received by the circuit 300. The circuit 300 can include a first input 305 configured to provide a first signal having a first voltage profile (e.g., a variable reference signal) associated with a temperature gradient or a second voltage profile (e.g., a fixed reference signal) associated with a non-temperature-related gradient to one or more transistors. The first signal can be applied to a gate of the one or more transistors, and a particular transistor can be activated (e.g., turned on) or deactivated (e.g., turned off) based on a signal (e.g., a control signal) received by one or more switches. Thus, by activating a transistor configured to receive the first signal associated with the first voltage profile or the second voltage profile, the circuit 300 can effectively operate without any transistors operating in a sub-threshold region or with very low Vds (e.g., drain-source voltage).

[0053] Circuit 300 can include a first transistor 310 and a second transistor 315 coupled with a first input 305 (e.g., a positive input 305) of circuit 300. In some examples, first transistor 310 and second transistor 315 can be n-channel (e.g., NMOS) transistors, and can be configured in parallel. However, in other examples, first transistor 310 and second transistor 315 can be different types of transistors. Further, first transistor 310 and second transistor 315 can each be associated with a different threshold voltage (e.g., different Vt). For example, first transistor 310 can have a thicker (e.g., different from) gate oxide than second transistor 315, and thus can be associated with a higher Vt than second transistor 315. The thickness of first transistor 310 and second transistor 315 can be based on the manufacturing process of the respective transistors. That is, different manufacturing processes can produce different transistor types with different characteristics (e.g., different oxide thicknesses). In some examples, the respective transistors can be activated (e.g., enabled in circuit 300) based on a voltage of a first signal and a control signal applied to circuit 300.

[0054] Circuit 300 can also include a third transistor 320 and a fourth transistor 325 coupled with a second input 330 (e.g., a negative input 330) of circuit 300. In some examples, third transistor 320 and fourth transistor 325 can be n-channel (e.g., NMOS) transistors, and can be configured in parallel. However, in other examples, third transistor 320 and fourth transistor 325 can be different types of transistors. Further, third transistor 320 and fourth transistor 325 can each be associated with a different threshold voltage (e.g., different Vt). For example, third transistor 320 can have a thicker (e.g., different from) gate oxide than fourth transistor 325, and thus can be associated with a higher Vt than fourth transistor 325. Further, first transistor 310 and third transistor 320 can have the same or similar gate oxide thickness (e.g., the same or similar Vt), and second transistor 315 and fourth transistor 325 can have the same or similar gate oxide thickness. However, as described above, the gate oxide of each of first transistor 310, second transistor 315, third transistor 320, and fourth transistor 325 can be based on a particular manufacturing process, which can cause the respective transistors to be activated (e.g., turned on) based on a voltage of a first signal and a control signal applied to circuit 300.

[0055] First input 305 can be configured to provide a first signal to first transistor 310 and third transistor 320, and second input 330 can be configured to provide a second signal to second transistor 315 and fourth transistor 325. For example, as described above, first transistor 310 and third transistor 320 can be associated with a first Vt, and second transistor 315 and fourth transistor 325 can be associated with a second Vt. In some examples, first input 305 can be configured to provide a first signal having a voltage that is greater than the first Vt, and second input 330 can be configured to provide a second signal having a voltage that is less than the second Vt. In this way, first transistor 310 and third transistor 320 can be activated (e.g., turned on) based on the first signal, and second transistor 315 and fourth transistor 325 can be activated (e.g., turned on) based on the second signal. Figure 4As shown in the middle, the first signal can have a first voltage profile 405 or a second voltage profile 410. In some examples, the first voltage profile 405 can be associated with a temperature gradient, and the second voltage profile 410 can be associated with a non-temperature gradient. The first voltage profile 405 can be associated with a negative gradient, such that at lower temperature values (e.g., lower temperature values of an associated memory chip), the voltage of the first signal having the first voltage profile 405 can be relatively higher, and at higher temperature values, the voltage of the first signal can be relatively lower. Additionally or alternatively, the second voltage profile 410 can not be associated with a temperature gradient. That is, the voltage of the first signal having the second voltage profile 410 can be constant, fixed, or can not vary substantially based on the temperature of the memory device (e.g., can have less than a threshold amount of variation over an operating temperature range, where the threshold amount can be 2mV, 5mV, lOmV, 25mV, or 50mV). In some instances, the voltage of the first signal having the second voltage profile 410 can vary between Tl and Tn (e.g., the second voltage profile 410 can be slightly convex or slightly concave), but the variation from end to end can be relatively low. Thus, although the second voltage profile 410 is shown as substantially constant in the middle, the second voltage profile 410 can be any shape or have any voltage value that varies relatively low over a temperature range (e.g., compared to the first voltage profile 405). Figure 4 Thus, although the second voltage profile 410 is shown as substantially constant in the middle, the second voltage profile 410 can be any shape or have any voltage value that varies relatively low over a temperature range (e.g., compared to the first voltage profile 405).

[0056] Circuit 300 can include one or more switches coupled with the first transistor 310, the second transistor 315, the third transistor 320, and the fourth transistor 325. For example, circuit 300 can include a first switch 335 coupled with the first control signal 340 and the first transistor 310, and a second switch 345 coupled with the second control signal 350 and the second transistor 315. Additionally or alternatively, circuit 300 can include a third switch 355 coupled with the first control signal 340 and the third transistor 320, and a fourth switch 360 coupled with the second control signal 350 and the fourth transistor 325. In some examples, the first control signal 340 can be associated with the first voltage profile 405, and the second control signal 350 can be associated with the second voltage profile 410. That is, when circuit 300 is operating in a temperature gradient mode, the first control signal 340 can be asserted to activate the first switch 335, the third switch 355, or both, and when circuit 300 is operating in a non-temperature gradient mode, the second control signal 350 can be asserted to activate the second switch 345, the fourth switch 360, or both.

[0057] In some examples, the circuit 300 can include or can be coupled with one or more non-volatile read-only memory units (e.g., a set of units). The one or more non-volatile read-only memory units can be or can include fuses or anti-fuses configured to store data indicating whether to activate the first control signal 340 or the second control signal 350. For example, the one or more non-volatile read-only memory units can store a first value or a second value. If the one or more non-volatile read-only memory units store the first value, the first control signal 340 can be asserted (e.g., can be high or VDD) and the first switch 335 and the third switch 355 can be activated, while the second control signal 350 can be de-asserted (e.g., can be low or VSS) and thus the second switch 345 and the fourth switch 360 can not be activated.

[0058] In other examples, if the one or more non-volatile read-only memory units store the second value, the second control signal 350 can be asserted and the second switch 345 and the fourth switch 360 can be activated, while the first control signal 340 is de-asserted and thus the first switch 335 and the third switch 355 can not be activated. In some examples, the one or more non-volatile read-only memory units can store any value, and thus whether the stored value activates or de-activates the respective control signal can be a matter of design choice.

[0059] The circuit 300 can also include a fifth transistor 365 and a sixth transistor 370 coupled with a voltage source 375 (e.g., VDD). In some examples, the fifth transistor 365 and the sixth transistor 370 can be p-channel (e.g., PMOS) transistors. However, in other examples, the fifth transistor 365 and the sixth transistor 370 can be different types of transistors. Additionally or alternatively, the fifth transistor 365 and the sixth transistor 370 can be or can be included in a current mirror configured to provide current from the voltage source 375 to one or more nodes of the circuit 300.

[0060] In some examples, the circuit 300 can include one or more other nodes. For example, the circuit 300 can include a first node 380 coupled with the first transistor 310 and the second transistor 315. In some examples, the first node 380 can be coupled with a source of the first transistor 310 and a source of the second transistor 315. The circuit 300 can also include a second node 385 coupled with the first switch 335, the second switch 345, and the fifth transistor 365. In some examples, the second node 385 can be coupled with a drain of the fifth transistor 365.

[0061] Additionally or alternatively, the circuit 300 can include a third node 390 coupled with the third transistor 320 and the fourth transistor 325. The third node 390 can be the same node as the first node 380. In some examples, the third node 390 can be coupled with the source of the third transistor 320 and the source of the fourth transistor 325, and can be the same node as the first node 380. The circuit 300 can also include a fourth node 395 coupled with the third switch 355, the fourth switch 360, and the sixth transistor 370. In some examples, the fourth node 395 can be coupled with the drain of the sixth transistor 370.

[0062] As described herein, during fabrication of the circuit 300, some corners (e.g., some process corners) can benefit from using a first signal (e.g., a reference signal) having a first voltage distribution 405, while other corners can benefit from using a reference signal having a second voltage distribution 410. That is, the voltages of these two reference signals (e.g., the reference signals having the first voltage distribution 405 and the second voltage distribution 410) can be generated using a bandgap voltage, but the first voltage distribution 405 can be based on temperature variations of the memory device, while the second voltage distribution 410 can not be based on (or the amount of variation can be relatively low) temperature variations of the memory device.

[0063] For example, the first transistor 310 and the third transistor 320 can have a higher Vt, and can benefit from using a reference signal having the first voltage distribution 405 to prevent the respective transistors from operating in a sub-threshold region. Further, the second transistor 315 and the fourth transistor 325 can have a lower Vt, and can benefit from using a reference signal having the second voltage distribution 410 to prevent the respective transistors from having a too small Vds (e.g., drain-source voltage). By preventing the respective transistors from operating in a sub-threshold region or having a very low Vds, the circuit 300 can effectively operate without experiencing issues that would otherwise arise due to variations in fabrication parameters.

[0064] By way of example, the circuit 300 can operate in a temperature gradient mode (e.g., using a reference signal having the first voltage distribution 405). The circuit 300 can operate in the temperature gradient mode based on the one or more non-volatile read-only memory cells storing a first value. Accordingly, the first control signal 340 can be asserted (e.g., driven high), which can activate the first switch 335. Further, the first input 305 (or the second input 330) can provide the first signal having a voltage based on a temperature of an associated memory chip to the gate of the first transistor 310 (or the gate of the second transistor 315). For example, as described above, the first input 305 (or the second input 330) can be coupled with a temperature sensor of the memory chip. The temperature sensor can provide the first signal having a voltage based on a temperature of the memory chip to the gate of the first transistor 310 (or the gate of the second transistor 315). Figure 4As shown in FIG. 4, the value of the voltage of the reference signal having the first voltage profile 405 can be between a first voltage 415 (e.g., at T1) and a second voltage 420 (e.g., at Tn). For exemplary purposes, the first voltage 415 can be relatively high (e.g., at or about 1.0 V) at -40 C (e.g., at T1), and the second voltage 420 can be relatively low (e.g., below 1.0 V) at 130 C (e.g., at Tn).

[0065] As described herein, the Vt of the first transistor 310 and the third transistor 320 can be lower than the first voltage at -40 C and 130 C. Thus, applying a first signal having a voltage that varies beyond a threshold (e.g., 50 mV, 100 mV, 150 mV, 200 mV) to the first transistor 310 or the third transistor 320 can activate the respective transistor, and thus prevent the transistor from operating in the sub-threshold region. In other examples, if the circuit 300 only includes the first transistor 310 and the third transistor 320 (e.g., if the circuit 300 does not include the second transistor 315 and the fourth transistor 325 for the non-temperature gradient mode), then the first transistor 310 and the third transistor 320 can operate in the sub-threshold region when in the non-temperature gradient mode.

[0066] Additionally or alternatively, the circuit 300 can operate in the non-temperature gradient mode (e.g., using a reference signal having the second voltage profile 410). The circuit 300 can operate in the non-temperature gradient mode based on the one or more non-volatile read-only memory cells storing a second value (e.g., a value different from the first value). Thus, the second control signal 350 can be asserted (e.g., driven high), which can activate the second switch 345 (and the fourth switch 360). Further, the first input 305 (or the second input 330) can provide the first signal having a voltage that is not based on the temperature of the associated memory chip to the gate of the second transistor 315 (or the gate of the fourth transistor 325). For example, as shown in FIG. 4, the first input 305 (or the second input 330) can provide the first signal having a voltage that is not based on the temperature of the associated memory chip to the gate of the second transistor 315 (or the gate of the fourth transistor 325) at T1 and Tn. Figure 4 As shown in FIG. 4, the value of the voltage of the reference signal having the second voltage profile 410 can be at or near a third voltage 425 (e.g., between T1 and Tn). For exemplary purposes, the third voltage 425 can be about 0.7 V between -40 C and 130 C.

[0067] As described herein, the Vt of the second transistor 315 and the fourth transistor 325 can be at or about 0.5 V. Thus, if a first signal (e.g., a temperature dependent signal) is applied to the first input 305, the lower Vt of the second transistor 315 will result in a relatively high (e.g., about 0.5 V) voltage at the first node 380, which will reduce the Vds of the second transistor 315 to a value that can affect the performance of the circuit 300. However, if a second signal (e.g., a non-temperature dependent signal) is applied to the first input 305, the lower Vt of the second transistor will maintain the second node 385 at or near the difference between the two voltages (e.g., at or about 0.2 V). In this case, the voltage at the second node 385 (or the fourth node 395) can be at or about 0.7 V, and thus the Vds (e.g., drain-source voltage) of the second transistor 315 and the fourth transistor 325 can be large enough such that the circuit 300 operates properly in the non-temperature dependent gradient mode.

[0068] Figure 5A An example of a circuit 500-a that supports configurable inputs of an amplifier in accordance with examples disclosed herein is shown. The circuit 500-a can include an amplifier 505, which can include various transistors and switches coupled with inputs and an output 520, as described with reference to Figure 3 the aspects of the circuit 300 described. For example, the circuit 500-a can include a first input 510 and a second input 515 (e.g., a negative input), which can be examples of the Figure 3 the first input 305 and the second input 330 described. Further, the amplifier 505 can include various transistors and switches coupled with inputs and an output 520, as described with reference to Figure 3 the aspects of the circuit 300 described. Using the input stage (e.g., the first input stage or the second input stage) of the circuit 300 as the amplifier 505 can allow the circuit 300 to operate within performance limits across a range of temperatures, and thus can provide the required output drive for the amplifier 505.

[0069] As described with reference to Figure 3As described, the circuit 300 can include various transistors that are activated based on a control signal and a voltage profile of a signal received by the circuit 300 (e.g., a first signal, a reference signal). The circuit 300 can be an example of or included within an amplifier 505, and can include a first input 510 configured to provide a first signal having a first voltage profile associated with a temperature gradient (e.g., a variable reference signal) or a second voltage profile associated with a non-temperature related gradient (e.g., a fixed reference signal) to one or more transistors. The first signal can be applied to a gate of the one or more transistors, and a particular transistor can be activated (e.g., enabled) or deactivated (e.g., disabled) based on one or more control signals received by one or more switches. Thus, by activating a transistor configured to receive the first signal associated with the first voltage profile or the second voltage profile, the amplifier 505 can be effectively operated without any transistors operating in a sub-threshold region or with very low Vds (e.g., drain-source voltage).

[0070] In some examples, the first transistor 310, the second transistor 315, the first switch 335, and the second switch 345 can be associated with the first input 510 of the amplifier 505. Additionally or alternatively, the third transistor 320, the fourth transistor 325, the third switch 355, and the fourth switch 360 can be associated with the second input 515 of the amplifier 505. For example, the amplifier 505 can be configured to receive an input voltage, and based on receiving the input voltage, can output a voltage greater than the input voltage (e.g., output an output voltage via the output 520). The voltage can be output from the amplifier based on activating the first switch, the second switch, the third switch, or the fourth switch.

[0071] For example, the amplifier can receive an input voltage at the first input 510. In some examples, the first switch 335 or the second switch 345 can be activated based on receiving a respective control signal. Further, the first signal can be received at a gate of the first transistor 310 and the second transistor 315. The first signal can be provided by the first input 305. Based on the first switch 335 or the second switch 345 being activated, a voltage at the fourth node 395 can be output from the amplifier 505 (e.g., via the output 520).

[0072] When the circuit 300 operates as an amplifier 505, an output voltage (e.g., at the output 520) can track an input voltage (e.g., at the first input 510) by using feedback from the output 520 to the second input 515 (e.g., via the feedback line 525). Thus, if the voltage at the output 520 is higher than the voltage at the first input 510, the feedback can cause the output voltage to decrease. Additionally or alternatively, if the output (e.g., the voltage at the output 520) is lower than the input, the feedback can cause the output voltage to increase. Using the input stage (e.g., the first input stage or the second input stage) of the circuit 300 as an amplifier 505 for voltage generation or regulation (e.g., a charge pump, a reference voltage generator, etc.), the circuit 300 can operate within performance limits over a full temperature range, and thus can provide the required output drive for the amplifier.

[0073] Figure 5B An example of a circuit 500-b that supports configurable inputs for an amplifier in accordance with examples disclosed herein is shown. The circuit 500-b can include a comparator 530, which can include a reference Figure 3 described aspects of the circuit 300. For example, the circuit 500-b can include a first input 535 and a second input 540, which can be examples of the reference Figure 3 described first input 305 and second input 330. Further, the comparator 530 can include various transistors and switches coupled with the inputs and an output 545, as described with reference to Figure 3 described. Using the circuit 300 as the comparator 530 in a voltage generation or regulation circuit (e.g., a charge pump, a reference voltage generator, etc.), the circuit 300 can operate within performance limits over a full temperature range, and thus can provide the required switching performance for the comparator 530.

[0074] As described herein with reference to Figure 3 described aspects of the circuit 300 can be used as the comparator 530. For example, the circuit 300 can output a voltage (e.g., at the node 395) that can swing based on whether the positive input 305 or the negative input 330 is higher. That is, if the positive input 305 is higher than the negative input 330, the circuit 300 can output a relatively higher voltage at the fourth node 395. If the negative input 330 is higher than the positive input 305, the circuit 300 can output a relatively lower voltage at the fourth node 395.

[0075] For example, the first signal can be received at the gates of the first transistor 310 and the second transistor 315. The first signal can be received at the first input 535 (positive input). The comparator 530 can then output a signal based on a difference between the second signal received at the second input 540 (negative input) (e.g., output an output signal via the output 545). Using the circuit 300 as the comparator 530 in a circuit for voltage generation or regulation (e.g., a charge pump, a reference voltage generator, etc.), the circuit 300 can operate within performance limits over a range of temperatures, and thus can provide the required switching performance for the comparator.

[0076] Figure 6 A flow diagram illustrating a method 600 of supporting configurable inputs of amplifiers in accordance with examples as disclosed herein is shown. The operations of method 600 can be implemented by a circuit or its components as described herein. For example, the operations of method 600 can be performed by the circuit described with reference to Figure 1 In some examples, a circuit can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the circuit can perform aspects of the described functions using special-purpose hardware.

[0077] At 605, the method can include receiving a first signal at a gate of a first transistor of a first type of a circuit, wherein the first transistor of the first type is coupled with a first node. The operations of 605 can be performed in accordance with examples as disclosed herein.

[0078] At 610, the method can include receiving the first signal at a gate of a second transistor of a second type of the circuit, wherein the second transistor of the second type is coupled with the first node, wherein the first signal includes a first voltage distribution within a range of a condition or a second voltage distribution within the range of the condition. The operations of 610 can be performed in accordance with examples as disclosed herein.

[0079] At 615, the method can include activating a first switch coupled with the first transistor and the second node based at least in part on the first control signal being received by the first switch and the first signal having the first voltage distribution within the range of the condition. The operations of 615 can be performed in accordance with examples as disclosed herein.

[0080] At 620, the method can include maintaining a second switch coupled with the second transistor and the second node in a deactivated state based at least in part on the first switch being activated. The operations of 620 can be performed in accordance with examples as disclosed herein.

[0081] In some examples, the apparatuses described herein can perform one or more methods, such as method 600. The apparatuses can include features, circuitry, logic, means, or instructions for (e.g., a non-transitory computer-readable medium storing instructions that are executable by a processor) receiving a first signal at a gate of a first transistor of a first type of circuitry, where the first transistor of the first type is coupled with a first node; receiving the first signal at a gate of a second transistor of a second type of circuitry, where the second transistor of the second type is coupled with the first node, where the first signal includes a first voltage distribution within a range of a condition or a second voltage distribution within the range of the condition; activating a first switch coupled with the first transistor and the second node based at least in part on the first control signal being received by the first switch and the first signal having the first voltage distribution within the range of the condition; and maintaining a second switch coupled with the second transistor and the second node in a deactivated state based at least in part on the first switch being activated.

[0082] Some examples of the method 600 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for reading data from a non-volatile memory element coupled with the circuitry, where based at least in part on a first value being read from the non-volatile memory element, the first control signal is configurable to activate the first switch and the second control signal is configurable to deactivate the second switch, and based at least in part on a second value being read from the non-volatile memory element, the first control signal is configurable to deactivate the first switch and the second control signal is configurable to activate the second switch.

[0083] In some examples of the method 600 and apparatus described herein, the first transistor and the method, apparatus, and non-transitory computer-readable medium can include further operations, features, circuitry, logic, means, or instructions for receiving an input voltage at a third node, and outputting an output voltage from an amplifier that can be greater than the input voltage based at least in part on the first switch being activated or the second switch being activated.

[0084] Some examples of the method 600 and apparatus described herein can further include operations, features, circuitry, logic, means, or instructions for receiving an input voltage at a third node, comparing the input voltage to a voltage of the first signal, and outputting an output voltage from the circuitry based at least in part on a difference between the input voltage and the voltage of the first signal.

[0085] In some examples of the method 600 and apparatus described herein, the first voltage distribution of the first signal includes a first temperature gradient, and the second voltage distribution of the first signal includes a second temperature gradient that can be different than the first temperature gradient.

[0086] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods can be combined.

[0087] An apparatus is described. The apparatus can include circuitry including a first transistor of a first type coupled with a first node and having a gate coupled with a first signal, a second transistor of a second type coupled with the first node and having a gate coupled with the first signal, a first switch coupled with the first transistor and a second node, wherein a first control signal of the first switch activates the first switch based at least in part on the first signal having a first voltage distribution within a range of a condition, and a second switch coupled with the second transistor and the second node, wherein a second control signal of the second switch activates the second switch based at least in part on the first signal having a second voltage distribution within the range of the condition.

[0088] In some examples, the apparatus can include a non-volatile memory element coupled with the circuitry, wherein based at least in part on the non-volatile memory element storing a first value, the first control signal is configurable to activate the first switch and the second control signal is configurable to deactivate the second switch, and based at least in part on the non-volatile memory element storing a second value, the first control signal is configurable to deactivate the first switch and the second control signal is configurable to activate the second switch.

[0089] In some examples of the apparatus, the circuitry further includes a third transistor of the first type coupled with a third node and having a gate coupled with a second signal, a fourth transistor of the second type coupled with the third node and having a gate coupled with the second signal, a third switch coupled with the third transistor and a fourth node, wherein the first control signal of the first switch activates the third switch based at least in part on the first signal having the first voltage distribution within the range of the condition, and a fourth switch coupled with the fourth transistor and the fourth node, wherein the second control signal of the fourth switch activates the fourth switch based at least in part on the first signal having the second voltage distribution within the range of the condition.

[0090] In some examples of the apparatus, the first node and the third node include a same node.

[0091] In some examples of the apparatus, an output of the circuitry can be at the fourth node, and the output can be based at least in part on a difference between the first signal and the second signal.

[0092] In some examples of the apparatus, the first transistor of the first type, the second transistor of the second type, the first switch, and the second switch can be associated with a first input stage of an amplifier, and the third transistor of the first type, the fourth transistor of the second type, the third switch, and the fourth switch can be associated with a second input stage of the amplifier.

[0093] In some examples, the apparatus can include a fifth transistor of a third type coupled with a voltage source and the second node, and a sixth transistor of the third type coupled with the voltage source and the fourth node, where the fifth transistor and the sixth transistor include a current mirror stage for providing current from the voltage source to the second node and the fourth node.

[0094] In some examples of the apparatus, the condition includes a temperature of a memory chip associated with the circuit, and the range includes a temperature range of the memory chip.

[0095] In some examples of the apparatus, the first voltage profile of the first signal includes a first temperature gradient, and the second voltage profile of the first signal includes a second temperature gradient that can be lower than the first temperature gradient.

[0096] In some examples of the apparatus, the first transistor of the first type includes a first gate oxide thickness, and the second transistor of the second type includes a second gate oxide thickness that can be different from the first gate oxide thickness.

[0097] Another apparatus is described. The apparatus can include an amplifier including a first input stage and a second input stage, where the first input stage includes a first transistor of a first type coupled with a first node and having a gate coupled with a first signal, a second transistor of a second type coupled with the first node and having a gate coupled with the first signal, a first switch coupled with the first transistor and a second node and configured to receive a first control signal, and a second switch coupled with the second transistor and the second node and configured to receive a second control signal, where the first input stage of the amplifier is configured to switch between activating the first transistor of the first type and activating the second transistor of the second type, where the first transistor of the first type is configured to be activated based at least in part on the first switch receiving the first control signal and the first signal having a first voltage profile within a range of a condition, and where the second transistor of the second type is configured to be activated based at least in part on the second switch receiving the second control signal and the first signal having a second voltage profile within the range of the condition.

[0098] In some examples of the apparatus, the second input stage includes: a third transistor of the first type coupled with a third node and having a gate coupled with a second signal; a fourth transistor of the second type coupled with the third node and having a gate coupled with the second signal; a third switch coupled with the third transistor and a fourth node and configured to receive the first control signal; and a fourth switch coupled with the fourth transistor and the fourth node and configured to receive the second control signal.

[0099] In some examples of the apparatus, the second input stage of the amplifier is configurable to switch between activating the third transistor of the first type and activating the fourth transistor of the second type, and the third transistor of the first type is activated based at least in part on the third switch receiving the first control signal and the first signal having the first voltage distribution within a range of the condition.

[0100] In some examples of the apparatus, the fourth transistor of the second type is activated based at least in part on the fourth switch receiving the second control signal and the first signal having the second voltage distribution within a range of the condition.

[0101] In some examples, the apparatus can include: a fifth transistor of a third type coupled with a voltage source and the second node; and a sixth transistor of the third type coupled with the voltage source and a fourth node, where the fifth transistor and the sixth transistor include a current mirror stage for providing current from the voltage source to the second node and the fourth node.

[0102] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent multiple signals, where the bus can have multiple bit widths.

[0103] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which signals can flow from one component to another. Components are said to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there exists any conductive path that can support the flow of signals from one component to the other at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0104] The term "coupled" refers to the condition of components moving from an open circuit relationship between the components, in which signals cannot currently pass between the components through a conductive path, to a closed circuit relationship between the components, in which signals can pass between the components through a conductive path. When a component such as a controller couples other components together, then the component causes a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0105] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is a break in the circuit between them. Components that are separated by a switch positioned between the two components are isolated from each other when the switch is open. When a controller isolates two components, the controller effects a change that prevents signals from flowing between the components using a conductive path that previously permitted signal flow.

[0106] Devices discussed herein that include a memory array can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0107] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive material, such as metal. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be terminated by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. A transistor can be "turned off" or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0108] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0109] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of the first digit or digits of a reference label, where the additional digits are duplicates. If only the first digit or digits of a reference label are used to refer to a component, then the description is meaningful irrespective of the particular reference label name used. The use of "adapted to" or "configured to" herein can refer to an element or a number of elements configured to perform certain operations. Such configurations can be either permanent, in that such elements exist in a given state, or variable, in that the elements change between different states. As used herein, "adapted to" or "configured to" can refer to an element or a number of elements configured to perform certain operations (e.g., "adapted to" or "configured to" perform certain operations). As used herein, "adapted to" or "configured to" can refer to an element or a number of elements configured to receive, process, generate, or otherwise handle a certain piece of information, data, or parameter.

[0110] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0111] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein, as will be apparent to those skilled in the art. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0112] As used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” is not to be construed as a reference to a set of conditions that must be met, but rather, the phrase “based on” is to be construed as meaning “based at least in part on.”

[0113] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0114] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: a circuit comprising: a first transistor of a first type coupled with a first node and having a gate coupled with a first signal; a second transistor of a second type coupled with the first node and having a gate coupled with the first signal; a first switch coupled with the first transistor and a second node, wherein a first control signal of the first switch activates the first switch based at least in part on the first signal having a first voltage profile within a range of a condition, wherein the condition comprises a temperature of a memory chip associated with the circuit and the range comprises a temperature range of the memory chip; and a second switch coupled with the second transistor and the second node, wherein a second control signal of the second switch activates the second switch based at least in part on the first signal having a second voltage profile within the range of the condition.

2. The apparatus of claim 1, further comprising: a non-volatile memory element coupled with the circuit, wherein based at least in part on the non-volatile memory element storing a first value, the first control signal is configured to activate the first switch and the second control signal is configured to deactivate the second switch, and based at least in part on the non-volatile memory element storing a second value, the first control signal is configured to deactivate the first switch and the second control signal is configured to activate the second switch.

3. The apparatus of claim 1, wherein the circuit further comprises: a third transistor of the first type coupled with a third node and having a gate coupled with a second signal; a fourth transistor of the second type coupled with the third node and having a gate coupled with the second signal; a third switch coupled with the third transistor and a fourth node, wherein the first control signal of the first switch activates the third switch based at least in part on the first signal having the first voltage profile within the range of the condition; and a fourth switch coupled with the fourth transistor and the fourth node, wherein the second control signal of the fourth switch activates the fourth switch based at least in part on the first signal having the second voltage profile within the range of the condition.

4. The apparatus of claim 3, wherein the first node and the third node comprise a same node.

5. The apparatus of claim 3, wherein an output of the circuit is at the fourth node, and the output is based at least in part on a difference between the first signal and the second signal.

6. The apparatus of claim 3, wherein the first transistor of the first type, the second transistor of the second type, the first switch, and the second switch are associated with a first input stage of an amplifier, and the third transistor of the first type, the fourth transistor of the second type, the third switch, and the fourth switch are associated with a second input stage of the amplifier. ​ 7. The apparatus of claim 6, further comprising: a fifth transistor of a third type coupled with a voltage source and the second node; and a sixth transistor of the third type coupled with the voltage source and the fourth node, wherein the fifth transistor and the sixth transistor comprise a current mirror stage for providing current from the voltage source to the second node and the fourth node.

8. The apparatus of claim 1, wherein the first voltage profile of the first signal comprises a first temperature gradient, and the second voltage profile of the first signal comprises a second temperature gradient lower than the first temperature gradient.

9. The apparatus of claim 1, wherein the first transistor of the first type comprises a first gate oxide thickness, and the second transistor of the second type comprises a second gate oxide thickness different from the first gate oxide thickness.

10. A method comprising: receiving a first signal at a gate of a first transistor of a first type of a circuit, wherein the first transistor of the first type is coupled with a first node; receiving the first signal at a gate of a second transistor of a second type of the circuit, wherein the second transistor of the second type is coupled with the first node, wherein the first signal comprises a first voltage profile within a range of a condition or a second voltage profile within the range of the condition, wherein the condition comprises a temperature of a memory chip associated with the circuit, and the range comprises a temperature range of the memory chip; activating a first switch coupled with the first transistor and a second node based at least in part on receiving a first control signal and the first signal having the first voltage profile within the range of the condition; and maintaining a second switch coupled with the second transistor and the second node in a deactivated state based at least in part on activating the first switch.

11. The method of claim 10, further comprising: reading data from a non-volatile memory element coupled with the circuit, wherein based at least in part on reading a first value from the non-volatile memory element, the first control signal is configured to activate the first switch and a second control signal is configured to deactivate the second switch, and based at least in part on reading a second value from the non-volatile memory element, the first control signal is configured to deactivate the first switch and the second control signal is configured to activate the second switch.

12. The method of claim 10, wherein the first transistor, the second transistor, the first switch, and the second switch are associated with an input stage of an amplifier, the method further comprising: receiving an input voltage at a third node; and outputting an output voltage from the amplifier that is greater than the input voltage based at least in part on activating the first switch or activating the second switch.

13. The method of claim 10, further comprising: receiving an input voltage at a third node; comparing the input voltage to a voltage of the first signal; and outputting an output voltage from the circuit based at least in part on a difference between the input voltage and the voltage of the first signal.

14. The method of claim 10, wherein the first voltage profile of the first signal comprises a first temperature gradient and the second voltage profile of the first signal comprises a second temperature gradient different than the first temperature gradient.

15. An apparatus comprising: an amplifier comprising a first input stage and a second input stage, wherein the first input stage comprises: a first transistor of a first type coupled with a first node and having a gate coupled with a first signal; a second transistor of a second type coupled with the first node and having a gate coupled with the first signal; a first switch coupled with the first transistor and a second node and configured to receive a first control signal; and a second switch coupled with the second transistor and the second node and configured to receive a second control signal, wherein the first input stage of the amplifier is configured to switch between activating the first transistor of the first type and activating the second transistor of the second type, wherein the first transistor of the first type is configured to be activated based at least in part on the first switch receiving the first control signal and the first signal having a first voltage profile within a range of a condition, wherein the condition comprises a temperature of a memory chip associated with the amplifier and the range comprises a temperature range of the memory chip, and wherein the second transistor of the second type is configured to be activated based at least in part on the second switch receiving the second control signal and the first signal having a second voltage profile within the range of the condition.

16. The apparatus of claim 15, wherein the second input stage comprises: a third transistor of the first type coupled with a third node and having a gate coupled with a second signal; a fourth transistor of the second type coupled with the third node and having a gate coupled with the second signal; a third switch coupled with the third transistor and a fourth node and configured to receive the first control signal; and a fourth switch coupled with the fourth transistor and the fourth node and configured to receive the second control signal.

17. The apparatus of claim 16, wherein the second input stage of the amplifier is configured to switch between activating the third transistor of the first type and activating the fourth transistor of the second type, and the third transistor of the first type is activated based at least in part on the third switch receiving the first control signal and the first signal having the first voltage profile within the range of the condition.

18. The apparatus of claim 17, wherein the fourth transistor of the second type is activated based at least in part on the fourth switch receiving the second control signal and the first signal having the second voltage profile within the range of the condition. ​ 19. The apparatus of claim 15, further comprising: a fifth transistor of a third type coupled with a voltage source and the second node; and a sixth transistor of the third type coupled with the voltage source and a fourth node, wherein the fifth transistor and the sixth transistor comprise a current mirror stage for providing current from the voltage source to the second node and the fourth node.

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