Load open circuit detection circuit and detection method

Abstract

This invention provides a load open-circuit detection circuit and method. The detection circuit includes: a first switching transistor connected in series between a power supply terminal and a load; a sampling branch connected in series between the power supply terminal and the load, used to provide a sampling signal based on the load current; a detection module connected to the sampling branch, used to provide a feedback signal and an open-circuit warning signal based on the sampling signal; and a feedback adjustment module used to adjust the current of the first switching transistor based on the feedback signal and a preset first reference signal. This invention can achieve higher accuracy in open-circuit detection, and can also improve the accuracy of open-circuit detection even with small load current or low switching impedance, resulting in higher detection accuracy.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a load open-circuit detection circuit and detection method. Background Technology

[0002] With the development of technology, the application of circuits has become more and more widespread. At the same time, the increase in electrical equipment, i.e. loads, has also posed challenges to safe electricity use. If one load is damaged, it is very likely to damage other loads in the area at the same time, or even damage the power supply equipment, ultimately causing large-scale damage to the entire circuit, resulting in economic losses or even endangering lives.

[0003] To ensure the normal operation of the driver chip, various protection circuits are required. Among them, the load open-circuit detection circuit monitors the load status in real time and sends an open-circuit warning signal to the system promptly when an open-circuit fault occurs. This type of circuit typically detects the current across the load, such as... Figure 1 An existing open-circuit detection circuit mainly determines the load R by using the current detection module 11 to sample the current of the power transistor Q1. L Whether the circuit is open or closed, and the control voltage for power transistor Q1 is provided by logic circuit 12 and driver 13. However, this method results in small sampling input signal amplitude and large current sampling error when the on-resistance of power transistor Q1 is small or the load current is small, which can easily lead to misjudgment.

[0004] Therefore, it is necessary to provide improved technical solutions to overcome the above-mentioned technical problems existing in the prior art. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a load open-circuit detection circuit and detection method, which can achieve higher accuracy in open-circuit detection. Furthermore, it can improve the accuracy of open-circuit detection even with small load current or low switching impedance, resulting in higher detection accuracy.

[0006] According to a first aspect of the present invention, a load open-circuit detection circuit is provided, comprising:

[0007] The first switching transistor is connected in series between the power supply and the load;

[0008] A sampling branch is connected in series between the power supply terminal and the load to provide a sampling signal based on the load current.

[0009] The detection module, connected to the sampling branch, is used to provide feedback signals and open-circuit warning signals based on the sampling signals;

[0010] The feedback adjustment module is used to adjust the current of the first switching transistor according to the feedback signal and the preset first reference signal.

[0011] Optionally, when the load current is less than a first current threshold, the feedback adjustment module is used to reduce the current of the first switching transistor according to the feedback signal and a preset first reference signal.

[0012] Optionally, the feedback adjustment module reduces the current of the first switching transistor based on the difference between the feedback signal and a preset first reference signal.

[0013] Optionally, when the load current is less than a second current threshold, wherein the second current threshold is less than a first current threshold, the feedback adjustment module reduces the current of the first switching transistor to zero.

[0014] Optionally, the sampling branch includes a sampling resistor and a second switching transistor connected in series.

[0015] Optionally, the detection module includes:

[0016] A first error amplifier circuit is used to amplify the sampled signal to provide the feedback signal and the indication current signal;

[0017] An early warning circuit is used to provide an open-circuit early warning signal according to a preset clock signal when the indicated current signal is less than a preset reference current.

[0018] Optionally, the magnitudes of the feedback signal and the indication current signal are positively correlated with the magnitude of the load current.

[0019] Optionally, the warning circuit is configured to integrate the indicator current signal over time during the high or low level of the clock signal to obtain a first integrated signal, and to provide the open-circuit warning signal if the time when the first integrated signal reaches a preset second reference signal is later than a predetermined time.

[0020] The early warning circuit samples and outputs the comparison result between the first integral signal and the second reference signal at the predetermined time.

[0021] Optionally, the warning circuit is further configured to integrate the reference current with respect to time while integrating the indication current signal with respect to time to obtain a second integrated signal, wherein the predetermined time is the time when the second integrated signal reaches the second reference signal.

[0022] Optionally, the warning circuit is configured to integrate the indicator current signal over time to obtain a first integrated signal during the high or low level of the clock signal, and simultaneously integrate a preset reference current over time to obtain a second integrated signal, and output the open circuit warning signal when the first integrated signal is less than the second integrated signal.

[0023] Optionally, the feedback adjustment module includes:

[0024] The second error amplifier circuit has a first input terminal that receives the first reference signal and a second input terminal that receives the feedback signal.

[0025] The adjustment unit has its input terminal connected to the output terminal of the second error amplifier circuit, and its output terminal connected to the gate of the first switching transistor. The adjustment unit is used to adjust the gate voltage of the first switching transistor based on the output signal of the second error amplifier circuit when the load current decreases, so as to reduce the current flowing through the first switching transistor.

[0026] According to a second aspect of the present invention, a load open-circuit detection method is provided, applied to a load open-circuit detection circuit, the load open-circuit detection circuit including a sampling branch, a detection module, and a feedback adjustment module, wherein the sampling branch is connected in parallel with the power supply control switch of the load, and the load open-circuit detection method includes:

[0027] The load current is sampled using a sampling branch to obtain a sampling signal;

[0028] The detection module provides feedback signals and open-circuit warning signals based on the sampled signals;

[0029] The current of the power supply control switch is adjusted using a feedback adjustment module based on the feedback signal and a preset first reference signal.

[0030] Optionally, adjusting the current of the power supply control switch using the feedback adjustment module based on the feedback signal and a preset first reference signal includes:

[0031] When the load current is less than the first current threshold, the current of the power supply control switch is reduced by the feedback adjustment module according to the feedback signal and the preset first reference signal.

[0032] Optionally, the feedback adjustment module reduces the current of the power supply control switch based on the difference between the feedback signal and a preset first reference signal.

[0033] Optionally, when the load current is less than a second current threshold, wherein the second current threshold is less than a first current threshold, the feedback adjustment module reduces the current of the power supply control switch to zero.

[0034] Optionally, the detection module provides feedback signals and open-circuit warning signals based on the sampled signals, including:

[0035] The sampled signal is amplified to provide the feedback signal and the indication current signal;

[0036] When the indicated current signal is less than a preset reference current, the open circuit warning signal is provided according to a preset clock signal.

[0037] Optionally, the magnitudes of the feedback signal and the indication current signal are positively correlated with the magnitude of the load current.

[0038] Optionally, providing the open-circuit warning signal according to a preset clock signal when the indicated current signal is less than a preset reference current includes:

[0039] During the high or low level of the clock signal, the indicator current signal is integrated over time to obtain a first integrated signal;

[0040] The open-circuit warning signal is provided if the time when the first integrated signal reaches the preset second reference signal is later than a predetermined time.

[0041] Specifically, at the predetermined time, the comparison result between the first integrated signal and the second reference signal is sampled and output.

[0042] Optionally, the predetermined time is the time when the second integrated signal reaches the second reference signal, and the second integrated signal is obtained by integrating a preset reference current over time.

[0043] Optionally, providing the open-circuit warning signal according to a preset clock signal when the indicated current signal is less than a preset reference current includes:

[0044] During the high or low level of the clock signal, the indicator current signal is integrated over time to obtain a first integrated signal, and a preset reference current is integrated over time to obtain a second integrated signal.

[0045] The open-circuit warning signal is output when the first integral signal is less than the second integral signal.

[0046] The beneficial effects of the present invention include at least the following:

[0047] In this embodiment of the invention, an additional sampling branch is connected in parallel across the main switch (i.e., the first switch). The load current is detected by sampling the current information on this branch. At the same time, the invention also adjusts the current of the main switch based on the sampling results of the sampling branch, so that the current on the main switch can be reduced when the load current is small, thereby allowing more current to be shunted in the sampling branch. Compared with the prior art, this reduces the impact of the offset voltage of the sampling branch on the sampling accuracy, enabling accurate open-circuit detection even under small load current conditions.

[0048] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0049] Figure 1 This diagram shows a schematic of an existing open-circuit detection circuit.

[0050] Figure 2 This diagram illustrates the structure of a load open-circuit detection circuit provided according to an embodiment of the present invention.

[0051] Figure 3 This diagram shows a schematic of the load open-circuit detection circuit in one of the examples of the present invention.

[0052] Figure 4 Show Figure 2 and Figure 3 A schematic diagram of the intermediate error amplifier circuit;

[0053] Figure 5a The first embodiment of the present invention is shown. Figure 2 A schematic diagram of the structure of the early warning circuit;

[0054] Figure 5b This illustrates a method provided according to a second embodiment of the present invention. Figure 2 A schematic diagram of the structure of the early warning circuit;

[0055] Figure 6 A schematic diagram showing the timing relationship of some signals in a load open-circuit detection circuit provided according to an embodiment of the present invention is shown.

[0056] Figure 7 A schematic flowchart of a load open-circuit detection method provided according to an embodiment of the present invention is shown. Detailed Implementation

[0057] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0058] like Figure 2 and Figure 3 As shown, the load open-circuit detection circuit disclosed in this embodiment of the invention includes: a switching transistor Q1, a sampling branch 21, a detection module 22, and a feedback adjustment module 23. The switching transistor Q1 serves as the load R. L The power supply control switch is the main switching transistor in the circuit. Switch Q1 is connected to the load R. L The sampling branch 21 is connected in series between the power supply terminal VCC and the reference ground. The sampling branch 21 is connected in parallel between the drain and source of the switching transistor Q1, meaning it is also connected in series between the power supply terminal VCC and the reference ground. The sampling branch 21 is used to measure the load current I.L A sampling signal (denoted as Vs) is provided. The detection module 22 is connected to the sampling branch 21 and is used to provide a feedback signal FB and an open-circuit warning signal OPEN based on the sampling signal Vs. The feedback adjustment module 23 is used to adjust the current (denoted as I1) flowing through the switching transistor Q1 based on the feedback signal FB and a preset reference signal Vref1.

[0059] It is understandable that the load current I L It equals the sum of the branch current (denoted as I2) of sampling branch 21 and the current I1 flowing through switch Q1. Therefore, the branch current I2 and the load current I L Positive correlation, and the sampled signal Vs is positively correlated with the load current I. L It also shows a positive correlation. This invention detects the branch current I2 by sampling the signal Vs, thereby indirectly achieving the detection of the load current I. L The purpose.

[0060] Specifically, the gate of switch Q1 is connected to driver 24, which generates a control signal for switch Q1 based on drive signal P_DR to control the conduction state of switch Q1. For example, switch Q1 is an NMOS transistor or a PMOS transistor.

[0061] Sampling branch 21 includes a sampling resistor Rs and a switching transistor Q2 connected in series. Switch Q2 is a secondary switching transistor, and its gate is connected to a driver 25. The driver 25 generates a control signal for switch Q2 based on a drive signal P_DR to control the conduction of switch Q2. For example, switch Q2 is an NMOS transistor or a PMOS transistor. Sampling branch 21 obtains a sampling signal Vs across the sampling resistor Rs based on the branch current I2 flowing through the sampling resistor Rs and the switching transistor Q2. The sampling signal Vs = Va - Vb, where Va and Vb correspond to the node potentials across the sampling resistor Rs, respectively.

[0062] It is understood that in this embodiment of the invention, the load current I is detected based on the sampling resistor Rs. L At the same load current I L This allows for the acquisition of a relatively reliable sampling signal input, reduces the impact of the switching transistor's on-resistance on sampling accuracy, and helps improve detection accuracy.

[0063] The detection module 22 further includes an error amplifier circuit 221 and an early warning circuit 222. The error amplifier circuit 221 amplifies the sampled signal Vs to provide a feedback signal FB and an indication current signal Is. The early warning circuit 222 provides an open-circuit early warning signal OPEN based on a preset clock signal CLK when the indication current signal Is is less than a preset reference current Iref.

[0064] Further reference Figure 4 The error amplifier circuit 221 includes transistors Q11 to Q17 and resistor R3. Transistors Q11, Q12, and Q13 form a current mirror structure, as do transistors Q14 and Q15. The drain of transistor Q11 receives the bias current Ib; transistors Q12 and Q14 are connected in series; transistors Q15 and Q13 are connected in series; the source of transistor Q14 receives the node voltage Va via resistor R1, and the source of transistor Q15 receives the node voltage Vb via resistor R2. The gate of transistor Q16 is connected to the drain of transistor Q15, the source of transistor Q16 receives the node voltage Va via resistor R1, and the drain of transistor Q16 is connected to reference ground via resistor R3. Transistor Q16 is located on the first output branch of the error amplifier circuit 221, and the error amplifier circuit 221 outputs a feedback signal FB at the drain of transistor Q16. The gate of transistor Q17 is connected to the drain of transistor Q15. The source of transistor Q17 receives the node voltage Va via resistor R1. Transistor Q17 is located on the second output branch of error amplifier circuit 221, and error amplifier circuit 221 outputs an indicator current signal Is at the drain of transistor Q17. For example, transistors Q11 to Q13 are all NMOS transistors, and transistors Q14 to Q17 are all PMOS transistors.

[0065] As can be seen from the working principle of the error amplifier circuit, the magnitudes of the feedback signal FB and the indicating current signal Is are both related to the load current I. L The magnitudes are positively correlated.

[0066] Optionally, in the first embodiment of the present invention, the warning circuit 222 is configured to integrate the indicating current signal Is over time during the high or low level of the clock signal CLK to obtain an integrated signal V1, and to provide an open-circuit warning signal OPEN when the time at which the integrated signal V1 reaches a preset reference signal Vref2 is later than a predetermined time. The warning circuit 222 is used to sample and output the comparison result between the integrated signal V1 and the reference signal Vref2 at the predetermined time. It should be understood that this embodiment can accurately sample and output the open-circuit warning signal OPEN when the indicating current signal Is is less than a preset reference current, with high accuracy and reliability.

[0067] In this first embodiment, the warning circuit 222 is further configured to integrate the indicated current signal Is over time while simultaneously integrating a preset reference current Iref over time to obtain an integrated signal V2. At this time, the aforementioned predetermined time is the moment when the integrated signal V2 reaches the reference signal Vref2. In other words, the warning circuit 222 is configured to output an open-circuit warning signal OPEN when the integrated signal V2 reaches the reference signal Vref2 during a period when the integrated signal V1 is less than the reference signal Vref2. Exemplarily, in this first embodiment, as... Figure 5a As shown, the warning circuit 222 includes: capacitor C1, capacitor C2, switching transistors Q4 and Q5, comparator 2221, comparator 2222, and D flip-flop 2223. The first terminal of capacitor C1 receives the indication current signal Is, and the second terminal of capacitor C1 is connected to reference ground. Switch Q4 provides a discharge path for capacitor C1 according to the clock signal CLK. The first input terminal of comparator 2221 is connected to the first terminal of capacitor C1 to receive the integration signal V1, and the second input terminal of comparator 2221 receives the reference signal Vref2. The first terminal of capacitor C2 receives the reference current Iref, and the second terminal of capacitor C2 is connected to reference ground. Switch Q5 provides a discharge path for capacitor C2 according to the clock signal CLK. The first input terminal of comparator 2222 is connected to the first terminal of capacitor C2 to receive the integration signal V2, and the second input terminal of comparator 2222 receives the reference signal Vref2. The data input of D flip-flop 2223 is connected to the output of comparator 2221, and the clock input of D flip-flop 2223 is connected to the output of comparator 2222. The reset terminal of D flip-flop 2223 receives the clock signal CLK, and the output of D flip-flop 2223 outputs an open-circuit warning signal OPEN. In this embodiment, both switching transistors Q4 and Q5 are exemplified as NMOS transistors. The warning circuit 222 integrates the indicator current signal Is and the reference current Iref over time during the low level of the clock signal CLK, and discharges capacitors C1 and C2 during the high level of the clock signal CLK.

[0068] Optionally, in the second embodiment of the present invention, the warning circuit 222 is configured to integrate the indicating current signal Is over time to obtain an integrated signal V1 during a specific time period (such as the high-level or low-level period of the clock signal CLK), and simultaneously integrate a preset reference current Iref over time to obtain an integrated signal V2 during the same specific time period. If the integrated signal V1 is less than the integrated signal V2, an open-circuit warning signal OPEN is output. In this second embodiment, a reference signal Vref2 can be omitted; a single comparator can be used to directly compare the integrated signals V1 and V2, resulting in a simple circuit structure.

[0069] Exemplarily, in this second embodiment, such as Figure 5b As shown, the warning circuit 222 includes: capacitor C3, capacitor C4, switching transistors Q6 and Q7, and comparator 2224. The first terminal of capacitor C3 receives an indication current signal Is, and the second terminal of capacitor C3 is connected to reference ground. Switch Q6 provides a discharge path for capacitor C3 according to the clock signal CLK. The first terminal of capacitor C4 receives a reference current Iref, and the second terminal of capacitor C4 is connected to reference ground. Switch Q7 provides a discharge path for capacitor C4 according to the clock signal CLK. The first input terminal of comparator 2224 is connected to the first terminal of capacitor C3 to receive the integration signal V1, the second input terminal of comparator 2224 is connected to the first terminal of capacitor C4 to receive the integration signal V2, and the output terminal of comparator 2224 outputs an open-circuit warning signal OPEN. In this embodiment, both switch Q6 and switch Q7 are exemplified as NMOS transistors. Thus, the warning circuit 222 integrates the indicator current signal Is and the reference current Iref over time during the low level of the clock signal CLK, and discharges capacitors C3 and C4 during the high level of the clock signal CLK.

[0070] When the load current I L When the current is less than a first current threshold, the feedback adjustment module 23 is configured to reduce the current of the switching transistor Q1 based on the feedback signal FB and the reference signal Vref1. Exemplarily, in some embodiments of the present invention, the feedback adjustment module 23 is specifically configured to reduce the current of the switching transistor Q1 based on the difference between the feedback signal FB and the reference signal Vref1.

[0071] When the load current I L When the current is less than the second current threshold (the second current threshold is less than the first current threshold), the feedback adjustment module 23 reduces the current of the switching transistor Q1 to zero according to the feedback signal FB and the reference signal Vref1.

[0072] For example, refer to Figure 2 The feedback adjustment module 23 includes an error amplifier circuit 231 and an adjustment unit 232. The first input terminal of the error amplifier circuit 231 receives a reference signal Vref1, and the second input terminal receives a feedback signal FB. The error amplifier circuit 231 outputs a signal representing the difference between the feedback signal FB and the reference signal Vref1. The input terminal of the adjustment unit 232 is connected to the output terminal of the error amplifier circuit 231, and the output terminal of the adjustment unit 232 is connected to the gate of the switching transistor Q1. The adjustment unit 232 is used to adjust the load current I... L When the current is reduced, the gate voltage Vgs1 of the switch Q1 is adjusted based on the output signal of the error amplifier circuit 231, thereby reducing the current I1 flowing through the switch Q1.

[0073] Optionally, the first input terminal of the error amplifier circuit 231 can be either its positive or negative input terminal. Correspondingly, when the first input terminal of the error amplifier circuit 231 is positive, its second input terminal is negative; conversely, when the first input terminal of the error amplifier circuit 231 is negative, its second input terminal is positive. Furthermore, the specific function and structure of the adjustment unit 232 differ depending on the type of the switching transistor Q1. For example, when the switching transistor Q1 is an NMOS transistor, the adjustment unit 232 is used to adjust the load current I... L When the voltage is reduced, the gate voltage Vgs1 of the switch Q1 is reduced based on the output signal of the error amplifier circuit 231, so as to reduce the current I1 flowing through the switch Q1; while when the switch Q1 is a PMOS transistor, the adjustment unit 232 is used to reduce the load current I1. L When the current decreases, the output signal of the error amplifier circuit 231 increases the gate voltage Vgs1 of the switch Q1 in order to reduce the current I1 flowing through the switch Q1.

[0074] In some examples of this invention, the switching transistor Q1 is an NMOS transistor, as shown in the reference. Figure 3 The adjustment unit 232 includes, for example, a switching transistor Q3, with the drain of the switching transistor Q3 connected to the gate of the switching transistor Q1, the source of the switching transistor Q3 connected to the reference ground, and the gate of the switching transistor Q3 connected to the output terminal of the error amplifier circuit 231.

[0075] As mentioned above, the feedback signal FB and the load current I L The correlation is positive, when the load current I L When the value is relatively small, the feedback signal FB is also relatively small, while the difference between the reference signal Vref1 and the feedback signal FB, and the output signal of the error amplifier circuit 231 are relatively large.

[0076] Figure 6 for Figures 3 to 5b The timing diagram of the circuit structure shown is illustrated when the switching transistor Q1 is an NMOS transistor. (Refer to...) Figure 6 At load current I L During periods exceeding the first current threshold, the output signal of the error amplifier circuit 231 is relatively small. At this time, switch Q3 is in the off state, and the gate voltage Vgs1 of switch Q1 remains constant, controlling switch Q1 to be fully on, resulting in a low on-resistance. When the load current I... L When the current decreases to the first current threshold, the output signal of the error amplifier circuit 231 increases to a certain extent, controlling the switch Q3 to start pulling down the gate voltage Vgs1 of the switch Q1, and as the load current I... LAs the voltage decreases, the gate voltage Vgs1 of switch Q1 also gradually decreases, the on-resistance of switch Q1 gradually increases, and the current I1 flowing through switch Q1 gradually decreases, with the rate of decrease accelerating compared to before time t1. This, in turn, leads to a decrease in the load current I... L During the period when the current is less than the first current threshold but greater than the second current threshold (i.e., within time period t1 to t2), a significant amount of current can be shunted in sampling branch 21. This continues until the load current I... L When the current decreases to the second current threshold (i.e., at time t2), the output signal of the error amplifier circuit 231 enables the switch Q3 to pull down the gate voltage Vgs1 of the switch Q1 to its turn-off threshold, thereby controlling the switch Q1 to turn off. At this time, the current I1 flowing through the switch Q1 decreases to zero.

[0077] With the load current I L When the branch current I2 decreases to the corresponding predetermined value, and the integral result of the corresponding indicator current signal Is within a specific time is less than the set threshold, the warning circuit 222 is triggered to output the open circuit warning signal OPEN.

[0078] Based on the above description, this embodiment of the invention detects the load current I by setting a sampling resistor Rs on the sampling branch 21. L Simultaneously, a feedback loop is set up to control the gate voltage of the switching transistor Q1 based on the detection result, thereby adjusting the current on the switching transistor Q1. This ensures that the load current I... L When the current is low, the on-resistance of switch Q1 can be increased by adjusting the gate voltage of switch Q1, thereby reducing the current on the main switch. This results in more current being shunted in the sampling branch, reducing the impact of the offset voltage of the sampling branch on the sampling accuracy, and enabling accurate open-circuit detection even with a small load current. Furthermore, this invention only adjusts the gate voltage Vgs1 of switch Q1 through feedback adjustment module 23 to regulate the current on switch Q1 under low current load conditions. Compared to existing technologies, this increases the sampling signal input and reduces the impact on the load R. L The actual impact on operation is minimal. In other words, the load open-circuit detection circuit disclosed in this invention can improve the accuracy of open-circuit detection even with small load current or low switching impedance, thus resulting in higher detection accuracy.

[0079] Furthermore, the present invention also provides a load open-circuit detection method, which can be applied to the aforementioned methods. Figures 2 to 6 The load open-circuit detection circuit shown is illustrated. Figure 7 As shown, the load open-circuit detection method includes performing the following steps:

[0080] In step S1, the load current is sampled using the sampling branch to obtain a sampling signal.

[0081] In this embodiment, reference Figure 2 Sampling branch 21 and load R L The power supply control switch, i.e., the switching transistor Q1, is connected in parallel. The sampling branch 21 includes a sampling resistor Rs and the switching transistor Q2 connected in series. The sampling branch 21 obtains the load current I across the sampling resistor Rs. L The sampled signal Vs.

[0082] In step S2, the detection module provides feedback signals and open-circuit warning signals based on the sampled signals.

[0083] In this embodiment, step S2 further includes: amplifying the sampled signal Vs to provide a feedback signal FB and an indication current signal Is; and providing an open-circuit warning signal open according to a preset clock signal CLK when the indication current signal Is is less than a preset reference current. The magnitudes of the feedback signal FB and the indication current signal Is are related to the load current I. L The magnitudes are positively correlated.

[0084] In some embodiments of the present invention, providing an open-circuit warning signal based on a preset clock signal CLK when the indicated current signal Is is less than a preset reference current further includes: integrating the indicated current signal Is over time during the high or low level of the clock signal CLK to obtain a first integrated signal, i.e., the aforementioned integrated signal V1; and providing an open-circuit warning signal OPEN when the time at which the first integrated signal V1 reaches a preset second reference signal (i.e., the aforementioned reference signal Vref2) is later than a predetermined time. The predetermined time is the time when the second integrated signal (i.e., the aforementioned integrated signal V2) reaches the second reference signal Vref2, and at the predetermined time, the comparison result between the first integrated signal V1 and the second reference signal Vref2 is sampled and output, and the second integrated signal V2 is obtained based on integrating the preset reference current Iref over time.

[0085] In some other embodiments of the present invention, providing an open-circuit warning signal OPEN according to a preset clock signal CLK when the indicated current signal Is is less than a preset reference current further includes: integrating the indicated current signal Is with respect to time during the high or low level of the clock signal CLK to obtain a first integrated signal V1, and simultaneously integrating the preset reference current Iref with respect to time to obtain a second integrated signal V2; and outputting the open-circuit warning signal OPEN when the first integrated signal V1 is less than the second integrated signal V2.

[0086] In step S3, the current of the power supply control switch is adjusted by the feedback adjustment module according to the feedback signal and the preset first reference signal.

[0087] In this embodiment, step S3 further includes: when the load current I... LWhen the current is less than a first current threshold, the current of the power supply control switch (i.e., the aforementioned switch Q1) is reduced according to the first reference signal (i.e., the aforementioned reference signal Vref1) and the feedback signal FB. For example, when the load current I... L When the current is less than the first current threshold, the current of the power supply control switch (i.e., the aforementioned switch Q1) can be reduced based on the difference between the first reference signal (i.e., the aforementioned reference signal Vref1) and the feedback signal FB.

[0088] Furthermore, when the load current is less than the second current threshold, which is less than the first current threshold, the power supply control switch is turned off, and the current flowing through the power supply control switch is zero.

[0089] It should be noted that the specific implementation of each step in the load open circuit detection method described above can be found in the aforementioned embodiment of the load open circuit detection circuit, and will not be repeated here.

[0090] In summary, this embodiment of the invention adds a sampling branch in parallel across the main switch. By sampling the current information on this branch, the load current is detected. Furthermore, this invention adjusts the current of the main switch based on the sampling results of the sampling branch, thereby reducing the current on the main switch when the load current is small. This results in more current being shunted in the sampling branch. Compared with the prior art, this reduces the impact of the offset voltage of the sampling branch on the sampling accuracy, enabling accurate open-circuit detection even under small load current conditions.

[0091] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A load open-circuit detection circuit, wherein, include: The first switching transistor is connected in series between the power supply and the load; A sampling branch is connected in series between the power supply terminal and the load to provide a sampling signal based on the load current. The detection module, connected to the sampling branch, is used to provide feedback signals and open-circuit warning signals based on the sampling signals; The feedback adjustment module is used to adjust the current of the first switching transistor according to the feedback signal and a preset first reference signal. When the load current is less than the first current threshold, the feedback adjustment module is used to reduce the current of the first switching transistor according to the feedback signal and the preset first reference signal. When the load current is less than the second current threshold, wherein the second current threshold is less than the first current threshold, the feedback adjustment module reduces the current of the first switching transistor to zero.

2. The load open-circuit detection circuit according to claim 1, wherein, The feedback adjustment module reduces the current of the first switching transistor based on the difference between the feedback signal and the preset first reference signal.

3. The load open-circuit detection circuit according to claim 1, wherein, The sampling branch includes a sampling resistor and a second switching transistor connected in series.

4. The load open-circuit detection circuit according to claim 1, wherein, The detection module includes: A first error amplifier circuit is used to amplify the sampled signal to provide the feedback signal and the indication current signal; An early warning circuit is used to provide an open-circuit early warning signal according to a preset clock signal when the indicated current signal is less than a preset reference current.

5. The load open-circuit detection circuit according to claim 4, wherein, The magnitudes of the feedback signal and the indication current signal are positively correlated with the magnitude of the load current.

6. The load open-circuit detection circuit according to claim 4, wherein, The warning circuit is configured to integrate the indicator current signal over time during a high or low level of the clock signal to obtain a first integrated signal, and to provide the open-circuit warning signal if the time when the first integrated signal reaches a preset second reference signal is later than a predetermined time. The early warning circuit samples and outputs the comparison result between the first integral signal and the second reference signal at the predetermined time.

7. The load open-circuit detection circuit according to claim 6, wherein, The warning circuit is further configured to integrate the reference current with respect to time while integrating the indicator current signal with respect to time to obtain a second integrated signal, wherein the predetermined time is the time when the second integrated signal reaches the second reference signal.

8. The load open-circuit detection circuit according to claim 4, wherein, The warning circuit is configured to integrate the indicator current signal over time to obtain a first integrated signal during the high or low level of the clock signal, and simultaneously integrate a preset reference current over time to obtain a second integrated signal, and output the open circuit warning signal when the first integrated signal is less than the second integrated signal.

9. The load open-circuit detection circuit according to claim 2, wherein, The feedback adjustment module includes: The second error amplifier circuit has a first input terminal that receives the first reference signal and a second input terminal that receives the feedback signal. An adjustment unit has its input terminal connected to the output terminal of the second error amplifier circuit, and its output terminal connected to the gate of the first switching transistor. The adjustment unit is used to adjust the gate voltage of the first switching transistor based on the output signal of the second error amplifier circuit when the load current decreases.

10. A load open-circuit detection method, applied to a load open-circuit detection circuit, the load open-circuit detection circuit comprising a sampling branch, a detection module, and a feedback adjustment module, wherein the sampling branch is connected in parallel with the power supply control switch of the load, wherein... The load open-circuit detection method includes: The load current is sampled using a sampling branch to obtain a sampling signal; The detection module provides feedback signals and open-circuit warning signals based on the sampled signals; The current of the power supply control switch is adjusted using a feedback adjustment module based on the feedback signal and a preset first reference signal. The method of adjusting the current of the power supply control switch using the feedback adjustment module based on the feedback signal and a preset first reference signal includes: When the load current is less than the first current threshold, the current of the power supply control switch is reduced by the feedback adjustment module according to the feedback signal and the preset first reference signal; And, when the load current is less than the second current threshold, wherein the second current threshold is less than the first current threshold, the feedback adjustment module reduces the current of the power supply control switch to zero.

11. The load open-circuit detection method according to claim 10, wherein, The feedback adjustment module reduces the current of the power supply control switch based on the difference between the feedback signal and the preset first reference signal.

12. The load open-circuit detection method according to claim 10, wherein, The detection module provides feedback signals and open-circuit warning signals based on the sampled signals, including: The sampled signal is amplified to provide the feedback signal and the indication current signal; When the indicated current signal is less than a preset reference current, the open circuit warning signal is provided according to a preset clock signal.

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