Power-off processing method, solid-state hard disk, and computing device

Abstract

The present application provides a power-off processing method, a solid-state hard disk and a computing device. The solid-state hard disk includes a main control chip and a backup power capacitor electrically connected to the main control chip, a volatile memory chip and at least one non-volatile memory chip. When the main control chip detects that the solid-state hard disk is in a power-off state, it controls the backup power capacitor to power the solid-state hard disk, obtains the data to be stored in the volatile memory chip, and for each data type of the data to be stored, determines the corresponding power-off storage space according to the data type of the data to be stored, and stores the data to be stored in the corresponding power-off storage space; the power-off storage space includes part of the storage space in at least one non-volatile memory chip, and the power-off storage space is a single-layer unit type storage space. This solves the problem in the related art that the backup power capacitor has a short power supply time, resulting in the solid-state hard disk being unable to write all the data to be stored in the volatile memory chip into the non-volatile memory chip when the power is off, resulting in data loss.

Description

Technical Field

[0001] The present application relates to the technical field of solid-state hard disks, and in particular to a power-off processing method, a solid-state hard disk, and a computing device. Background Art

[0002] A solid-state drive (SSD), also known as a solid-state drive (SSD), is a hard drive made with an array of solid-state electronic memory chips. To improve the read and write performance of SSDs, SSDs typically write data to a volatile memory chip first, then write the data from the volatile memory chip to a non-volatile memory chip for permanent storage.

[0003] When a solid-state drive loses power, the data in the volatile memory chip is completely lost, affecting the data storage effect. In related technologies, the SSD can be temporarily powered by the built-in backup capacitor, so that the data in the volatile memory chip can still be written to the non-volatile memory chip when the SSD loses power.

[0004] However, the power supply time of the backup capacitor in the related art is relatively short, resulting in the inability of the solid-state drive to write all the data to be stored in the volatile memory chip to the non-volatile memory chip when the power is off, thereby causing data loss. Summary of the Invention

[0005] The embodiments of the present application provide a power-off processing method, a solid-state hard drive, and a computing device, which are used to solve the problem in the related art that the power supply time of the backup capacitor is short, resulting in the solid-state hard drive being unable to write all the data to be stored in the volatile memory chip to the non-volatile memory chip when the power is off, thereby causing data loss.

[0006] In a first aspect, an embodiment of the present application provides a power-off processing method, which is applied to a solid-state drive. The solid-state drive includes a main control chip and a backup capacitor electrically connected to the main control chip, a volatile memory chip, and at least one non-volatile memory chip. The method includes:

[0007] When the main control chip detects that the solid-state hard disk is in a power-off state, it controls the backup capacitor to supply power to the solid-state hard disk and obtains the data to be stored in the volatile memory chip; wherein the data to be stored includes data of multiple data types to be stored;

[0008] The main control chip determines, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and stores the data to be stored in the corresponding power-off storage space;

[0009] The power-off storage space includes a portion of storage space in at least one non-volatile memory chip, and the power-off storage space is a single-layer unit type storage space.

[0010] The beneficial effects of this embodiment are as follows: On the one hand, this embodiment utilizes the fast data storage speed of the single-layer cell type storage space. When the solid-state drive is in a power-off state, the data to be stored in the volatile memory chip is stored in the single-layer cell type power-off storage space in the non-volatile memory chip, thereby improving the storage speed of the data to be stored, ensuring that the solid-state drive can store a large amount of data in the non-volatile memory chip within a limited storage time, and reducing the possibility that the solid-state drive cannot write all the data to be stored in the volatile memory chip to the non-volatile memory chip when the power is off, thereby causing the possibility of loss of the data to be stored. On the other hand, this embodiment can directly determine the corresponding power-off storage space based on the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space, avoiding the time-consuming search for available power-off storage space and improving the storage speed of the data to be stored.

[0011] In the preferred technical solution of the power-off processing method described above, the main control chip determines, for each data type of data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and stores the data to be stored in the corresponding power-off storage space, including:

[0012] The main control chip determines the power-off storage space corresponding to the data to be stored for each data type according to the data type of the data to be stored, determines the storage channel corresponding to the corresponding power-off storage space, and stores the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

[0013] The beneficial effects of this embodiment are as follows: the main control chip can directly determine the power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and determine the storage channel corresponding to the corresponding power-off storage space, and directly store the data to be stored in the corresponding power-off storage space through the corresponding storage channel, thereby avoiding the time-consuming search for available power-off storage space and the corresponding storage channel, and improving the storage speed of the data to be stored.

[0014] In the preferred technical solution of the power-off processing method described above, the main control chip determines, for each data type of data to be stored, a power-off storage space corresponding to the data to be stored, and determines a storage channel corresponding to the corresponding power-off storage space according to the data type of the data to be stored, and stores the data to be stored in the corresponding power-off storage space through the corresponding storage channel, including:

[0015] The main control chip reads a first correspondence table and a second correspondence table stored in the volatile memory chip, or reads the first correspondence table and the second correspondence table stored in the non-volatile memory chip; wherein the first correspondence table is a correspondence table between data types and power-off storage spaces, and the second correspondence table is a correspondence table between power-off storage spaces and storage channels;

[0016] The main control chip determines, for each data type of data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored and the first correspondence table, and determines a storage channel corresponding to the corresponding power-off storage space according to the corresponding power-off storage space and the second correspondence table, and stores the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

[0017] The beneficial effects of this embodiment are as follows: the first correspondence table between data types and power-off storage spaces, and the second correspondence table between power-off storage spaces and storage channels can be stored in a volatile memory chip or a non-volatile memory chip. When the solid-state hard disk loses power, the main control chip can directly read the first correspondence table and the second correspondence table to determine a power-off storage space suitable for storing data to be stored of each data type, and a storage channel leading to the power-off storage space, so that the main control chip can quickly store the data to be stored in the power-off storage space, thereby improving the storage speed of the data to be stored.

[0018] The preferred technical solution for power failure processing described above also includes:

[0019] The main control chip generates a power-off data completion flag corresponding to the data type of the data to be stored, after storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel, and stores the power-off data completion flag in the power-off storage space;

[0020] When the main control chip detects that the solid state drive is in a powered-on state and the power-off data storage completion mark is stored in the power-off storage space, the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip.

[0021] The beneficial effects of this embodiment are as follows: After the main control chip stores the data to be stored in the corresponding power-down storage space through the corresponding storage channel, it generates a power-down data completion flag corresponding to the data type of the data to be stored, indicating that the data to be stored in the power-down storage space has been completely stored. The main control chip stores the power-down data completion flag in the power-down storage space so that it can subsequently determine whether the data to be stored is completely stored in the power-down storage space based on whether the power-down data completion flag is stored in the power-down storage space, thereby implementing integrity verification of the stored data by the main control chip. In addition, after the main control chip performs integrity verification on the data to be stored in the power-off storage space, the data to be stored that has passed the verification is stored in the non-power-off storage space of the non-volatile memory chip. On the one hand, compared with other non-single-layer unit type storage spaces, the available capacity of the power-off storage space is a single-layer unit type storage space. Storing the data to be stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip can reduce the number of cells occupied by the data to be stored; on the other hand, storing the data to be stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip can subsequently perform data clearing processing on the power-off storage space, thereby providing available power-off storage space for the second power-off of the solid-state hard disk, and preventing insufficient power-off storage space during the second power-off.

[0022] In the preferred technical solution of the above-mentioned power-off processing method, when the main control chip detects that the solid-state hard disk is in a powered-on state and a power-off data storage completion mark is displayed in the power-off storage space, the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip, including:

[0023] When the main control chip detects that the solid state drive is in a powered-on state and a power-off data storage completion mark is displayed in the power-off storage space, the main control chip stores the data to be stored in the power-off storage space into the volatile memory chip;

[0024] The main control chip stores the data to be stored in the volatile memory chip into the non-power-off storage space of the non-volatile memory chip.

[0025] The beneficial effects of this embodiment are as follows: when the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip, the data to be stored can be first stored in the volatile memory chip for management, and then the data to be stored in the volatile memory chip can be stored in the non-power-off storage space of the non-volatile memory chip. This allows the main control chip to store the data to be stored in the volatile memory chip into the non-power-off storage space of the non-volatile memory chip when the amount of data to be stored in the volatile memory chip reaches a certain amount, thereby reducing the number of accesses to the non-volatile memory chip and extending the service life of the solid-state drive.

[0026] In the preferred technical solution of the power-off processing method described above, when the main control chip detects that the solid-state hard disk is in a powered-on state and a power-off data storage completion mark is displayed in the power-off storage space, the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip, including:

[0027] When the main control chip detects that the solid state drive is in a powered-on state and the power-off data storage completion mark is stored in the power-off storage space, it directly stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip.

[0028] The beneficial effect of this embodiment is that the main control chip can directly store the data to be stored in the acquired power-off storage space into the non-power-off storage space of the non-volatile memory chip, thereby improving the data storage speed.

[0029] In the preferred technical solution of the above power-off processing method, the following is also included:

[0030] The main control chip formats the power-off storage space into the single-layer unit type storage space to perform data clearing processing on the power-off storage space.

[0031] The beneficial effects of this embodiment are as follows: after the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space, it can format the power-off storage space into a single-layer unit type storage space to clear data in the power-off storage space, ensuring that when the solid-state hard disk loses power for the second time, the main control chip does not need to spend time searching for available power-off storage space, and can directly store the data to be stored in the corresponding power-off storage space, thereby improving the data storage speed.

[0032] In the preferred technical solution of the above power-off processing method, the following is also included:

[0033] The main control chip determines the amount of data to be stored for each data type and the capacity corresponding to each power-off storage space;

[0034] The main control chip adjusts the power-failure storage space corresponding to the data to be stored according to the amount of the data to be stored of each data type and the capacity corresponding to each power-failure storage space to obtain an adjusted power-failure storage space, and determines an adjusted storage channel corresponding to the adjusted power-failure storage space;

[0035] Then, storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel includes:

[0036] The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0037] The beneficial effects of this embodiment are as follows: the main control chip can adjust the power-off storage space corresponding to the data to be stored according to the data volume of each data type to be stored and the capacity corresponding to each power-off storage space, and obtain the adjusted storage channel corresponding to the adjusted power-off storage space to ensure that the data to be stored with a large amount of data can be stored in the corresponding power-off storage space in a segmented and parallel manner through multiple storage channels, thereby shortening the storage time of all the data to be stored.

[0038] In the preferred technical solution of the above power-off processing method, the following is also included:

[0039] The main control chip determines the total number of power-off storage spaces and the priority corresponding to the data to be stored of each data type;

[0040] The main control chip determines the number of power-failure storage spaces corresponding to the data to be stored according to the total number of the power-failure storage spaces and the priority corresponding to the data to be stored of each data type;

[0041] The main control chip adjusts the power-failure storage space corresponding to the data to be stored according to the number of the power-failure storage spaces to obtain an adjusted power-failure storage space, and determines an adjusted storage channel corresponding to the adjusted power-failure storage space;

[0042] Then, storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel includes:

[0043] The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0044] The beneficial effects of this embodiment are as follows: the main control chip can determine the number of power-off storage spaces corresponding to the data to be stored according to the total number of power-off storage spaces and the priority corresponding to the data to be stored of each data type, and adjust the power-off storage spaces corresponding to the data to be stored according to the number of power-off storage spaces, and obtain the adjusted storage channels corresponding to the adjusted power-off storage spaces to ensure that the data to be stored with higher priority can be segmented and paralleled through multiple storage channels and quickly stored in the power-off storage space, thereby avoiding the problem of power-off loss of the data to be stored with higher priority.

[0045] In the preferred technical solution of the above power-off processing method, the following is also included:

[0046] The main control chip determines the wear degree of each power-off storage space;

[0047] The main control chip adjusts the power-off storage space corresponding to the data to be stored according to the wear degree of each power-off storage space to obtain an adjusted power-off storage space, and determines an adjusted storage channel corresponding to the adjusted power-off storage space;

[0048] Then, storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel includes:

[0049] The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0050] The beneficial effects of this embodiment are as follows: the main control chip adjusts the storage channel and the power-off storage space according to the wear degree of the power-off storage space to ensure that the main control chip preferentially uses the power-off storage space with low wear degree to store the data to be stored, thereby improving the storage security of the data to be stored.

[0051] In a second aspect, an embodiment of the present application provides a power failure processing device, comprising:

[0052] A control module, configured to control the backup capacitor to supply power to the solid-state drive and obtain data to be stored in the volatile memory chip when detecting that the solid-state drive is in a power-off state; wherein the data to be stored includes data of multiple data types;

[0053] A processing module, configured to determine, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space;

[0054] The power-off storage space includes a portion of storage space in at least one non-volatile memory chip, and the power-off storage space is a single-layer unit type storage space.

[0055] The beneficial effects of this embodiment are as follows: On the one hand, this embodiment utilizes the fast data storage speed of the single-layer cell type storage space. When the solid-state drive is in a power-off state, the data to be stored in the volatile memory chip is stored in the single-layer cell type power-off storage space in the non-volatile memory chip, thereby improving the storage speed of the data to be stored, ensuring that the solid-state drive can store a large amount of data in the non-volatile memory chip within a limited storage time, and reducing the possibility that the solid-state drive cannot write all the data to be stored in the volatile memory chip to the non-volatile memory chip when the power is off, thereby causing the possibility of loss of the data to be stored. On the other hand, this embodiment can directly determine the corresponding power-off storage space based on the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space, avoiding the time-consuming search for available power-off storage space and improving the storage speed of the data to be stored.

[0056] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is specifically used to:

[0057] For each data type of data to be stored, the power-off storage space corresponding to the data to be stored is determined according to the data type of the data to be stored, and the storage channel corresponding to the corresponding power-off storage space is determined, and the data to be stored is stored in the corresponding power-off storage space through the corresponding storage channel.

[0058] The beneficial effects of this embodiment are as follows: the processing module can directly determine the corresponding power-off storage space according to the data type of the data to be stored, and determine the storage channel corresponding to the corresponding power-off storage space, and directly store the data to be stored in the corresponding power-off storage space through the corresponding storage channel, thereby avoiding time-consuming search for available power-off storage space and improving the storage speed of the data to be stored.

[0059] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is specifically used to:

[0060] Reading a first correspondence table and a second correspondence table stored in the volatile memory chip, or reading the first correspondence table and the second correspondence table stored in the non-volatile memory chip; wherein the first correspondence table is a correspondence table between data types and power-off storage spaces, and the second correspondence table is a correspondence table between power-off storage spaces and storage channels;

[0061] For each data type of data to be stored, the power-off storage space corresponding to the data to be stored is determined according to the data type of the data to be stored and the first correspondence table, and the storage channel corresponding to the corresponding power-off storage space is determined according to the corresponding power-off storage space and the second correspondence table, and the data to be stored is stored in the corresponding power-off storage space through the corresponding storage channel.

[0062] The beneficial effects of this embodiment are as follows: the first correspondence table between data types and power-off storage spaces and the second correspondence table between power-off storage spaces and storage channels can be stored in a volatile memory chip or a non-volatile memory chip. When the solid-state hard disk loses power, the processing module can directly read the first correspondence table and the second correspondence table to determine a power-off storage space suitable for storing data to be stored of each data type, as well as a storage channel leading to the power-off storage space, so that the main control chip can quickly store the data to be stored in the power-off storage space, thereby improving the storage speed of the data to be stored.

[0063] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is further used to:

[0064] For each data type of the data to be stored, after the data to be stored is stored in the corresponding power-off storage space through the corresponding storage channel, a power-off data completion flag corresponding to the data type of the data to be stored is generated, and the power-off data completion flag is stored in the power-off storage space;

[0065] When it is detected that the solid state drive is in a powered-on state and a power-off data storage completion mark is stored in the power-off storage space, the data to be stored in the power-off storage space is stored in the non-power-off storage space of the nonvolatile memory chip.

[0066] The beneficial effects of this embodiment are as follows: After the processing module stores the data to be stored in the corresponding power-failure storage space through the corresponding storage channel, it generates a power-failure data completion flag corresponding to the data type of the data to be stored, indicating that the data to be stored in the power-failure storage space has been completely stored. The processing module stores the power-failure data completion flag in the power-failure storage space, so that it can subsequently determine whether the data to be stored is completely stored in the power-failure storage space based directly on whether the power-failure data completion flag is stored in the power-failure storage space, thereby implementing the processing module's integrity verification of the stored data. In addition, after the processing module performs integrity verification on the data to be stored in the power-off storage space, the data to be stored that has successfully been verified is stored in the non-power-off storage space of the non-volatile memory chip. On the one hand, compared with other non-single-layer unit type storage spaces, the available capacity of the power-off storage space is a single-layer unit type storage space. Storing the data to be stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip can reduce the number of cells occupied by the data to be stored; on the other hand, storing the data to be stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip can subsequently perform data clearing processing on the power-off storage space, thereby providing available power-off storage space for the second power-off of the solid-state hard disk, and preventing insufficient power-off storage space during the second power-off.

[0067] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is specifically used to:

[0068] When it is detected that the solid state drive is in a powered-on state and a power-off data storage completion mark is stored in the power-off storage space, the data to be stored stored in the power-off storage space is stored in the volatile memory chip;

[0069] The data to be stored in the volatile memory chip is stored in the non-power-off storage space of the non-volatile memory chip.

[0070] The beneficial effects of this embodiment are as follows: when the processing module stores the data to be stored stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip, the data to be stored can be first stored in the volatile memory chip for management, and then the data to be stored in the volatile memory chip can be stored in the non-power-off storage space of the non-volatile memory chip. This allows the processing module to store the data to be stored stored in the volatile memory chip into the non-power-off storage space of the non-volatile memory chip when the amount of data to be stored in the volatile memory chip reaches a certain amount, thereby reducing the number of accesses to the non-volatile memory chip and extending the service life of the solid-state hard disk.

[0071] In the preferred technical solution of the above power failure processing device, the processing module is specifically used to:

[0072] When it is detected that the solid state drive is in a powered-on state and the power-off data storage completion mark is stored in the power-off storage space, the data to be stored in the power-off storage space is directly stored in the non-power-off storage space of the non-volatile memory chip.

[0073] The beneficial effect of this embodiment is that the processing module can directly store the data to be stored in the acquired power-off storage space into the non-power-off storage space of the non-volatile memory chip, thereby improving the data storage speed.

[0074] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is further used to:

[0075] The power-off storage space is formatted into the single-layer unit type storage space, so as to perform data clearing processing on the power-off storage space.

[0076] The beneficial effects of this embodiment are as follows: after the processing module stores the data to be stored in the power-off storage space into the non-power-off storage space, the power-off storage space can be formatted into a single-layer unit type storage space to perform data clearing processing on the power-off storage space, ensuring that when the solid-state hard disk loses power for the second time, the processing module does not need to spend time searching for available power-off storage space, and can directly store the data to be stored in the corresponding power-off storage space, thereby improving the data storage speed.

[0077] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is further used to:

[0078] Determine the amount of data to be stored for each data type and the capacity corresponding to each power-off storage space;

[0079] Adjusting the power-failure storage space corresponding to the data to be stored according to the amount of the data to be stored of each data type and the capacity corresponding to each power-failure storage space to obtain an adjusted power-failure storage space, and determining an adjusted storage channel corresponding to the adjusted power-failure storage space;

[0080] The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0081] The beneficial effects of this embodiment are as follows: the processing module can adjust the power-off storage space corresponding to the data to be stored according to the data volume of each data type and the capacity corresponding to each power-off storage space, and obtain the adjusted storage channel corresponding to the adjusted power-off storage space to ensure that the data to be stored with a large amount of data can be stored in the corresponding power-off storage space in a segmented and parallel manner through multiple storage channels, thereby shortening the storage time of all the data to be stored.

[0082] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is further used to:

[0083] Determine the total number of power-off storage spaces and the priority corresponding to the data to be stored for each data type;

[0084] Determining the number of power-failure storage spaces corresponding to the data to be stored according to the total number of the power-failure storage spaces and the priority corresponding to the data to be stored of each data type;

[0085] adjusting the power-failure storage space corresponding to the data to be stored according to the number of the power-failure storage spaces to obtain an adjusted power-failure storage space, and determining an adjusted storage channel corresponding to the adjusted power-failure storage space;

[0086] The data to be stored is stored in the adjusted power-off storage space through the adjusted storage channel.

[0087] The beneficial effects of this embodiment are as follows: the processing module can determine the number of power-failure storage spaces corresponding to the data to be stored based on the total number of power-failure storage spaces and the priority corresponding to the data to be stored of each data type, and adjust the power-failure storage spaces corresponding to the data to be stored based on the number of power-failure storage spaces, and obtain the adjusted storage channels corresponding to the adjusted power-failure storage spaces to ensure that the data to be stored with a higher priority can be segmented and paralleled through multiple storage channels and quickly stored in the power-failure storage space, thereby avoiding the problem of the data to be stored with a higher priority being lost due to power failure.

[0088] In the preferred technical solution of the above-mentioned power failure processing device, the processing module is further used to:

[0089] Determine the wear level of each power-off storage space;

[0090] adjusting the power-failure storage space corresponding to the data to be stored according to the wear degree of each power-failure storage space to obtain an adjusted power-failure storage space, and determining an adjusted storage channel corresponding to the adjusted power-failure storage space;

[0091] The data to be stored is stored in the adjusted power-off storage space through the adjusted storage channel.

[0092] The beneficial effects of this embodiment are as follows: the processing module adjusts the storage channel and the power-off storage space according to the wear degree of the power-off storage space to ensure that the main control chip preferentially uses the power-off storage space with low wear degree to store the data to be stored, thereby improving the storage security of the data to be stored.

[0093] In a third aspect, an embodiment of the present application provides a solid-state drive, comprising:

[0094] A main control chip, and a backup capacitor, a volatile memory chip and at least one non-volatile memory chip electrically connected to the main control chip; wherein,

[0095] The main control chip is used to control the backup capacitor to supply power to the solid-state hard disk and obtain the data to be stored in the volatile memory chip when detecting that the solid-state hard disk is in a power-off state; wherein the data to be stored includes data of multiple data types to be stored;

[0096] The main control chip is further configured to determine, for each data type of the data to be stored, a corresponding power-off storage space for the data to be stored according to the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space through the corresponding storage channel;

[0097] The power-off storage space includes a portion of storage space in at least one non-volatile memory chip, and the power-off storage space is a single-layer unit type storage space.

[0098] The beneficial effects of this embodiment are as follows: On the one hand, this embodiment utilizes the fast data storage speed of the single-layer cell type storage space. When the solid-state drive is in a power-off state, the data to be stored in the volatile memory chip is stored in the single-layer cell type power-off storage space in the non-volatile memory chip, thereby improving the storage speed of the data to be stored, ensuring that the solid-state drive can store a large amount of data in the non-volatile memory chip within a limited storage time, and reducing the possibility that the solid-state drive cannot write all the data to be stored in the volatile memory chip to the non-volatile memory chip when the power is off, thereby causing the possibility of loss of the data to be stored. On the other hand, this embodiment can directly determine the corresponding power-off storage space based on the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space, avoiding the time-consuming search for available power-off storage space and improving the storage speed of the data to be stored.

[0099] In a fourth aspect, an embodiment of the present application provides a computing device, comprising a motherboard and the solid-state drive described in the third aspect;

[0100] Wherein, the mainboard includes a mainboard interface, and the solid-state hard disk includes a hard disk connector;

[0101] The mainboard is connected to the solid state hard disk through the mainboard interface and the hard disk connector.

[0102] The beneficial effects of this embodiment are as follows: On the one hand, this embodiment utilizes the fast data storage speed of the single-layer cell type storage space. When the solid-state drive is in a power-off state, the data to be stored in the volatile memory chip is stored in the single-layer cell type power-off storage space in the non-volatile memory chip, thereby improving the storage speed of the data to be stored, ensuring that the solid-state drive can store a large amount of data in the non-volatile memory chip within a limited storage time, and reducing the possibility that the solid-state drive cannot write all the data to be stored in the volatile memory chip to the non-volatile memory chip when the power is off, thereby causing the possibility of loss of the data to be stored. On the other hand, this embodiment can directly determine the corresponding power-off storage space based on the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space, avoiding the time-consuming search for available power-off storage space and improving the storage speed of the data to be stored.

[0103] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer execution instructions, and when the computer execution instructions are executed by a processor, they are used to implement the power-off processing method of the solid-state hard disk described in the first aspect.

[0104] The beneficial effects of this embodiment are as follows: On the one hand, this embodiment utilizes the fast data storage speed of the single-layer cell type storage space. When the solid-state drive is in a power-off state, the data to be stored in the volatile memory chip is stored in the single-layer cell type power-off storage space in the non-volatile memory chip, thereby improving the storage speed of the data to be stored, ensuring that the solid-state drive can store a large amount of data in the non-volatile memory chip within a limited storage time, and reducing the possibility that the solid-state drive cannot write all the data to be stored in the volatile memory chip to the non-volatile memory chip when the power is off, thereby causing the possibility of loss of the data to be stored. On the other hand, this embodiment can directly determine the corresponding power-off storage space based on the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space, avoiding the time-consuming search for available power-off storage space and improving the storage speed of the data to be stored. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0106] Figure 1 A structural diagram of a solid-state hard disk provided in an embodiment of the present application;

[0107] Figure 2 A flowchart of a first embodiment of a power failure processing method provided in an embodiment of the present application;

[0108] Figure 3 A flowchart of a second embodiment of a power failure processing method provided in an embodiment of the present application;

[0109] Figure 4 A flowchart of a third embodiment of a power failure processing method provided in an embodiment of the present application;

[0110] Figure 5 A flowchart of a fourth embodiment of a power failure processing method provided in an embodiment of the present application;

[0111] Figure 6 A flowchart of a fifth embodiment of a power failure processing method provided in an embodiment of the present application;

[0112] Figure 7 A schematic structural diagram of an embodiment of a power failure processing device provided in an embodiment of the present application;

[0113] Figure 8 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0114] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments made by ordinary technicians in this field based on the inspiration of these embodiments fall within the scope of protection of this application.

[0115] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0116] Glossary:

[0117] Solid State Disk (SSD): Also known as solid-state drive, it is a hard disk made of an array of solid-state electronic memory chips.

[0118] Memory chips: These are general-purpose integrated circuits, representing the specific application of the embedded system-on-chip concept in the storage industry. By embedding software within a single chip, they achieve multifunctionality and high performance, supporting multiple protocols, diverse hardware, and diverse applications. The most commonly used memory chips in the market include volatile memory chips (such as dynamic random access memory (DRAM)) and non-volatile memory chips (such as NAND Flash).

[0119] Storage channel: The link path between the main control chip and the non-volatile memory chip, used to issue IO read and write operations and control commands to the non-volatile memory chip. Each storage channel can be connected to at least one non-volatile memory chip.

[0120] Flash Translation Layer (FTL) mapping table: This table maps the logical block addresses (LBAs) maintained within the SSD (user-visible addresses) to the physical block addresses (PBAs) within the SSD's internal flash memory allocation. This table controls the physical location of stored data.

[0121] In the related art, the backup capacitor built into the SSD can briefly power the SSD when the SSD is powered off, allowing the main control chip to write data from the volatile memory chip to the non-volatile memory chip. However, the power supply time of the SSD backup capacitor is relatively short. As a result, when the SSD loses power, it is unable to write all the data to be stored in the volatile memory chip to the non-volatile memory chip, which in turn causes data loss.

[0122] Based on the above technical problems, an embodiment of the present application proposes a method for increasing the speed at which a main control chip stores data to be stored in a non-volatile memory chip when a solid-state drive loses power.

[0123] The following is a detailed description of the power failure processing solution for the solid-state drive according to the embodiment of the present application.

[0124] For example, Figure 1 A structural diagram of a solid state hard disk provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the solid state drive 10 may include: a main control chip 101, a volatile memory chip 102, at least one non-volatile memory chip and a backup capacitor 103. For example, Figure 1 Four non-volatile memory chips are shown, namely non-volatile memory chip 104, non-volatile memory chip 105, non-volatile memory chip 106 and non-volatile memory chip 107. Among them, the main control chip 101 is connected to the non-volatile memory chip 104 through the first storage channel, connected to the non-volatile memory chip 105 through the second storage channel, connected to the non-volatile memory chip 106 through the third storage channel, and connected to the non-volatile memory chip 107 through the third storage channel. It should be noted that one storage channel can correspond to at least one non-volatile memory chip. It should also be noted that the main control chip 101 can be connected to the volatile memory chip 102 through the volatile storage channel, and the main control chip 101 can also be electrically connected to the backup capacitor 103.

[0125] In addition, the solid state drive 10 may further include a hard disk connector ( Figure 1 (not shown) so that the solid state drive 10 can be connected to a computing device via a hard drive connector. The computing device can be a terminal device (such as a mobile phone, a computer), a server, or other equipment.

[0126] It should be noted that the main control chip 101 serves as the control unit of the solid-state drive 10, coordinating the operation and data storage of the entire solid-state drive 10. For example, the data to be stored in the volatile memory chip 102 needs to be stored in the non-volatile memory chip via the main control chip 101. In other words, the main control chip 101 can obtain the data to be stored in the volatile memory chip 102 and store the data to be stored in the non-volatile memory chip. It should also be noted that the main control chip 101 can be a system-level chip - a system on chip (SoC), the main control chip 101 can also be a chip-level chip - a micro control unit (MCU), and the main control chip 101 can also be other chips with control and processing capabilities.

[0127] It should also be noted that the backup capacitor 103 is a backup power supply device provided on the solid state drive 10. For example, the backup capacitor 103 can be a backup battery unit (BBU) or an uninterruptible power supply (UPS).

[0128] Volatile memory chip 102 serves as a temporary storage unit for SSD 10, and has the characteristic of losing data upon power failure. Volatile memory chip 102 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), or other chips that require power to store data.

[0129] The non-volatile memory chip, as a storage unit for permanently storing data in the solid-state drive 10, has the characteristic of retaining data even when the power is off. The non-volatile memory chip can be read-only memory (ROM), programmable read-only memory (PROM), electrically alterable read-only memory (EAROM), flash memory, or other chips that can store data without power.

[0130] It should be noted that Figure 1 This is only a structural diagram of a solid state drive provided in the embodiment of the present application. Figure 1The actual form of the various devices included in the Figure 1 The interaction mode between devices is limited and can be set according to actual needs in the application of the solution.

[0131] The technical solutions of the embodiments of the present application are described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0132] Figure 2 This is a flow chart of a power failure processing method according to an embodiment of the present application. Figure 2 , the method specifically comprises the following steps:

[0133] S201: When the main control chip detects that the solid state drive is in a power-off state, it controls the backup capacitor to supply power to the solid state drive and obtains the data to be stored in the volatile memory chip.

[0134] In this embodiment, when the solid-state drive is plugged into the motherboard of a computing device via the hard drive connector, the computing device can provide power to the solid-state drive. The main control chip can control the computing device to act as the main power supply device, so that the computing device provides power to the entire solid-state drive. In other words, it controls the computing device to provide power to the main control chip, volatile memory chip, and non-volatile memory chip.

[0135] The main control chip can detect whether the solid-state hard drive is in a power-off state, that is, detect whether the computing device is currently acting as the main power supply device, and supplies power to the entire solid-state hard drive through the hard drive connector. In one implementation, the main control chip can determine whether the solid-state hard drive is in a power-off state based on whether the power supply current value of the computing device used to power the solid-state hard drive is lower than a preset current value. In one implementation, the main control chip can determine whether the solid-state hard drive is in a power-off state based on whether the power supply voltage value of the computing device used to power the solid-state hard drive is lower than a preset voltage value. In one implementation, the main control chip can determine whether the solid-state hard drive is in a power-off state based on whether the power supply frequency of the computing device used to power the solid-state hard drive is lower than a preset power supply frequency.

[0136] When the main control chip detects that the solid-state drive is in a power-off state, that is, when it determines that the computing device is not currently acting as the main power supply device to power the entire solid-state drive, it controls the backup power capacitor to power the entire solid-state drive. On the one hand, the main control chip controls the backup power capacitor to power the solid-state drive, which enables the main control chip to execute the power-off processing method for the solid-state drive. On the other hand, because the volatile memory chip is a volatile medium and has the characteristic of losing data when the power is lost, the main control chip controls the backup power capacitor to power the solid-state drive, which can prevent the volatile memory chip from losing the data to be stored in the volatile memory chip due to power failure.

[0137] In addition, when the main control chip detects that the solid-state drive is in a power-off state, it can also obtain the data to be stored in the volatile memory chip. The data to be stored includes data of various data types. For example, the data to be stored includes data of user data type, data of metadata type, and data of FTL type to be flashed.

[0138] S202: The main control chip determines, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and stores the data to be stored in the corresponding power-off storage space.

[0139] In this embodiment, the solid-state drive includes multiple storage channels (CHs), each CH corresponds to at least one chip enable (CE), that is, each storage channel corresponds to at least one non-volatile memory chip. Each CE includes multiple cores (DIEs), each DIE includes multiple planes (Planes), each Plane includes multiple blocks (Blocks), where a Block is the smallest erase unit. Each Block includes multiple pages (Pages), where a Page is the smallest read / write unit. Each Page includes multiple cells (Cells), where a Cell is the smallest data storage unit.

[0140] The cells in non-volatile memory chips can be divided into different types according to the number of bits stored, namely single-level cell (SLC) type, double-level cell (MLC) type and triple-level cell (TLC) type, etc. In the SLC type storage space, each cell stores 1 bit of data; in the MLC type storage space, each cell stores 2 bits of data; in the TLC type storage space, each cell stores 3 bits of data. The more bits stored in a cell at one time, the greater the capacity of the cell. In addition, it should be noted that the write latency of the SLC type storage space is 200-300 microseconds, the write latency of the MLC type storage space is 600-900 microseconds, and the write latency of the TLC type storage space is 900-1350 microseconds. In other words, the SLC type storage space has the fastest storage speed.

[0141] The main control chip can format part of the storage space in at least one non-volatile memory chip in the solid-state drive into a single-layer unit type storage space and determine the storage space as a power-off storage space. The power-off storage space includes power-off storage space corresponding to data to be stored of multiple data types.

[0142] In one implementation, the main control chip can format part of the storage space in at least one non-volatile memory chip in the solid-state drive as a single-layer unit type storage space based on the initialization instruction sent by the computing device when the solid-state drive is initialized, and determine the storage space as the power-off storage space. It should be noted that the power-off storage space can be part of the storage space in a non-volatile memory chip under a storage channel, or all of the storage space in a non-volatile memory chip under a storage channel; it can be part of the storage space in multiple non-volatile memory chips under a storage channel; it can be all of the storage space in multiple non-volatile memory chips under a storage channel; it can also be part or all of the storage space in one or more non-volatile memory chips corresponding to multiple storage channels. This embodiment is not limited to this. It should also be noted that in one implementation, the power-off storage space can also be part or all of the storage space in at least one higher-performance single storage particle (non-volatile memory chip (such as Optane chip)) external to the solid-state drive.

[0143] In another implementation, the main control chip can format part of the storage space in at least one non-volatile memory chip in the solid-state drive into a single-layer unit type storage space based on the initialization instruction sent by the computing device at any time when the solid-state drive is not in a power-off state, and determine the storage space as a power-off storage space.

[0144] In another implementation, when the solid-state hard disk is in a power-off state, the main control chip can format part of the storage space in at least one non-volatile memory chip in the solid-state hard disk into a single-layer unit type storage space based on the information that the capacity of the power-off storage space cannot meet the current storage needs, and determine the storage space as the power-off storage space.

[0145] Specifically, the data to be stored in the non-volatile memory chip is stored in each cell of each non-volatile memory chip in the form of electric charge. When the main control chip formats part of the storage space in the non-volatile memory chip into a single-layer cell type storage space, it formats part of the storage space in at least one non-volatile memory chip in the solid-state drive into a single-layer cell type by modifying the number of threshold voltages of the cell storage data corresponding to part of the storage space in at least one non-volatile memory chip. For example, when the number of threshold voltages is 1, the storage space is a single-layer cell type, when the number of threshold voltages is 3, the storage space is a double-layer cell type, and when the number of threshold voltages is 7, the storage space is a triple-layer cell type.

[0146] In this embodiment, the main control chip can determine the corresponding power-failure storage space for each data type of data to be stored based on the data type of the data to be stored, and directly store the data to be stored in the corresponding power-failure storage space. Specifically, since the main control chip is connected to the non-volatile memory chip via a storage channel, that is, the main control chip stores the data to be stored in the power-failure storage space via the storage channel, when determining the power-failure storage space corresponding to the data to be stored, the main control chip can determine the storage channel corresponding to the power-failure storage space, and store the data to be stored in the corresponding power-failure storage space via the corresponding storage channel.

[0147] It should be noted that the volatile memory chip can store a first correspondence table between the data type of the data to be stored and the power-off storage space, and a second correspondence table between the power-off storage space and the storage channel; the non-volatile memory chip can also store a first correspondence table between the data type of the data to be stored and the power-off storage space, and a second correspondence table between the power-off storage space and the storage channel. After controlling the backup capacitor to power the solid-state hard disk, the main control chip can read the above two correspondence tables stored in the volatile memory chip, or read the above two correspondence tables stored in the non-volatile memory chip, thereby determining the power-off storage space corresponding to the data to be stored based on the above first correspondence table and the data type of the data to be stored, and determining the storage channel corresponding to the power-off storage space based on the corresponding power-off storage space and the second correspondence table, so that the data to be stored can be stored in the corresponding power-off storage space through the corresponding storage channel.

[0148] It should also be noted that when the main control chip stores the data to be stored of each data type into the corresponding power-off storage space through the corresponding storage channel, the data are stored in parallel. That is, the main control chip stores the data to be stored of multiple data types into the corresponding power-off storage space through the corresponding storage channel at the same time. For example, after determining that the data to be stored includes data to be stored of the user data type and data to be stored of the metadata type, the main control chip can determine, based on the first correspondence table and the second correspondence table, that the power-off storage space corresponding to the data to be stored of the user data type is the first power-off storage space, and that the storage channel corresponding to the first power-off storage space is the first storage channel; the main control chip can determine, based on the first correspondence table and the second correspondence table, that the power-off storage space corresponding to the data to be stored of the metadata type is the second power-off storage space and the third power-off storage space, and that the storage channels corresponding to the second power-off storage space and the third power-off storage space are the second storage channel and the third storage channel, wherein the second power-off storage space corresponds to the second storage channel, and the third power-off storage space corresponds to the third storage channel. The main control chip can divide the metadata type data to be stored to obtain first metadata type data to be stored and second metadata type data to be stored. The main control chip can store the user data type data to be stored in the first power-off storage space via the first storage channel, and simultaneously store the first metadata type data to be stored in the second power-off storage space via the second storage channel, and simultaneously store the second metadata type data to be stored in the third power-off storage space via the third storage channel.

[0149] It should also be noted that when the main control chip formats part of the storage space in at least one non-volatile memory chip in the solid-state hard disk into a single-layer unit type storage space and determines the storage space as a power-off storage space, that is, when the main control chip determines the power-off storage space, it can modify the flash memory space allocation range in the flash memory translation layer mapping table according to the physical location of the power-off storage space. The main control chip can store the data to be stored obtained from the volatile memory chip through the corresponding storage channel to the physical location corresponding to the power-off storage space according to the flash memory space allocation range in the modified flash memory translation layer mapping table.

[0150] In this embodiment, when the main control chip detects that the solid-state drive is in a power-off state, it controls the backup capacitor to supply power to the solid-state drive. Taking advantage of the high data storage speed of the single-layer cell type storage space, the main control chip stores the data to be stored in the volatile memory chip into the single-layer cell type power-off storage space in the non-volatile memory chip, thereby improving the storage speed of the data to be stored. This ensures that the solid-state drive can store a large amount of data in the non-volatile memory chip within a limited storage time, thereby reducing the possibility of data loss due to the inability to write all the data to be stored in the volatile memory chip to the non-volatile memory chip during a power-off state. In addition, this embodiment can directly determine the power-off storage space corresponding to the data to be stored based on the data type of the data to be stored, determine the storage channel corresponding to the power-off storage space, and store the data to be stored in the corresponding power-off storage space through the corresponding storage channel, thereby avoiding the need to search for available power-off storage space and improving the storage speed of the data to be stored.

[0151] Based on the above-mentioned method embodiment 1, the following method embodiment 2 describes in detail the process of the main control chip storing the data to be stored in the power-off storage space to the non-power-off storage space of the non-volatile memory chip after the main control chip stores the data to be stored in the power-off storage space.

[0152] Figure 3 This is a flow chart of a second embodiment of a power-off protection method provided in an embodiment of the present application, which specifically includes the following steps:

[0153] S301: The main control chip generates a power-off data completion flag corresponding to the data type of the data to be stored for each data type, after storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel, and stores the power-off data completion flag in the power-off storage space.

[0154] In this embodiment, the main control chip can generate a power-off data completion flag corresponding to the data type of the data to be stored, and store the power-off data completion flag in the power-off storage space after storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel for each data type to be stored.

[0155] For example, the main control chip can determine, for data to be stored of a user data type, that the power-failure storage space corresponding to the data to be stored of that type is the first power-failure storage space, and that the storage channel corresponding to the first power-failure storage space is the first storage channel. After storing the data to be stored of the user data type in the first power-failure storage space through the first storage channel, the main control chip can generate a first power-failure data completion flag corresponding to the user data type, and store the first power-failure data completion flag in the first power-failure storage space.

[0156] For another example, the main control chip can determine that the power-failure storage space corresponding to metadata-type data to be stored is the second power-failure storage space and the third power-failure storage space, and determine that the storage channels corresponding to the second power-failure storage space and the third power-failure storage space are the second storage channel and the third storage channel. The second storage channel is the storage channel leading from the main control chip to the second power-failure storage space, and the third storage channel is the storage channel leading from the main control chip to the third power-failure storage space. The main control chip can segment the metadata-type data to be stored, obtaining first metadata-type data to be stored and second metadata-type data to be stored. After storing the first metadata-type data to be stored in the second power-failure storage space via the second channel, the main control chip can generate a second power-failure data completion flag corresponding to the metadata type and store the second power-failure data completion flag in the second power-failure storage space. After storing the second metadata-type data to be stored in the third power-failure storage space via the third channel, the main control chip can generate a third power-failure data completion flag corresponding to the metadata type and store the third power-failure data completion flag in the third power-failure storage space.

[0157] S302: When the main control chip detects that the solid state drive is powered on and the power-off data storage in the power-off storage space is marked as complete, the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip.

[0158] In this embodiment, when the main control chip detects that the solid-state hard disk is in a powered-on state, that is, when the main control chip detects that the solid-state hard disk is not in a powered-off state, it can detect whether a power-off data completion mark is stored in the power-off storage space. When the main control chip detects that a power-off data completion mark is stored in the power-off storage space, it determines that the data to be stored in the power-off storage space is complete, and the main control chip can store the data to be stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip. In addition, when the main control chip detects that the power-off data completion mark is not stored in the power-off storage space, it determines that the data to be stored in the power-off storage space is not complete, and at this time the main control chip can repair the data to be stored in the power-off storage space.

[0159] Specifically, in the process of the main control chip storing the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip, one implementation method is that the main control chip stores the data to be stored in the power-off storage space into the volatile memory chip, so that the volatile memory chip organizes the data to be stored, and the main control chip stores the data to be stored in the volatile memory chip into the non-power-off storage space of the non-volatile memory chip. Another implementation method is that the main control chip directly stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip. It should be noted that the non-power-off storage space of the non-volatile memory chip can be a single-layer unit type storage space, a double-layer unit type storage space, or a triple-layer unit type storage space, and this embodiment does not limit this.

[0160] It should also be noted that after the main control chip stores the data to be stored in all the power-off storage spaces into the non-power-off storage space of the non-volatile memory chip, it can use the whole block (Block) erasing method to format the power-off storage space into a single-layer unit type storage space (free and available power-off storage space) to clear data in the power-off storage space, so as to ensure that when the solid-state hard disk loses power for the second time, the main control chip does not need to waste time searching for available power-off storage space, and directly stores the data to be stored in the corresponding power-off storage space.

[0161] In this embodiment, after the main control chip stores the data to be stored in the corresponding power-down storage space through the corresponding storage channel, it generates a power-down data completion flag corresponding to the type of data to be stored, indicating that the data to be stored in the power-down storage space has been completely stored. The main control chip stores the power-down data completion flag in the power-down storage space so that it can subsequently determine whether the data to be stored is completely stored in the power-down storage space based directly on whether the power-down data completion flag is stored in the power-down storage space, thereby implementing integrity verification of the data to be stored by the main control chip. In addition, after the main control chip performs integrity verification on the data to be stored in the power-off storage space, the data to be stored that has passed the verification is stored in the non-power-off storage space of the non-volatile memory chip. On the one hand, compared with other non-single-layer unit type storage spaces, the available capacity of the power-off storage space is a single-layer unit type storage space. Storing the data to be stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip can reduce the number of cells occupied by the data to be stored; on the other hand, storing the data to be stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip can subsequently use the whole-block erase method to clear data in the power-off storage space to obtain idle and available power-off storage space, thereby providing available power-off storage space for the second power-off of the solid-state drive, and preventing insufficient power-off storage space during the second power-off.

[0162] Based on the above-mentioned method embodiment 1, the following method embodiment 3 describes in detail a specific implementation process of determining the storage channel and power-off storage space for the main control chip, and storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

[0163] Figure 4 This is a flow chart of a third embodiment of a power-off protection method provided in an embodiment of the present application. The method specifically includes the following steps:

[0164] S401: The main control chip determines, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored and determines a storage channel corresponding to the corresponding power-off storage space according to the data type of the data to be stored.

[0165] In this embodiment, for each data type of the data to be stored, the main control chip can determine the power-off storage space corresponding to the data to be stored and determine the storage channel leading to the power-off storage space according to the data type of the data to be stored.

[0166] For example, the main control chip can determine that the power-failure storage space corresponding to the user data type is the first power-failure storage space, and the storage channel corresponding to the first power-failure storage space is the first storage channel, where the first storage channel is the storage channel from the main control chip to the first power-failure storage space. The main control chip can determine that the power-failure storage space corresponding to the metadata type is the second power-failure storage space and the third power-failure storage space, and the storage channels corresponding to the second power-failure storage space and the third power-failure storage space are the second storage channel and the third storage channel, where the second storage channel is the storage channel from the main control chip to the second power-failure storage space, and the third storage channel is the storage channel from the main control chip to the third power-failure storage space.

[0167] S402: The main control chip determines the amount of data to be stored of each data type and the capacity corresponding to each power-off storage space.

[0168] In this embodiment, the main control chip can obtain the data volume of each data type to be stored and the capacity corresponding to each power-off storage space.

[0169] For example, when the main control chip determines that the data to be stored in the volatile memory chip includes data to be stored of the user data type and data to be stored of the metadata type, it can determine that the data size of the user data type to be stored is 3MB, and the data size of the metadata type to be stored is 1MB. The main control chip can also determine that the power-off storage space corresponding to the user data type is the first power-off storage space, and the corresponding capacity of the first power-off storage space is 2MB. The main control chip can also determine that the power-off storage space corresponding to the metadata type is the second power-off storage space and the third power-off storage space, and determine that the corresponding capacity of the second power-off storage space and the third power-off storage space is 2MB.

[0170] S403: The main control chip adjusts the power-off storage space corresponding to the data to be stored according to the amount of data to be stored of each data type and the capacity corresponding to each power-off storage space to obtain an adjusted power-off storage space, and determines an adjusted storage channel corresponding to the adjusted power-off storage space.

[0171] In this embodiment, the main control chip can adjust the power-off storage space corresponding to the data to be stored according to the data amount of each data type to be stored and the capacity corresponding to each power-off storage space to obtain the adjusted power-off storage space and determine the adjusted storage channel corresponding to the adjusted power-off storage space.

[0172] For example, when the main control chip determines that the first power-off storage space (with a capacity of 2MB) cannot store the data to be stored of the user data type (data volume of 3MB), it can adjust the power-off storage space corresponding to the data to be stored, determine that the power-off storage space corresponding to the data to be stored of the user data type is the first power-off storage space (with a capacity of 2MB) and the second power-off storage space (with a capacity of 2MB), and determine that the power-off storage space corresponding to the data to be stored of the metadata type is the third power-off storage space (with a capacity of 2MB). Since the first storage channel is the storage channel of the main control chip leading to the first power-off storage space, the second storage channel is the storage channel of the main control chip leading to the second power-off storage space, and the third storage channel is the storage channel of the main control chip leading to the third power-off storage space, the main control chip determines that the storage channels for transmitting the data to be stored of the user data type are the first storage channel (corresponding to the first power-off storage space) and the second storage channel (corresponding to the second power-off storage space), and the storage channel for transmitting the data to be stored of the metadata type is the third storage channel (corresponding to the third power-off storage space).

[0173] S404: The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0174] In this embodiment, after determining the adjusted storage channel and the adjusted power-off storage space, the main control chip can store the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0175] It should be noted that after determining the adjusted power-off storage space, the main control chip can update the first correspondence table (the correspondence table between the type of data to be stored and the power-off storage space) stored in the volatile memory chip and at least one non-volatile memory chip according to the adjusted power-off storage space, so that when the solid-state hard disk suffers a second power outage, the main control chip can determine the power-off storage space corresponding to the type of data to be stored according to the updated correspondence table.

[0176] In this embodiment, the main control chip can adjust the power-off storage space corresponding to the data to be stored according to the data volume of each data type to be stored and the capacity corresponding to each power-off storage space to obtain the adjusted power-off storage space, and determine the adjusted storage channel corresponding to the adjusted power-off storage space to ensure that data with a large amount of data to be stored can be stored in parallel in multiple corresponding power-off storage spaces through multiple storage channels, shortening the time for storing data with a large amount of data to be stored in the non-volatile memory chip, and further ensuring that all data to be stored can be completely stored in the non-volatile memory chip within a limited time.

[0177] Based on the above-mentioned method embodiment 1, another specific implementation process of determining the storage channel and power-off storage space for the main control chip and storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel is described in detail through method embodiment 4.

[0178] Figure 5 This is a flow chart of a fourth embodiment of a power-off protection method provided in an embodiment of the present application, which specifically includes the following steps:

[0179] S501: The main control chip determines, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored and determines a storage channel corresponding to the corresponding power-off storage space according to the data type of the data to be stored.

[0180] In this embodiment, the main control chip determines the power-off storage space corresponding to each data type of the data to be stored and determines the storage channel corresponding to the power-off storage space according to the data type of the data to be stored.

[0181] For example, the main control chip determines that the power-off storage space corresponding to the user data type to be stored is the first power-off storage space and the second power-off storage space based on a first correspondence table between the data type to be stored and the power-off storage space, and determines that the storage channel corresponding to the first power-off storage space is the first storage channel, and the storage channel corresponding to the second power-off storage space is the second storage channel based on a second correspondence table between the power-off storage space and the storage channel. In other words, the main control chip can determine that the storage channels corresponding to the user data type to be stored are the first storage channel and the second storage channel. The main control chip determines that the power-off storage space corresponding to the metadata type to be stored is the third power-off storage space, and determines that the storage channel corresponding to the third power-off storage space is the third storage channel. In other words, the main control chip can determine that the storage channel corresponding to the metadata type to be stored is the third storage channel.

[0182] S502: The main control chip determines the total number of power-off storage spaces and the priority corresponding to the data to be stored of each data type.

[0183] In this embodiment, the main control chip can obtain the total number of power-off storage spaces and the priority of the to-be-stored data of each data type.

[0184] For example, the total number of power-off storage spaces that can be acquired by the main control chip is 3, the priority of the to-be-stored data of the user data type is low, and the priority of the to-be-stored data of the metadata type is high.

[0185] S503: The main control chip determines the number of power-failure storage spaces corresponding to the data to be stored according to the total number of power-failure storage spaces and the priority corresponding to the data to be stored of each data type.

[0186] In this embodiment, the volatile memory chip and at least one non-volatile memory chip may store a table of correspondences between priorities, the total number of power-failure storage spaces, and the number of power-failure storage spaces. The main control chip may determine the number of power-failure storage spaces corresponding to the data to be stored for each data type based on the table of correspondences between priorities, the total number of power-failure storage spaces, and the number of power-failure storage spaces corresponding to each data type.

[0187] For example, when the main control chip determines that the priority of the to-be-stored data of the user data type is low and the total number of power-failure storage spaces is 3, based on the above correspondence table, the main control chip can determine that the number of power-failure storage spaces corresponding to the to-be-stored data of the user data type is 1. When the main control chip determines that the priority of the to-be-stored data of the metadata type is high and the total number of power-failure storage spaces is 3, based on the above correspondence table, the main control chip can determine that the number of power-failure storage spaces corresponding to the to-be-stored data of the metadata type is 2.

[0188] S504: The main control chip adjusts the power-failure storage space corresponding to the data to be stored according to the number of the power-failure storage spaces to obtain an adjusted power-failure storage space, and determines an adjusted storage channel corresponding to the adjusted power-failure storage space.

[0189] In this embodiment, the main control chip can adjust the power-off storage space corresponding to the data to be stored according to the number of power-off storage spaces to obtain the adjusted power-off storage space and determine the adjusted storage channel corresponding to the adjusted power-off storage space.

[0190] For example, the main control chip can determine that the number of power-off storage spaces corresponding to the data to be stored of the user data type is 1, and determine that the number of power-off storage spaces corresponding to the data to be stored of the metadata type is 2. The main control chip can adjust the power-off storage space corresponding to the data to be stored of the user data type from the first power-off storage space and the second power-off storage space to the first power-off storage space according to the number of power-off storage spaces. After adjusting the power-off storage space, the main control chip can adjust the storage channel for transmitting the data to be stored of the user data type from the first storage channel and the second storage channel to the first storage channel. The main control chip adjusts the power-off storage space corresponding to the data to be stored of the metadata type from the third power-off storage space to the second power-off storage space and the third power-off storage space, and further adjusts the storage channel for transmitting the data to be stored of the metadata type from the third storage channel to the second storage channel and the third storage channel.

[0191] S505: The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0192] In this embodiment, after determining the adjusted storage channel and the adjusted power-off storage space, the main control chip can store the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0193] It should be noted that after determining the adjusted power-off storage space, the main control chip can update the first correspondence table stored in the volatile memory chip and at least one non-volatile memory chip based on the information, so that when the solid-state hard disk suffers a second power outage, the main control chip can determine the power-off storage space corresponding to the data type of the data to be stored based on the updated first correspondence table.

[0194] In this embodiment, the main control chip can determine the number of power-off storage spaces corresponding to the data to be stored based on the total number of power-off storage spaces and the priority corresponding to the data to be stored of each data type, and adjust the power-off storage spaces corresponding to the data to be stored according to the number of power-off storage spaces, and then adjust the storage channels to ensure that the data to be stored with higher priority can pass through multiple storage channels in parallel and be quickly stored in the power-off storage space, thereby avoiding the problem of power-off loss of the data to be stored with higher priority.

[0195] Based on the above-mentioned method embodiment 1, the following method embodiment 5 will describe in detail another specific implementation process of determining the storage channel and power-off storage space for the main control chip, and storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

[0196] Figure 6 This is a flow chart of a fifth embodiment of a power-off protection method provided in an embodiment of the present application, which specifically includes the following steps:

[0197] S601: The main control chip determines, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored and determines a storage channel corresponding to the corresponding power-off storage space according to the data type of the data to be stored.

[0198] S602: The main control chip determines the wear degree of each power-off storage space.

[0199] In this embodiment, the main control chip can determine the wear degree of each power-off storage space.

[0200] For example, the main control chip may determine that the wear degree of the first power-off storage space is 23, the wear degree of the second power-off storage space is 56, the wear degree of the third power-off storage space is 76, and the wear degree of the fourth power-off storage space is 12.

[0201] S603: The main control chip adjusts the power-off storage space corresponding to the data to be stored according to the wear degree of each power-off storage space to obtain an adjusted power-off storage space, and determines an adjusted storage channel corresponding to the adjusted power-off storage space.

[0202] In this embodiment, the main control chip can compare the wear of each power-off storage space and determine the power-off storage space with the least wear as the power-off storage space corresponding to the data to be stored, thereby obtaining an adjusted power-off storage space. The main control chip determines the storage channel corresponding to the adjusted power-off storage space as the adjusted storage channel.

[0203] For example, since the wear degree (12) of the fourth power-off storage space is less than the wear degree (76) of the third power-off storage space, the main control chip can adjust the power-off storage space corresponding to the metadata type data to be stored from the third power-off storage space to the fourth power-off storage space. Since the third power-off storage space corresponds to the third storage channel and the fourth power-off storage space corresponds to the fourth storage channel, the main control chip adjusts the storage channel for transmitting the metadata type data to be stored from the third storage channel to the fourth storage channel.

[0204] S604: The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0205] In this embodiment, after determining the adjusted storage channel and the adjusted power-off storage space, the main control chip can store the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0206] It should be noted that after determining the adjusted power-off storage space, the main control chip can update the first correspondence table between the data type stored in the volatile memory chip and at least one non-volatile memory chip and the power-off storage space based on the information, so that when the solid-state hard disk suffers a second power outage, the main control chip can determine the power-off storage space corresponding to the type of data to be stored based on the updated first correspondence table.

[0207] In this embodiment, the main control chip can adjust the power-off storage space used to store the data to be stored according to the wear degree of the power-off storage space, and then adjust the storage channel used to transmit the data to be stored to ensure that the power-off storage space with low wear degree is used first to store the data to be stored, thereby avoiding the problem of data loss caused by storing the data to be stored in the power-off storage space with high wear degree.

[0208] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0209] Figure 7 A schematic diagram of a power failure processing device according to an embodiment of the present application; Figure 7 As shown, the power-off processing device 70 includes: a control module 71 and a processing module 72. The control module 71 is configured to, upon detecting that the solid-state drive is in a power-off state, control the backup capacitor to supply power to the solid-state drive and obtain data to be stored stored in the volatile memory chip; the data to be stored includes data of multiple data types; the processing module 72 is configured to, for each data type, determine a corresponding power-off storage space for the data to be stored based on the data type of the data to be stored, and store the data to be stored in the corresponding power-off storage space; the power-off storage space includes a portion of storage space in at least one non-volatile memory chip, and the power-off storage space is a single-layer unit type storage space.

[0210] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0211] In the preferred technical solution of the above-mentioned power-off processing device, the processing module 72 is specifically used to: for each data type of the data to be stored, determine the power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and determine the storage channel corresponding to the corresponding power-off storage space, and store the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

[0212] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0213] In the preferred technical solution of the above-mentioned power-off processing device, the processing module 72 is specifically used to: read the first correspondence table and the second correspondence table stored in the volatile memory chip, or read the first correspondence table and the second correspondence table stored in the non-volatile memory chip; wherein the first correspondence table is a correspondence table between data types and power-off storage spaces, and the second correspondence table is a correspondence table between power-off storage spaces and storage channels; for each data type of data to be stored, according to the data type of the data to be stored and the correspondence table, determine the power-off storage space corresponding to the data to be stored, determine the storage channel corresponding to the corresponding power-off storage space, and store the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

[0214] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0215] In the preferred technical solution of the above-mentioned power-off processing device, the processing module 72 is also used to: for each data type of data to be stored, after the data to be stored is stored in the corresponding power-off storage space through the corresponding storage channel, generate a power-off data completion identifier corresponding to the data type of the data to be stored, and store the power-off data completion identifier in the power-off storage space; when it is detected that the solid-state hard disk is in a powered-on state and the power-off data completion identifier is stored in the power-off storage space, store the data to be stored stored in the power-off storage space in the non-power-off storage space of the non-volatile memory chip.

[0216] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0217] In the preferred technical solution of the above-mentioned power-off processing device, the processing module 72 is specifically used to: when it is detected that the solid-state hard disk is in a powered-on state and the power-off data stored in the power-off storage space is marked as completed, store the data to be stored in the power-off storage space in the volatile memory chip; and store the data to be stored in the volatile memory chip in the non-power-off storage space of the non-volatile memory chip.

[0218] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0219] In the preferred technical solution of the above-mentioned power-off processing device, the processing module 72 is specifically used to: when it is detected that the solid-state hard disk is in a powered-on state and the power-off data stored in the power-off storage space is marked as completed, directly store the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip.

[0220] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0221] In the preferred technical solution of the above power-off processing device, the processing module 72 is further configured to format the power-off storage space into a single-layer unit type storage space to perform data clearing processing on the power-off storage space.

[0222] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0223] In the preferred technical solution of the power-off processing device of the solid-state hard disk described above, the processing module 72 is further used to: determine the amount of data to be stored of each data type and the capacity corresponding to each power-off storage space; adjust the power-off storage space corresponding to the data to be stored according to the amount of data to be stored of each data type and the capacity corresponding to each power-off storage space to obtain an adjusted power-off storage space, and determine an adjusted storage channel corresponding to the adjusted power-off storage space; and the main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0224] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0225] In the preferred technical solution of the above-mentioned power-failure processing device, the processing module 72 is further used to: determine the total number of power-failure storage spaces and the priority corresponding to the data to be stored of each data type; determine the number of power-failure storage spaces corresponding to the data to be stored according to the total number of power-failure storage spaces and the priority corresponding to the data to be stored of each data type; adjust the power-failure storage spaces corresponding to the data to be stored according to the number of power-failure storage spaces to obtain adjusted power-failure storage spaces, and determine adjusted storage channels corresponding to the adjusted power-failure storage spaces; and store the data to be stored in the adjusted power-failure storage spaces through the adjusted storage channels.

[0226] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0227] In the preferred technical solution of the above-mentioned power-off processing device, the processing module 72 is also used to: determine the wear degree of each power-off storage space; adjust the power-off storage space corresponding to the data to be stored according to the wear degree of each power-off storage space to obtain the adjusted power-off storage space, and determine the adjusted storage channel corresponding to the adjusted power-off storage space; store the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

[0228] The power-off processing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0229] Figure 8 This is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. Figure 8 As shown, computing device 80 includes motherboard 81 and solid state drive 82. Motherboard 81 includes motherboard interface 811, and solid state drive 82 includes hard drive connector 822. Motherboard 81 is connected to solid state drive 82 via motherboard interface 811 and hard drive connector 822.

[0230] In one possible implementation, the computing device 80 may further include an adapter cable, and the motherboard 81 may be connected to the solid-state drive 82 via the motherboard interface 811 , the adapter cable, and the hard drive connector 822 .

[0231] Among them, the computing device can be a terminal device (mobile phone, computer) and server and other devices.

[0232] It should be noted that the solid state drive 82 in the embodiment of the present application is the above Figure 1 The solid-state hard drive provided can implement the technical solution shown in the above method embodiment. Its implementation principles and beneficial effects are similar and will not be repeated here.

[0233] An embodiment of the present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the technical solution provided by any of the aforementioned method embodiments.

[0234] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0235] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A power failure processing method, characterized in that: Applied to a solid-state hard disk, the solid-state hard disk includes a main control chip and a backup capacitor electrically connected to the main control chip, a volatile memory chip, and at least one non-volatile memory chip, the method comprising: When the main control chip detects that the solid-state hard disk is in a power-off state, it controls the backup capacitor to supply power to the solid-state hard disk and obtains the data to be stored in the volatile memory chip; wherein the data to be stored includes data of multiple data types to be stored; The main control chip determines, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and simultaneously stores the data to be stored of each data type into the corresponding power-off storage space through the corresponding storage channel; The power-off storage space includes a portion of storage space in at least one non-volatile memory chip, and the power-off storage space is a single-layer unit type storage space.

2. The power failure processing method according to claim 1, characterized in that: The main control chip determines, for each data type of data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored, and simultaneously stores the data to be stored for each data type into the corresponding power-off storage space through the corresponding storage channel, including: The main control chip determines the power-off storage space corresponding to the data to be stored for each data type according to the data type of the data to be stored, determines the storage channel corresponding to the corresponding power-off storage space, and stores the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

3. The power failure processing method according to claim 2, characterized in that: The main control chip determines, for each data type of the data to be stored, a power-off storage space corresponding to the data to be stored, and determines a storage channel corresponding to the corresponding power-off storage space according to the data type of the data to be stored, and stores the data to be stored in the corresponding power-off storage space through the corresponding storage channel, including: The main control chip reads a first correspondence table and a second correspondence table stored in the volatile memory chip, or reads the first correspondence table and the second correspondence table stored in the non-volatile memory chip; wherein the first correspondence table is a correspondence table between data types and power-off storage spaces, and the second correspondence table is a correspondence table between power-off storage spaces and storage channels; The main control chip determines, for each data type of data to be stored, a power-off storage space corresponding to the data to be stored according to the data type of the data to be stored and the first correspondence table, and determines a storage channel corresponding to the corresponding power-off storage space according to the corresponding power-off storage space and the second correspondence table, and stores the data to be stored in the corresponding power-off storage space through the corresponding storage channel.

4. The power failure processing method according to claim 2, characterized in that: Also includes: The main control chip generates a power-off data completion flag corresponding to the data type of the data to be stored, after storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel, and stores the power-off data completion flag in the power-off storage space; When the main control chip detects that the solid state drive is in a powered-on state and the power-off data storage completion mark is stored in the power-off storage space, the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip.

5. The power failure processing method according to claim 4, characterized in that: When the main control chip detects that the solid state drive is in a powered-on state and a power-off data storage completion mark is stored in the power-off storage space, the main control chip stores the data to be stored in the power-off storage space into the non-power-off storage space of the non-volatile memory chip, including: When the main control chip detects that the solid state drive is in a powered-on state and a power-off data storage completion mark is displayed in the power-off storage space, the main control chip stores the data to be stored in the power-off storage space into the volatile memory chip; The main control chip stores the data to be stored in the volatile memory chip into the non-power-off storage space of the non-volatile memory chip.

6. The power failure processing method according to claim 5, characterized in that: Also includes: The main control chip formats the power-off storage space into the single-layer unit type storage space to perform data clearing processing on the power-off storage space.

7. The power failure processing method according to claim 2, characterized in that: Also includes: The main control chip determines the amount of data to be stored for each data type and the capacity corresponding to each power-off storage space; The main control chip adjusts the power-failure storage space corresponding to the data to be stored according to the amount of the data to be stored of each data type and the capacity corresponding to each power-failure storage space to obtain an adjusted power-failure storage space, and determines an adjusted storage channel corresponding to the adjusted power-failure storage space; Then, storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel includes: The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

8. The power failure processing method according to claim 2, characterized in that: Also includes: The main control chip determines the wear degree of each power-off storage space; The main control chip adjusts the power-off storage space corresponding to the data to be stored according to the wear degree of each power-off storage space to obtain an adjusted power-off storage space, and determines an adjusted storage channel corresponding to the adjusted power-off storage space; Then, storing the data to be stored in the corresponding power-off storage space through the corresponding storage channel includes: The main control chip stores the data to be stored in the adjusted power-off storage space through the adjusted storage channel.

9. A solid state hard disk, characterized in that: include: A main control chip, and a backup capacitor, a volatile memory chip and at least one non-volatile memory chip electrically connected to the main control chip; wherein, The main control chip is used to control the backup capacitor to supply power to the solid-state hard disk and obtain the data to be stored in the volatile memory chip when detecting that the solid-state hard disk is in a power-off state; wherein the data to be stored includes data of multiple data types to be stored; The main control chip is further configured to determine, for each data type of the data to be stored, a corresponding power-off storage space for the data to be stored according to the data type of the data to be stored, and simultaneously store the data to be stored of each data type into the corresponding power-off storage space through the corresponding storage channel; The power-off storage space includes a portion of storage space in at least one non-volatile memory chip, and the power-off storage space is a single-layer unit type storage space.

10. A computing device, characterized in that comprising a mainboard and the solid state hard disk according to claim 9; Wherein, the mainboard includes a mainboard interface, and the solid-state hard disk includes a hard disk connector; The mainboard is connected to the solid state hard disk through the mainboard interface and the hard disk connector.

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