Test method and system of memory chip

Abstract

The invention provides a test method and system for a storage chip, and relates to the technical field of storage chips, and the method comprises the steps: obtaining the physical parameter data of the storage chip; mapping each physical parameter data to a low-dimensional manifold space in a coupling manner by taking a storage unit as a unit; calculating the local curvature of each storage unit in the low-dimensional manifold space; the storage units are screened according to the size relation between the self-adaptive local curvature threshold value based on the average value and the standard deviation and the local curvature; in combination with a low-dimensional manifold space, a test path of a fault potential area is generated based on an optimal transmission theory; testing the memory chip once according to the test path; and verifying whether the fault potential area is completely tested or not by combining a homology group in algebraic topology, if so, outputting the tested fault storage unit, otherwise, generating a supplementary test path, and performing secondary test according to the supplementary test path. The test efficiency and the identification accuracy of the fault unit can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chips, and in particular to a memory chip testing method and system. Background Art

[0002] Non-volatile memory (NVM) is a type of memory chip that retains data even after a power outage. Common types of non-volatile chips include NAND Flash, NOR Flash, EPROM, EEPROM, MRAM, and ReRAM. Unlike volatile memories like DRAM and SRAM, NVM can be used for long-term data storage and is an essential core component in embedded systems, solid-state drives (SSDs), mobile devices, and industrial control.

[0003] While non-volatile memory chips store data for long periods of time, they also face a variety of physical failure risks, including write loss, data retention decay, bad block formation, and bit flipping. Therefore, systematic and meticulous testing is crucial. This testing not only identifies initial and manufacturing defects but also assesses lifespan, fault tolerance, and data integrity, ensuring chip reliability, security, and stability for large-scale applications.

[0004] However, most existing non-volatile memory chip testing methods use global traversal testing, which performs indiscriminate repeated read and write operations on all memory cells. As the capacity of memory chips becomes larger and larger, traditional traversal testing methods are not only inefficient and time-consuming, but also cause a large number of redundant tests, making it difficult to accurately identify areas with high failure probability, resulting in a waste of test resources and the easy concealment of key defects. Frequent erasure and writing will also accelerate the aging of memory cells, affecting the chip life and stability. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of an embodiment of the present invention is to provide a method for testing a memory chip, which can solve the problem that most of the non-volatile memory chip testing methods in the prior art adopt global traversal testing, and perform indiscriminate repeated read and write operations on all memory cells. As the capacity of memory chips becomes larger and larger, traditional traversal testing methods are not only inefficient and time-consuming, but also cause a large number of redundant tests, making it difficult to accurately identify areas with high failure probability, resulting in waste of test resources, key defects being easily concealed, and frequent erasing and writing will accelerate the aging of memory cells, affecting the chip life and stability.

[0006] According to a first aspect of an embodiment of the present invention, a method for testing a memory chip is provided, comprising: S1: Acquire physical parameter data of the memory chip, wherein the physical parameter data includes charge leakage rate data, erase count data, and memory cell spacing data; S2: Taking storage units as units, each physical parameter data is mapped to a low-dimensional manifold space in a coupled manner; S3: Calculate the local curvature of each storage unit in the low-dimensional manifold space; S4: Filtering storage cells using a relationship between an adaptive local curvature threshold based on a mean value and a standard deviation and the local curvature, wherein the filtered storage cells constitute a potential fault area; S5: Combined with low-dimensional manifold space, test paths for potential fault areas are generated based on optimal transmission theory; S6: Test the memory chip once according to the test path; S7: Verify whether the potential fault area is fully tested by combining the homology group in algebraic topology. If so, proceed to step S9; otherwise, proceed to step S8. S8: Generate a supplementary test path and perform a secondary test based on the supplementary test path; S9: Output the faulty storage unit obtained from the test.

[0007] A second aspect of an embodiment of the present invention provides a memory chip testing system, comprising: a processor and a memory; The memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the memory chip testing method of the first aspect are implemented.

[0008] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least: In an embodiment of the present invention, by extracting key physical parameters such as charge leakage rate, number of erases and cell spacing, a characteristic vector reflecting the actual aging and coupling interference state of the storage cell is constructed, and through nonlinear manifold embedding and local curvature calculation, high-risk areas are accurately identified, thereby avoiding the invalid traversal that is prevalent in traditional testing from the source. Subsequently, an adaptive threshold screening mechanism is used to focus on structurally complex areas, and combined with optimal transmission theory, a test sequence for units with high failure probability is generated according to the minimum path cost, further compressing test jumps and duration. On this basis, the homology group difference analysis in algebraic topology is introduced to ensure that all key topological structures are covered; if a structural gap is found, the path of the missed area with the smallest diameter is re-tested to avoid repeated testing and redundant erasure. Effectively improve test efficiency and the accuracy of identifying faulty units, and avoid reducing chip life due to unnecessary testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are only for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the drawings, the same reference symbols represent the same components. Obviously, the drawings described below are only some embodiments of the present invention. It is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0010] Figure 1 This is a flow chart of a method for testing a memory chip provided by an embodiment of the present invention;

[0011] Figure 2 The figure is a schematic structural diagram of a memory chip testing system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0012] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the scope of protection of the present invention.

[0013] The memory chip testing method provided by the embodiment of the present invention is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios.

[0014] Reference Manual Figure 1 , which shows a flow chart of a method for testing a memory chip provided by an embodiment of the present invention.

[0015] An embodiment of the present invention provides a method for testing a memory chip, comprising the following steps: S1: Acquire physical parameter data of a memory chip, wherein the physical parameter data includes charge leakage rate data, erase count data, and memory cell spacing data.

[0016] Among them, the charge leakage rate data represents the decay rate of charge in the storage cell over time, and is a core indicator reflecting the "data retention capability" of non-volatile cells. The higher the leakage rate, the more unstable the data retention, indicating that the cell has potential risks. The erase count data represents the total number of times a certain storage cell has been erased and written, and is a key parameter for judging the "ageing degree" of the cell. The more erase and write times, the more likely the cell is to have physical defects such as erase failure and bit inversion. The storage cell spacing data represents the physical or logical position distance between a storage cell and its surrounding cells, reflecting possible interference or coupling effects between cells, such as the electric field disturbance caused by writing to adjacent cells.

[0017] In a possible implementation, S1 specifically includes: S101: Obtain charge leakage rate data and erase count data by reading a storage chip log.

[0018] S102: Obtaining memory cell spacing data through a memory chip layout.

[0019] It's understood that the charge leakage rate of newly manufactured memory chips can be predicted using device simulation software (such as TCAD) at standard temperature and voltage. The erase count is obtained from the "erase and write life table" during factory testing. The memory cell pitch is directly read from the physical design (Layout) file in the back-end layout. For memory chips currently in use, this can be obtained from chip operation logs, controller records, and in-service data monitoring.

[0020] It should be noted that by extracting quantifiable physical parameters during the operation of the memory chip, the health status and failure tendency of each memory unit can be accurately reflected, providing a reliable basis for subsequent fault prediction and differentiated testing, effectively improving the targetedness and accuracy of the test, and avoiding resource waste and chip damage caused by blind traversal.

[0021] S2: Taking storage units as units, each physical parameter data is mapped to the low-dimensional manifold space in a coupled manner.

[0022] The low-dimensional manifold space is a low-dimensional embedding space extracted from the original high-dimensional feature space. It preserves the geometric structural relationships or similarity patterns between storage cells. While the original physical parameter space is high-dimensional (such as charge leakage rate, erase count, and cell spacing), it is computationally complex due to its multi-dimensionality. The low-dimensional manifold space represents these features comprehensively, revealing potential abnormal clusters or fault structures more clearly.

[0023] Specifically, each storage cell corresponds to a feature vector (including charge leakage rate, number of erases, spacing, etc.). These features are not used in isolation, but are coupled together (taking into account the inherent correlations between them). Then, through an embedding mapping algorithm, this high-dimensional data is reduced in dimension and mapped into a low-dimensional space. This resulting space is known as a low-dimensional manifold space, which can reflect which cells are similar to each other and which cells may form abnormal structures. By jointly embedding multiple parameters into the low-dimensional manifold space, the potential correlations between physical properties are effectively integrated, and the structural patterns and local abnormal characteristics between storage cells are explored. This allows for more accurate spatial distribution modeling and risk cell positioning, laying the foundation for subsequent screening and test path optimization.

[0024] In a possible implementation, S2 specifically includes: S201: Create a storage unit feature vector including physical parameter data.

[0025] S202: Calculate the similarity matrix between the eigenvectors of each storage unit using the Mahalanobis kernel matrix.

[0026] The formula form of the similarity matrix is: ; in, and Represent the storage unit feature vectors of the i-th and j-th storage units respectively, express and The similarity matrix between them, exp represents the natural exponential function, represents a nonlinear mapping function, and express and The local density estimate of Represents the scale coefficient that controls the influence range of the similarity of the feature vector of the storage unit.

[0027] in, The local density estimate reflects the density of the memory cells in the entire memory chip. The specific calculation method of local density estimation usually depends on the similarity between the feature vectors of the storage units. It can be calculated by counting the similarity within a certain range (for example, based on Euclidean distance or similarity measurement) and The nonlinear mapping function can be a Gaussian mapping or a polynomial mapping.

[0028] Specifically, adjust It can affect whether cells are considered similar. For example, when the value is large, even if two cells have very different characteristics, they may be considered similar. On the other hand, when the value is small, the similarity is judged more strictly. More specifically, The value range is 0.1 to 1.

[0029] S203: Calculate the eigenvalues ​​and the projection value of each storage unit eigenvector on each feature dimension from the similarity matrix.

[0030] S204: Mapping each physical parameter data to a low-dimensional manifold space in a coupled manner according to the eigenvalues ​​and the projection values.

[0031] The mapping formula of step S204 is specifically: ; in, express The low-dimensional manifold coordinates of in the low-dimensional manifold space, Indicates the eigenvalue of the dth feature dimension, d=1,2,3, express The projection value on the d-th feature dimension.

[0032] Specifically, this process can effectively convert the physical parameters of the memory chip into the eigenvectors of the memory cell and use the Mahalanobis kernel matrix to calculate the similarity matrix between these eigenvectors. Through nonlinear mapping and local density estimation, combined with adjustment parameters, the similarity between memory cells is accurately evaluated. Then, through eigenvalue decomposition and projection, the high-dimensional data is mapped into a low-dimensional manifold space, effectively reducing the dimension and retaining key information. This method can significantly improve test efficiency while maintaining data complexity, accurately locate potential fault areas, and optimize the test path of the memory chip, reducing unnecessary redundant testing, while improving the accuracy and pertinence of the test.

[0033] S3: Calculate the local curvature of each storage unit in the low-dimensional manifold space.

[0034] Local curvature is a metric that describes the degree of local geometric deformation of a storage cell within a low-dimensional manifold space. By calculating the local curvature of each storage cell in this low-dimensional space, we can effectively identify areas with structural abrupt changes and complex geometric relationships. This allows for precise detection and early warning of high-risk potential defects, preventing traditional methods from missing critical abnormal cells.

[0035] In a possible implementation, S3 specifically includes: S301: Establishing a local coordinate system with different feature dimensions as coordinate axes.

[0036] Specifically, by selecting different features in the data as coordinate axes, a new coordinate system is established to represent the local structure and relationships of the data. This allows the analysis of specific features to be focused without considering all features in the dataset, thus simplifying the understanding and processing of complex data.

[0037] S302: Obtain tangent vectors of low-dimensional manifold coordinates in different feature dimensions, wherein the tangent vector is used to describe the basic unit of change of the point corresponding to each storage unit along different dimensions in the manifold space.

[0038] S303: Calculate the local curvature based on the obtained tangent vector and the Riemann curvature tensor.

[0039] The calculation process of local curvature is as follows: ; in, Indicates the storage unit corresponding to the i The corresponding local curvature in manifold space is, represents the Frobenius norm, and They represent the tangent vectors describing the changes in charge leakage rate, erase count and memory cell spacing, respectively. represents the inner product operator, Represents the Riemann curvature tensor that describes the curved state caused by the synergy between the charge leakage rate direction and the erase count direction.

[0040] Among them, the Riemann curvature tensor is a core concept in differential geometry, which is used to describe the degree of curvature and directional dependence of a space at a certain point.

[0041] Specifically, by constructing a local coordinate system with the characteristic dimension as the coordinate axis, the tangent vectors of each storage unit in all directions in the low-dimensional manifold space are extracted, and then the local curvature of the point is accurately calculated in combination with the Riemann curvature tensor. This curvature value reflects the geometric complexity and degree of abnormality of the structure of the unit in the characteristic space. The calculation formula comprehensively considers the nonlinear coupling relationship between the three characteristic dimensions (charge leakage rate, number of erases, and cell spacing) to identify high-risk areas with mutation or heterogeneity. Compared with traditional distance or statistical anomaly detection methods, this method can capture "inflection points" and "abnormal clusters" hidden in the spatial structure, greatly improving the positioning accuracy of potential faulty units, ensuring that subsequent tests focus on locations where defects may actually exist, and reducing test redundancy and resource waste.

[0042] S4: Filtering storage cells using a size relationship between an adaptive local curvature threshold based on a mean value and a standard deviation and the local curvature, wherein the filtered storage cells constitute a potential fault area.

[0043] It should be noted that by constructing an adaptive threshold based on the average value and standard deviation of the curvature distribution of all storage cells, we can dynamically determine which cells have significantly higher curvatures, and then screen out these high-structural complexity areas as potential fault areas. This allows for the intelligent extraction of key test objects from all storage cells, improving test efficiency and enhancing the targeted nature of defect detection.

[0044] In a possible implementation, the adaptive local curvature threshold is specifically the sum of the average local curvature intensity of the low-dimensional manifold space and three times the local curvature variance.

[0045] The formula form of the adaptive local curvature threshold is: ; in, Indicates the total number of storage units, represents the local curvature variance.

[0046] S4 specifically includes: The storage cells corresponding to the local curvatures greater than the adaptive local curvature threshold are retained to obtain the potential fault area.

[0047] Specifically, by counting the local curvature of all memory cells in a low-dimensional manifold space, calculating the mean and variance, and setting a dynamic threshold, cells with curvature significantly above the normal fluctuation range are screened as potential fault areas. This method has the advantages of strong adaptability and high sensitivity to anomalies. It can accurately extract structural anomaly areas based on the actual chip distribution, avoiding misjudgments or missed detections caused by fixed thresholds, and improving fault identification accuracy and testing efficiency.

[0048] S5: Combined with low-dimensional manifold space, test paths of potential fault areas are generated based on optimal transmission theory.

[0049] It should be noted that using optimal transmission theory to plan test paths in low-dimensional space, taking into account distance and structural complexity, and prioritizing traversal of high-risk units with the minimum jump cost can significantly compress the test path length, reduce test time and resource consumption, and at the same time improve fault detection efficiency and accuracy.

[0050] In a possible implementation, S5 specifically includes: S501: Establishing a test jump cost function describing a jump from a first storage unit to a second storage unit by combining low-dimensional manifold coordinates of different storage units in the low-dimensional manifold space and local curvatures between different storage units.

[0051] The test jump cost function is specifically: ; ; in, represents the test jump cost of jumping from the i-th storage unit to the j-th storage unit, y i express, represents the geometric structure relationship between the i-th storage unit and the j-th storage unit in the low-dimensional manifold space calculated by the neighborhood Jacobian matrix of the i-th storage unit and the neighborhood Jacobian matrix of the j-th storage unit, Indicates measurement The rank of complexity, Represents a distance measure and curvature complexity The weight parameter, J i and J j express.

[0052] S502: Determine a test path for potential fault areas with the goal of ensuring that important points are passed first.

[0053] The solution formula for the test path is: ; ; Where S represents the potential fault area, represents the test path from storage unit i to storage unit j that covers the potential fault area, Indicates the test path under the minimum function value As the optimal test path Output, Indicates the test path The gradient convergence amount on the i-th storage unit is the test resource consumption on the storage unit i.

[0054] Specifically, Is a constraint that controls the test strategy The purpose of the distribution method is to distribute test resources unevenly, focusing on high-risk areas and high-complexity areas.

[0055] It should be noted that this process constructs a jump cost function based on low-dimensional embedded coordinates and local geometry, comprehensively considering the spatial distance and curvature differences between storage cells to quantify the quality of test paths. Furthermore, optimal transmission theory is introduced to solve test paths that prioritize coverage of high-risk points while minimizing cost. Resource distribution constraints are then used to prioritize the investment of test resources in complex areas. This method enables a differentiated testing strategy with the shortest path, clear goals, and optimal efficiency, significantly improving fault detection coverage and resource efficiency.

[0056] S6: Perform a test on the memory chip according to the test path.

[0057] In a possible implementation, S6 specifically includes: The test data is used to perform a test according to the test path, wherein the test data includes zero-one data, grid data, inverted checkerboard data, row-reversed data and pseudo-random data.

[0058] It's important to note that by using a variety of test data types (such as zero-one data, grid data, and inverted checkerboard data), we can comprehensively cover the different response modes and possible fault types of memory cells. These high-coverage standard test patterns enable rapid and accurate detection of potential memory chip defects, while reducing missed tests and improving test reliability, providing an accurate basis for subsequent fault location.

[0059] S7: Verify whether the potential fault area is fully tested in combination with the homology group in algebraic topology. If so, proceed to step S9; otherwise, proceed to step S8.

[0060] Homology groups are a core concept in algebraic topology, used to characterize the topological structure of a space across different dimensions. Comparing homology groups determines whether the test area is fully covered at the structural level, effectively avoiding structural omissions caused by path selection. This ensures the mathematical and spatial integrity of the test results, thereby improving test reliability and defect detection rates.

[0061] In a possible implementation, S7 specifically includes: S701: Calculate the multi-order homology groups of the potential fault region and the low-dimensional manifold space respectively.

[0062] S702: Calculate the rank difference between the potential fault region and the multi-order homology group of the low-dimensional manifold space.

[0063] The calculation formula of the rank difference is: ; in, represents the homology group order, represents the number of connected components in the region, represents the number of rings or loops in the area, represents the number of cavities or faces in the region, Represents The associated rank difference value, and Respectively represent The related fault potential region S and the multi-order homology group of the low-dimensional manifold space M, Represents the rank operator.

[0064] Specifically, It represents the number of connected components in the region, that is, how many disconnected parts or independent regions there are in the space. The number of rings or loops in an area is how many ring structures there are in the space or paths that cannot be contracted into points. Represents the number of cavities or faces in a region, like "holes" in space or "surfaces" in two dimensions.

[0065] It is important to note that by calculating the homology group ranks of the potential fault region and the low-dimensional manifold space in different dimensions, we can determine the structural differences between the two in each topological dimension. This rank difference can be used to determine whether there are any key topological features that have not been fully tested. This avoids simple point coverage testing, more accurately ensures structural completeness, effectively identifies missed areas, and improves test integrity and accuracy.

[0066] S703: If the rank difference value is greater than 0, it is determined that the potential fault area has completed the full test; otherwise, it is determined that the potential fault area has not completed the full test.

[0067] It should be noted that this process determines whether the test area has achieved complete structural coverage by calculating the homology groups of the potential fault area and the overall low-dimensional manifold space in different topological dimensions (such as connectivity, loops, and cavities), and further calculating their rank difference values. If there is a rank difference, it means that key topological structures have not been measured and require additional testing. Compared with traditional point coverage strategies, this method not only considers whether "certain units have been measured", but also verifies the integrity of the test from a topological perspective. It has higher mathematical rigor and global accuracy, can effectively prevent structural omissions, and improve the quality and reliability of test coverage.

[0068] S8: Generate a supplementary test path, and perform a secondary test based on the supplementary test path.

[0069] A supplementary test path is a minimized, supplementary test path replanned based on topological analysis results after detecting structural omissions in a potential fault area (as determined by coherence group comparison). This intelligent supplementary test path generation mechanism accurately locates incomplete topological areas, ensuring a narrow and targeted supplementary test scope, avoiding duplication of testing and wasted resources, ensuring comprehensive coverage of potential fault areas at minimal cost, and improving test integrity and efficiency.

[0070] In a possible implementation, S8 specifically includes: S801: Filter out missed detection areas from the low-dimensional manifold space.

[0071] S802: Determine the minimum diameter area from the missed-detection area.

[0072] S803: Generate a supplementary measurement path for the minimum diameter area.

[0073] The formula for generating the supplementary measurement path is as follows: ; in, Indicates the supplementary test path, Indicates taking the minimum function value , The multi-order homology group representing the fault potential area S The projection P, C on the multi-order homology group of the low-dimensional manifold space M represents the missed area, Indicates the diameter of C.

[0074] S804: Perform a secondary test according to the supplementary test path.

[0075] It's important to note that after detecting incomplete structural coverage of potential fault areas, this process first uses homology group mapping to identify incompletely tested areas in the low-dimensional manifold space. Then, the structural region with the smallest diameter is selected from these areas to generate a minimally costly retest path, which is then used for efficient retesting. This method, combining topological analysis with optimization strategies, minimizes the retest scope and resource consumption while ensuring complete structural coverage, avoiding duplicate testing, improving test efficiency, and improving chip protection capabilities. It is particularly suitable for fast and accurate fault detection in large-capacity memory chips.

[0076] S9: Output the faulty storage unit obtained from the test.

[0077] In practical applications, a multi-dimensional feature vector of the storage cell is constructed by extracting physical parameters such as charge leakage rate, number of erases, and cell spacing, and mapped to a low-dimensional manifold space, thereby reducing computational complexity while maintaining structural relationships. By combining local curvature analysis with adaptive threshold screening, potential fault areas are accurately located, and optimal transmission theory is then used to generate the shortest test path that covers key cells, significantly improving test efficiency and accuracy. After the test is completed, the homology group difference analysis in algebraic topology is used to verify whether the structure is fully covered. If there are omissions, a minimum supplementary test path is generated for supplementary testing, and the faulty cell is finally output. This method takes into account speed, resource control, and integrity, avoids redundant testing and chip damage, and is suitable for efficient and reliable testing of large-capacity non-volatile memory chips.

[0078] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least: In an embodiment of the present invention, by extracting key physical parameters such as charge leakage rate, number of erases and cell spacing, a characteristic vector reflecting the actual aging and coupling interference state of the storage cell is constructed, and through nonlinear manifold embedding and local curvature calculation, high-risk areas are accurately identified, thereby avoiding the invalid traversal that is prevalent in traditional testing from the source. Subsequently, an adaptive threshold screening mechanism is used to focus on structurally complex areas, and combined with optimal transmission theory, a test sequence for units with high failure probability is generated according to the minimum path cost, further compressing test jumps and duration. On this basis, the homology group difference analysis in algebraic topology is introduced to ensure that all key topological structures are covered; if a structural gap is found, the path of the missed area with the smallest diameter is re-tested to avoid repeated testing and redundant erasure. Effectively improve test efficiency and the accuracy of identifying faulty units, and avoid reducing chip life due to unnecessary testing.

[0079] Reference Manual Figure 2 , shows a structural diagram of a memory chip testing system provided by an embodiment of the present invention.

[0080] The embodiment of the present invention provides a memory chip testing system 20, comprising: a processor 201 and a memory 202; The memory 202 stores programs or instructions that can be run on the processor 201. When the programs or instructions are executed by the processor 201, the steps of the above-mentioned memory chip testing method are implemented and the same technical effect can be achieved. To avoid repetition, the present invention will not go into details.

[0081] It should be understood that the processor 201 in the embodiment of the present invention may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0082] It should also be understood that the memory 202 in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0083] The above embodiments can be implemented in whole or in part via software, hardware (e.g., circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are fully or partially performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0084] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0085] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0086] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0087] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of the device or unit, which can be electrical, mechanical or other forms.

[0088] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0089] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0090] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention. Any person skilled in the art can, within the technical scope disclosed in the present invention,

[0092] Any changes or substitutions that can be easily imagined should be included in the protection scope of the present invention.

Claims

1. A method for testing a memory chip, characterized in that: include: S1: Acquire physical parameter data of the memory chip, wherein the physical parameter data includes charge leakage rate data, erase count data, and memory cell spacing data; S2: Mapping each of the physical parameter data to a low-dimensional manifold space in a coupled manner, using storage units as units; S3: Calculating the local curvature of each of the storage units in the low-dimensional manifold space; S4: screening the storage units using a magnitude relationship between an adaptive local curvature threshold based on a mean value and a standard deviation and the local curvature, wherein the screened storage units constitute a potential fault area; S5: combining the low-dimensional manifold space and generating a test path for the potential fault area based on optimal transmission theory; S6: Perform a test on the memory chip according to the test path; S7: Verify whether the potential fault area is fully tested by combining the homology group in algebraic topology. If so, proceed to step S9; otherwise, proceed to step S8. S8: Generate a supplementary test path, and perform a secondary test according to the supplementary test path; S9: Output the faulty storage unit obtained from the test.

2. The memory chip testing method according to claim 1, wherein: Said S1 specifically includes: S101: Obtain the charge leakage rate data and the erase count data by reading a storage chip log; S102: Acquire the memory cell spacing data through a memory chip layout.

3. The memory chip testing method according to claim 1, wherein: The S2 specifically includes: S201: Establishing a storage unit feature vector including the physical parameter data; S202: Calculating a similarity matrix between the eigenvectors of each storage unit using a Mahalanobis kernel matrix; S203: Calculating eigenvalues ​​and projection values ​​of the eigenvectors of each storage unit on each feature dimension from the similarity matrix; S204: Mapping each of the physical parameter data to the low-dimensional manifold space in a coupled manner according to the eigenvalues ​​and the projection values.

4. The memory chip testing method according to claim 3, wherein: The S3 specifically includes: S301: Establishing a local coordinate system with different feature dimensions as coordinate axes; S302: Obtaining tangent vectors of low-dimensional manifold coordinates in different feature dimensions, wherein the tangent vectors are used to describe the basic units of changes of points corresponding to each storage unit along different feature dimensions in the low-dimensional manifold space; S303: Calculate the local curvature according to the obtained tangent vector and the Riemann curvature tensor.

5. The memory chip testing method according to claim 1, wherein: The adaptive local curvature threshold is specifically the sum of the average local curvature intensity of the low-dimensional manifold space and three times the local curvature variance; The S4 specifically includes: The storage units corresponding to the local curvatures greater than the adaptive local curvature threshold are retained to obtain the potential fault area.

6. The memory chip testing method according to claim 3, wherein: The S5 specifically includes: S501: establishing a test jump cost function describing a jump from a first storage unit to a second storage unit based on the low-dimensional manifold coordinates of different storage units in the low-dimensional manifold space and the local curvature between different storage units; S502: Determine a test path for the potential fault area with the goal of passing through important points first.

7. The memory chip testing method according to claim 1, wherein: The S6 is specifically: The test data is used to perform a test according to the test path, wherein the test data includes zero-one data, grid data, inverted checkerboard data, row-reversed data and pseudo-random data.

8. The memory chip testing method according to claim 1, wherein: The S7 specifically includes: S701: Calculate the multi-order homology groups of the potential fault region and the low-dimensional manifold space respectively; S702: Calculating the rank difference between the potential fault region and the multi-order homology group of the low-dimensional manifold space; S703: If the rank difference value is greater than 0, determine that the potential fault area has completed the full test; otherwise, determine that the potential fault area has not completed the full test.

9. The memory chip testing method according to claim 1, wherein: The S8 specifically includes: S801: Screening out missed detection areas from the low-dimensional manifold space; S802: Determine a minimum diameter area from the missed-detection area; S803: Generate a supplementary measurement path for the minimum diameter area; S804: Perform a secondary test according to the supplementary test path.

10. A memory chip testing system, characterized in that: include: processor and memory; The memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the memory chip testing method according to any one of claims 1 to 9 are implemented.

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