A control amplifier circuit, a sensitive amplifier and a semiconductor memory

Abstract

The embodiment of the present disclosure provides a control amplification circuit, a sensitive amplifier and a semiconductor memory, the control amplification circuit comprises: a power consumption control circuit, configured to receive a power consumption control signal and output a first reference signal according to the power consumption control signal; an isolation circuit, configured to determine a control instruction signal and generate an isolation control signal according to the control instruction signal; and an amplification circuit, configured to receive the first reference signal, the isolation control signal and a to-be-processed signal, and process the to-be-processed signal based on the first reference signal and the isolation control signal to obtain a target amplification signal. In this way, by controlling the amplification circuit, the first reference signal can be adjusted according to the power consumption control signal, so that the circuit power consumption is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a control amplifier circuit, a sensitive amplifier, and a semiconductor memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. During data reading, the read data signal for each memory cell is read sequentially via the local data line, global data line, and data bus; conversely, during data writing, the write data signal is written to the memory cell sequentially via the data bus, global data line, and local data line.

[0003] Currently, a sensitive amplifier exists between the storage unit and the local data line to improve the signal quality of the storage unit's contents. Stored data needs to be amplified by this sensitive amplifier before being read or written, but the signal amplification process consumes a significant amount of power. Summary of the Invention

[0004] This disclosure provides a control amplifier circuit, a sensitive amplifier, and a semiconductor memory that can reduce circuit power consumption during signal amplification.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a control amplifier circuit, including:

[0007] A power consumption control circuit is used to receive a power consumption control signal and output a first reference signal based on the power consumption control signal.

[0008] An isolation circuit is used to determine the control command signal and generate an isolation control signal based on the control command signal.

[0009] An amplifier circuit is used to receive a first reference signal, an isolation control signal, and a signal to be processed, and to process the signal to be processed based on the first reference signal and the isolation control signal to obtain the target amplified signal.

[0010] In some embodiments, the power consumption control circuit includes a first control circuit and a second control circuit, and the power consumption control signal includes a first power consumption control signal and a second power consumption control signal; wherein, the first control circuit is used to receive the first power consumption control signal and output a first reference signal having a first voltage value when the first power consumption control signal is at a first level; the second control circuit is used to receive the second power consumption control signal and output a first reference signal having a second voltage value when the second power consumption control signal is at a first level; wherein, the first voltage value is higher than the second voltage value.

[0011] In some embodiments, the first control circuit includes a plurality of first control sub-circuits, each first control sub-circuit including a first switch and a second switch; wherein, the first terminal of the first switch is used to receive a first power consumption control signal, the third terminal of the first switch, the first terminal of the second switch, and the second terminal of the second switch are connected, the third terminal of the second switch is connected to ground, and the second terminals of the second switches in the plurality of first control sub-circuits are interconnected; the second terminal of the first switch is used to output a first reference signal.

[0012] In some embodiments, a switch is provided between the third terminal of the first switching transistor and the first terminal of the second switching transistor, and the control terminal of the switch is connected to a power-saving control signal; wherein, when the first power consumption control signal is at a first level, the switch is controlled to be in a closed state by the power-saving control signal.

[0013] In some embodiments, the second control circuit includes a plurality of second control sub-circuits, and the second control sub-circuit includes a third switch; wherein, the first terminal of the third switch is used to receive a second power consumption control signal, the third terminal of the third switch is connected to ground, and the second terminal of the third switch is used to output a first reference signal.

[0014] In some embodiments, the power consumption control circuit further includes a control signal generation circuit; wherein the control signal generation circuit includes a plurality of first inverters, and the first inverters are used to receive an initial control signal and generate a power consumption control signal; wherein, among the plurality of first inverters, the first power consumption control signal of each first control sub-circuit is output through a first inverter, and the second power consumption control signal of each second control sub-circuit is output through a first inverter.

[0015] In some embodiments, the control amplification circuit further includes a reference control circuit; the reference control circuit is used to determine a reference control signal and output a second reference signal according to the reference control signal; the amplification circuit is also used to receive a first reference signal, a second reference signal, an isolation control signal and a signal to be processed, and process the signal to be processed based on the first reference signal, the second reference signal and the isolation control signal to obtain the target amplified signal shown.

[0016] In some embodiments, the reference control circuit includes a plurality of third control sub-circuits, and the third control sub-circuit includes a fourth switch; wherein, one end of the fourth switch is connected to a reference control signal, the second end of the fourth switch is connected to a first preset power supply, and the third end of the fourth switch is used to output a second reference signal.

[0017] In some embodiments, the reference control circuit includes multiple signal processing sub-circuits and multiple third control sub-circuits; wherein, the signal processing sub-circuit includes a second inverter, which is used to receive an initial reference signal and generate a reference control signal; the third control sub-circuit includes a fourth switch, the first terminal of which is connected to the reference control signal, the second terminal of which is connected to a first preset power supply, and the third terminal of which is used to output a second reference signal; wherein, the multiple signal processing sub-circuits and the multiple third control sub-circuits correspond one-to-one.

[0018] In some embodiments, the isolation circuit includes a first signal determination circuit, a power output circuit, a second signal determination circuit, and an isolation control circuit; wherein, the first signal determination circuit is used to output a first power switching signal and / or a second power switching signal according to the preset operation instruction after receiving the preset operation instruction; the power output circuit is used to output an isolation power value according to the first power switching signal and / or the second power switching signal; the second signal determination circuit is used to output a control instruction signal according to the preset operation instruction after receiving the preset operation instruction; and the isolation control circuit is used to receive the isolation power value and the control instruction signal and generate an isolation control signal.

[0019] In some embodiments, the power output circuit is configured to determine that the isolation power supply value has a third voltage value when the first power switching signal has a second level state and the second power switching signal has a first level state; or to determine that the isolation power supply value has a fourth voltage value when the first power switching signal has a first level state and the second power signal has a second level state; wherein the third voltage value and the fourth voltage value both belong to the first level state, and the third voltage value is greater than the fourth voltage value.

[0020] In some embodiments, the isolation control circuit is specifically configured to determine that the isolation control signal has a third voltage value when the control command signal has a first level state and the isolation power supply value has a third voltage value; or to determine that the isolation control signal has a fourth voltage value when the control command signal has a first level state and the isolation power supply value has a fourth voltage value; or to determine that the isolation control signal has a fifth voltage value when the control command signal has a second level state; wherein the fifth voltage value belongs to the second level state and the fifth voltage value is less than the fourth voltage value.

[0021] In some embodiments, the power output circuit includes a second preset power supply, a third preset power supply, a fifth switching transistor, and a sixth switching transistor; wherein, the first terminal of the fifth switching transistor is connected to a first power switching signal, and the first terminal of the sixth switching transistor is connected to a second power switching signal; the second terminal of the fifth switching transistor is connected to the second preset power supply, and the second terminal of the sixth switching transistor is connected to the third preset power supply; the third terminal of the fourth switching transistor is connected to the third terminal of the sixth switching transistor and is used to output an isolated power supply value; wherein, the second preset power supply is used to output a third voltage value, and the third preset power supply is used to output a fourth voltage value.

[0022] In some embodiments, the isolation control circuit includes a third inverter, a seventh switch, and an eighth switch; wherein, the input terminal of the third inverter is connected to a control command signal, and the output terminal of the third inverter is connected to the first terminal of the seventh switch and the first terminal of the eighth switch, respectively; the second terminal of the seventh switch is connected to an isolation power supply value, and the third terminal of the eighth switch is connected to a ground signal; the third terminal of the seventh switch and the second terminal of the eighth switch are connected to output an isolation control signal.

[0023] In some embodiments, the amplifier circuit includes a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch; the first terminal of the ninth switch is connected to the third terminal of the thirteenth switch for receiving a signal to be processed; the second terminals of the ninth switch, the third terminals of the eleventh switch, and the first terminals of the twelfth switch are connected to the second terminals of the fourteenth switch; the first terminal of the tenth switch is connected to the third terminal of the fourteenth switch for receiving a reference signal to be processed; the second terminals of the tenth switch, the third terminals of the twelfth switch, and the first terminals of the eleventh switch are connected to the second terminals of the thirteenth switch; the third terminals of the ninth and tenth switches are connected to a first reference signal; the second terminals of the eleventh and twelfth switches are connected to a second reference signal; and the first terminals of the thirteenth and fourteenth switches are connected to an isolation control signal.

[0024] In some embodiments, the amplifier circuit further includes a pre-charge circuit, and the pre-charge circuit includes a fifteenth switch and a sixteenth switch; wherein, the first terminal of the fifteenth switch and the first terminal of the sixteenth switch are connected to a pre-charge control signal; the second terminal of the fifteenth switch is connected to a fourth preset power supply, and the third terminal of the fifteenth switch is connected to the second terminal of the tenth switch; the second terminal of the sixteenth switch is connected to the second terminal of the tenth switch, and the third terminal of the sixteenth switch is connected to the second terminal of the ninth switch.

[0025] In some embodiments, the amplifier circuit further includes a noise cancellation circuit, which includes a seventeenth switch and an eighteenth switch; wherein, the first terminal of the seventeenth switch and the first terminal of the eighteenth switch are connected to the noise cancellation signal; the second terminal of the seventeenth switch is connected to the second terminal of the ninth switch, and the third terminal of the seventeenth switch is connected to the first terminal of the ninth switch; the second terminal of the eighteenth switch is connected to the second terminal of the tenth switch, and the third terminal of the eighteenth switch is connected to the first terminal of the tenth switch.

[0026] In some embodiments, the amplifier circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, a signal amplification stage, a signal write-back stage, and a pre-charge stage; if the amplifier circuit is in the second charge sharing stage, the signal amplification stage, or the pre-charge stage, the isolation control signal is maintained with a third voltage value; or if the amplifier circuit is in the standby stage or the signal write-back stage, the isolation control signal is maintained with a fourth voltage value; or if the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, the isolation control signal is maintained with a fifth voltage value.

[0027] In some embodiments, when the amplifier circuit is in the signal write-back stage, the first power consumption control signal is in a first level state and the second power consumption control signal is in a second level state; when the amplifier circuit is in the standby stage, noise cancellation stage, first charge sharing stage, second charge sharing stage, signal amplification stage, or pre-charge stage, the first power consumption control signal is in a second level state.

[0028] In some embodiments, the fifth, sixth, seventh, eleventh, and twelfth switching transistors are P-type channel field-effect transistors; the first, second, third, fourth, eighth, ninth, tenth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth switching transistors are N-type channel field-effect transistors; wherein, the first terminal of the P-type channel field-effect transistor is the gate terminal, the second terminal of the P-type channel field-effect transistor is the source terminal, and the third terminal of the P-type channel field-effect transistor is the drain terminal; the first terminal of the N-type channel field-effect transistor is the gate terminal, the second terminal of the N-type channel field-effect transistor is the drain terminal, and the third terminal of the N-type channel field-effect transistor is the source terminal.

[0029] In a second aspect, embodiments of this disclosure provide a sensitive amplifier, including a control amplifier circuit as described in any of the first aspects.

[0030] Thirdly, embodiments of this disclosure provide a semiconductor memory, including the sensitive amplifier described in the second aspect.

[0031] This disclosure provides a control amplifier circuit, a sensitive amplifier, and a semiconductor memory, comprising: a power consumption control circuit for receiving a power consumption control signal and outputting a first reference signal based on the power consumption control signal; an isolation circuit for determining a control command signal and generating an isolation control signal based on the control command signal; and an amplification circuit for receiving the first reference signal, the isolation control signal, and a signal to be processed, and processing the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal. Thus, by controlling the amplification circuit, the first reference signal can be adjusted according to the power consumption control signal, thereby reducing circuit power consumption. Attached Figure Description

[0032] Figure 1 A schematic diagram illustrating an application scenario for a sensitive amplifier;

[0033] Figure 2 A schematic diagram of the composition structure of a control amplifier circuit provided in an embodiment of this disclosure;

[0034] Figure 3 A schematic diagram of the composition structure of another control amplifier circuit provided in an embodiment of this disclosure;

[0035] Figure 4A This is a schematic diagram of the structure of a power consumption control circuit provided in an embodiment of the present disclosure;

[0036] Figure 4B This is a schematic diagram of another power consumption control circuit provided in an embodiment of the present disclosure;

[0037] Figure 5 This is a schematic diagram of the structure of an inverter provided in an embodiment of the present disclosure;

[0038] Figure 6A This is a schematic diagram of a reference control circuit provided in an embodiment of the present disclosure;

[0039] Figure 6B This is a schematic diagram of another reference control circuit provided in an embodiment of the present disclosure;

[0040] Figure 7 This is a schematic diagram of an isolation circuit provided in an embodiment of the present disclosure;

[0041] Figure 8 This is a schematic diagram of an amplifier circuit provided in an embodiment of the present disclosure;

[0042] Figure 9 This is a schematic diagram of another amplifier circuit provided in an embodiment of the present disclosure;

[0043] Figure 10This is a schematic diagram illustrating an application scenario of a control amplifier circuit provided in an embodiment of the present disclosure;

[0044] Figure 11 This is a schematic diagram illustrating another application scenario of the control amplifier circuit provided in the embodiments of this disclosure;

[0045] Figure 12 This is a signal timing diagram of an amplifier circuit provided in an embodiment of the present disclosure;

[0046] Figure 13 This is a signal timing diagram of an amplifier circuit;

[0047] Figure 14 A schematic diagram of the composition structure of a sensitive amplifier provided in an embodiment of this disclosure;

[0048] Figure 15 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0049] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0051] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0052] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0053] P-channel MOSFET: Hole-type MOSFET;

[0054] N-channel MOSFET: Electronic field-effect transistor.

[0055] It is understandable that sensitive amplifiers are needed to amplify signals during various operational processes in DRAM. (See also...) Figure 1 This illustrates a schematic diagram of an application scenario for a sensitive amplifier. For example... Figure 1 As shown, this application scenario includes a first signal line 11, a second signal line 12, and a sensitive amplifier 113. Among them,

[0056] The first signal line 11 has a first switch 111 and a first capacitor 112 for receiving the signal to be processed, Vin+; the second signal line 12 has a second switch 121 and a first capacitor 122 for receiving a reference signal to be processed, Vin-. The voltage difference between the signal to be processed, Vin+, and the reference signal to be processed, Vin-, is ΔVin. The sensitive amplifier 113 is used to amplify either the signal to be processed, Vin+, or the reference signal to be processed, Vin-. Here, the first switch 111 and the first capacitor 112 can be considered as one storage unit, and the second switch 121 and the second capacitor 122 can be considered as another storage unit.

[0057] Specifically, the sensitive amplifier includes a first switch 131, a second switch 132, a third switch 133, and a fourth switch 134. All are connected to the reference signal to be processed, Vin-. The third terminal of the first switch 131, the second terminal of the second switch 132, the first terminal of the third switch 133, and the first terminal of the fourth switch 134 are all connected to the signal to be processed, Vin+. In this application scenario, a fifth switch 135 and a sixth switch 136 also exist. The first terminal of the fifth switch 135 is connected to the first control signal SAP, and the second terminal of the fifth switch 135 is connected to the power supply signal VBLH. The third terminal of the fifth switch 135, the second terminal of the first switch 131, and the second terminal of the third switch 133 are connected to form the first reference signal terminal. The first terminal of the sixth switch 136 is connected to the second control signal SAN, and the second terminal of the sixth switch 136 is connected to the ground signal GND. The second terminal of the sixth switch 136, the third terminal of the second switch 132, and the third terminal of the fourth switch 134 are connected to form the second reference signal terminal. Among them, the first switch 131, the third switch 132, and the fifth switch 135 are P-type field-effect transistors, with the first terminal of the P-type field-effect transistor being the gate pin, the second terminal of the P-type field-effect transistor being the source pin, and the third terminal of the P-type field-effect transistor being the drain pin; the second switch 132, the fourth switch 134, and the sixth switch 136 are N-type field-effect transistors, with the first terminal of the N-type field-effect transistor being the gate pin, the second terminal of the N-type field-effect transistor being the drain pin, and the third terminal of the N-type field-effect transistor being the source pin.

[0058] In addition, a pre-charging circuit may exist between the first signal line 11 and the second signal line 12, and a pre-charging circuit may also exist between the second terminal of the third switch 133 and the third terminal of the fourth switch, for pre-charging the first reference signal terminal and the second reference signal terminal.

[0059] Currently, the signal amplification speed of the sensitive amplifier 10 is slow, the circuit is prone to noise, and the power consumption is high, which affects the performance of the semiconductor memory.

[0060] This disclosure provides a control amplifier circuit, including: a power consumption control circuit for receiving a power consumption control signal and outputting a first reference signal based on the power consumption control signal; an isolation circuit for determining a control command signal and generating an isolation control signal based on the control command signal; and an amplifier circuit for receiving the first reference signal, the isolation control signal, and a signal to be processed, and processing the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal. Thus, by controlling the amplifier circuit, the first reference signal can be adjusted according to the power consumption control signal, thereby reducing circuit power consumption.

[0061] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0062] In one embodiment of this disclosure, see Figure 2 This illustrates a schematic diagram of the composition of a control amplifier circuit 20 provided in an embodiment of the present disclosure. For example... Figure 2 As shown, the control amplifier circuit 20 may include:

[0063] The power consumption control circuit 21 is used to receive the power consumption control signal and output a first reference signal according to the power consumption control signal;

[0064] Isolation circuit 22 is used to determine the control command signal and generate an isolation control signal based on the control command signal;

[0065] Amplifier circuit 23 is used to receive a first reference signal, an isolation control signal, and a signal to be processed, and to process the signal to be processed based on the first reference signal and the isolation control signal to obtain the target amplified signal.

[0066] It should be noted that the control amplifier circuit 20 provided in this embodiment can be applied in various signal amplification scenarios, such as the sensitive amplifier in DRAM.

[0067] The control amplifier circuit 20 provided in this embodiment receives a power consumption control signal, a control command signal, and a signal to be processed from an external source. Based on the power consumption control signal and the control command signal, it completes the amplification process of the signal to be processed, and finally obtains the target amplified signal. Here, both the power consumption control signal and the control command signal need to be determined according to the specific operating stage of the amplifier circuit.

[0068] Specifically, for the control amplifier circuit 20, the power consumption control circuit 21 outputs a first reference signal based on the power consumption control signal; the isolation circuit 22 outputs an isolation control signal based on the control command signal and the isolation power supply value; and the amplifier circuit 23 amplifies the signal to be processed based on the first reference signal and the isolation control signal, and outputs the target amplified signal.

[0069] In this way, since a power consumption control circuit is set in the control amplifier circuit, the specific voltage value of the first reference signal can be adjusted according to the power consumption control signal, the signal amplification process can be optimized, and the power consumption of the circuit can be reduced.

[0070] In some embodiments, Figure 2 On the basis of, such as Figure 3 As shown, the power consumption control circuit 21 includes a first control circuit 211 and a second control circuit 212, and the power consumption control signals include a first power consumption control signal and a second power consumption control signal; wherein,

[0071] The first control circuit 211 is used to receive the first power consumption control signal and output a first reference signal with a first voltage value when the first power consumption control signal is at a first level.

[0072] The second control circuit 212 is used to receive the second power consumption control signal and output a first reference signal with a second voltage value when the second power consumption control signal is at the first level.

[0073] Here, the first voltage value is higher than the second voltage value.

[0074] It should be noted that the first voltage level is relative to the second voltage level, and the specific voltage range of the first (or second) voltage level needs to be determined for the specific electronic device. For example, for a P-type field-effect transistor (FET), the first voltage level enables it to be in the ON state, and the second voltage level enables it to be in the OFF state; for an N-type FET, the first voltage level enables it to be in the OFF state, and the second voltage level enables it to be in the ON state. Here, because different switching transistors have different specifications, the first voltage level may have different voltage ranges for different switching transistors. For ease of understanding, in a conventional notation, the first voltage level can be represented by logic "1", and the second voltage level can be represented by logic "0".

[0075] It should be understood that the first reference signal can be at least a first voltage value or a second voltage value, and can also have more voltage values.

[0076] In this way, when the first control circuit is turned on, the voltage value of the first reference signal is the first voltage value, and when the second control circuit is turned on, the voltage value of the first reference signal is the second voltage value. This provides the control circuit with more control means, optimizes the signal amplification process, and reduces circuit power consumption.

[0077] In some embodiments, Figure 3 Based on this, see Figure 4A This disclosure provides a schematic diagram of the structure of a power consumption control circuit 21 according to an embodiment. (See attached diagram.) Figure 4A As shown, the first control circuit 211 includes multiple first control sub-circuits (e.g., first control circuit 211a, first control sub-circuit 211b), and each first control sub-circuit includes a first switching transistor (e.g., first switching transistor 301a, first switching transistor 301b) and a second switching transistor 302 (e.g., second switching transistor 302a, second switching transistor 302b); wherein,

[0078] The first terminal of the first switch is used to receive the first power consumption control signal (e.g., the first power consumption control signal pdn3, the first power consumption control signal pdn2). The third terminal of the first switch, the first terminal of the second switch, and the second terminal of the second switch are connected. The third terminal of the second switch is connected to the ground signal. The second terminals of the second switches in multiple first control sub-circuits are connected to each other. For example, the second terminals of the second switch 302a and the second switch 302b are in a connected state.

[0079] The second terminal of the first switching transistor is used to output the first reference signal NCS.

[0080] It should be noted that, Figure 4A The diagram shows two first control sub-circuits, but in actual applications, there may be more or fewer first control sub-circuits. Additionally, there are multiple first power consumption control signals, with each signal input to a single first control sub-circuit. Here, the different first power consumption control signals can have the same or different voltage levels. In other words, each first control sub-circuit is controlled by a single first power consumption control signal.

[0081] like Figure 4A As shown, both the first and second switching transistors are N-type field-effect transistors (FETs). In the following description, the first terminal of the N-type FET is the gate pin, the second terminal is the drain pin, and the third terminal is the source pin.

[0082] For example, when both the first power consumption control signal pdn3 and the first power consumption control signal pdn2 are at a first level, both the first switch 301a and the second switch 302a are turned on, pulling the potential of the first reference signal down to a first voltage value Vt, where Vt refers to the threshold voltage of the second switch 302a and the second switch 302b. Here, if the threshold voltages of the second switch 302a and the second switch 302b are different, then Vt refers to the higher of the gate turn-on voltage of the second switch 302a and the threshold voltage of the second switch 302b.

[0083] By setting the second switching transistor, the current flowing through the first switching transistor is reduced. The special connection of the second switching transistor results in a very small current flowing through the two switching transistors, very low power consumption, and a stable first voltage value Vt can be provided to the NCS terminal.

[0084] In addition, by controlling the number of first switching transistors in the on state, the speed of voltage pull-down can also be controlled, thereby reducing the noise generated when the signal level decreases during signal amplification.

[0085] In some embodiments, see Figure 4B A schematic diagram of another power consumption control circuit 21 provided in this embodiment of the present disclosure. Figure 4B As shown, a switch is provided between the third terminal of the first switching transistor and the first terminal of the second switching transistor, and the control terminal of the switch is connected to the power saving control signal; wherein, when the first power consumption control signal is at the first level, the switch is controlled to be in the closed state by the power saving control signal.

[0086] In this way, by setting a switch in the first control sub-circuit and introducing a power-saving control signal for control, the operating state of the second switching transistor can be better controlled.

[0087] In some embodiments, such as Figure 4A or Figure 4B As shown, the second control circuit 212 includes multiple second control sub-circuits (e.g., second control sub-circuit 212a, second control sub-circuit 212b), and each second control sub-circuit includes a third switching transistor (e.g., third switching transistor 303a, third switching transistor 303b); wherein,

[0088] The first terminal of the third switch is used to receive the second power consumption control signal (e.g., the second power consumption control signal pdn0, the second power consumption control signal pdn1), the third terminal of the third switch is connected to the ground signal, and the second terminal of the third switch is used to output the first reference signal NCS.

[0089] It should be noted that, Figure 4A as well as Figure 4BEach example shows two second control sub-circuits, but in practical applications, there may be more or fewer. Furthermore, there are multiple second power consumption control signals, with each signal input to a single second control sub-circuit. Here, the different second power consumption control signals can have the same or different voltage levels. In other words, one second control sub-circuit is controlled by a single second power consumption control signal. Figure 5 As shown, the third switching transistors are all N-type field-effect transistors.

[0090] For example, when both the second power consumption control signal pdn1 and the second power consumption control signal pdn0 are at the first level, both the third switch transistors 303a and 303b are turned on, pulling down the potential of the first reference signal to the second voltage value Vss. Since the third terminal of the third switch transistor is connected to ground potential, the second voltage value Vss can also be called ground potential.

[0091] In addition, by controlling the number of third switching transistors in the on state, the speed of voltage pull-down can also be controlled, thereby reducing the noise generated when the signal level decreases during signal amplification.

[0092] In some embodiments, such as Figure 4A or Figure 4B As shown, the power consumption control circuit 21 also includes a control signal generation circuit 213; wherein,

[0093] The control signal generation circuit includes multiple first inverters (e.g., first inverter 321a, first inverter 321b, first inverter 321c, first inverter 321d), and the first inverters are used to receive initial control signals (e.g., initial control signals IDD3P0, IDD3P1, IDD3P2, IDD3P3) and generate power consumption control signals (e.g., first power consumption control signal pdn3, first power consumption control signal pdn2, second power consumption control signal pdn1, second power consumption control signal pdn0).

[0094] In other words, in these first inverters, one first inverter is used to output a first power consumption control signal or to output a second power consumption control signal. Correspondingly, in the plurality of first inverters, the first power consumption control signal of each first control sub-circuit is output through one first inverter, and the second power consumption control signal of each second control sub-circuit is output through one first inverter.

[0095] It should be noted that Figure 4a shows four first inverters, but in actual applications, there may be more or fewer first inverters. Additionally, there are multiple initial control signals, with one initial control signal input to one first inverter. Here, the different initial control signals can have different voltage levels. In other words, one first inverter is controlled by a single initial control signal.

[0096] For example, when both the initial control signal IDD3P0 and the initial control signal IDD3P1 are in the second level state, the first inverter 321a outputs the second power consumption control signal pdn0 in the first level state, and the first inverter 321b outputs the second power consumption control signal pdn1 in the first level state, thereby turning on the third switch 303a and the third switch 303b, and pulling down the first reference signal to the second voltage value Vss.

[0097] Conversely, when the initial control signals IDD3P0 and IDD3P1 are both at the first level, and the initial control signals IDD3P2 and IDD3P3 are both at the second level, the first inverter 321a outputs the second power consumption control signal pdn0 at the second level, the first inverter 321b outputs the first power consumption control signal pdn1 at the second level, the first inverter 321c outputs the first power consumption control signal pdn2 at the first level, and the first inverter 321d outputs the second power consumption control signal pdn3 at the first level. This turns on the first switches 301a and 301b, while turning off the third switches 303a and 303b. The first reference signal is pulled down to the first voltage value Vt. At this time, the source-drain voltage difference of the first switch 301a decreases, the current flowing through the first switch 301a also decreases, and the power of the first switch 301a is reduced relative to the third switch 303a. The power of the first switch 301b is also reduced compared to the third switch 303b.

[0098] It should also be noted that, such as Figure 4A or Figure 4B As shown, the input of the first inverter is also connected to the power supply signal Vncsg. When the initial control signal is in the second level state, the second inverter outputs a power consumption control signal in the first level state according to the power supply signal Vncsg; when the initial control signal is in the first level state, the second inverter outputs a power consumption control signal in the second level state. See also... Figure 5 The diagram illustrates a schematic representation of an inverter provided in an embodiment of this disclosure. Figure 5 As shown in (a), the first inverter 321a can be implemented by an N-type field-effect transistor and a P-type field-effect transistor.

[0099] In this way, the first control circuit and the second control circuit can control the first reference signal to be pulled down to a first voltage value or a second voltage value, so as to optimize the subsequent signal processing process and reduce circuit power consumption.

[0100] In some embodiments, such as Figure 3 As shown, the control amplifier circuit 20 also includes a reference control circuit 24;

[0101] Reference control circuit 24 is used to determine a reference control signal and output a second reference signal according to the reference control signal;

[0102] The amplifier circuit 23 is also used to receive the first reference signal, the second reference signal, the isolation control signal and the signal to be processed, and to process the signal to be processed based on the first reference signal, the second reference signal and the isolation control signal to obtain the target amplified signal shown.

[0103] It should be noted that the first reference signal can provide a low reference potential for the amplifier circuit 23, and the second reference signal can provide a high reference potential for the amplifier circuit 23, so that the amplifier circuit 23 can amplify the signal to be processed according to the high reference potential and the low reference potential.

[0104] It should be understood that when the first reference signal is used as a low reference potential, its specific voltage value can be either a first voltage value Vt or a second voltage value Vss. Since the first voltage value Vt is higher than the second voltage value Vss, the source-drain voltage difference of the first switching transistor 301a decreases, and the current flowing through the first switching transistor 301a is also lower than the current flowing through the third switching transistor 303a. This reduces the operating current of the first control circuit when maintaining one end of the amplifier circuit 23 at a low reference potential, allowing the amplifier circuit 23 to save some power consumption during signal amplification.

[0105] In one specific embodiment, in Figure 3 Based on this, see Figure 6A This illustrates a schematic diagram of a reference control circuit 24 provided in an embodiment of the present disclosure. Figure 6A As shown, the reference control circuit 24 includes multiple third control sub-circuits (e.g., third control sub-circuit 241a, third control sub-circuit 241b, third control sub-circuit 241c), and each third control sub-circuit includes a fourth switch (e.g., fourth switch 304a, fourth switch 304b, fourth switch 304c); wherein,

[0106] One end of the fourth switch is connected to a reference control signal (e.g., reference control signal pup1, reference control signal pup2, reference control signal pup3), the second end of the fourth switch is connected to a first preset power supply (e.g., first preset power supply Vblh1, first preset power supply Vblh2, first preset power supply Vblh3), and the third end of the fourth switch is used to output a second reference signal PCS.

[0107] It should be noted that, Figure 6A The diagram shows three third control sub-circuits, but in practical applications, there may be more or fewer fourth switching transistors. Additionally, there are multiple reference control signals, with one reference control signal corresponding to one third control sub-circuit. The level states of these multiple reference control signals can be different; that is, the level states of reference control signals pup1, pup2, and pup3 change independently. In other words, one third control sub-circuit is controlled by a single reference control signal.

[0108] like Figure 6A As shown, the fourth switch can be an N-type field-effect transistor. Therefore, taking the fourth switch 304a as an example, when the reference control signal pup1 is in the second level state, the fourth switch 304a is off; when the reference control signal pup1 is in the first level state, the fourth switch 304a is on, and the on-state fourth switch will charge the second reference signal PCS according to the first preset power supply Vblh1, thereby providing a high reference potential for the second level state.

[0109] It should be noted that each of the different fourth switches is connected to a separate first preset power supply, and the voltage values ​​of these first preset power supplies can be different to provide different voltage rise rates for the second reference signal PCS. Furthermore, the voltage rise rate can also be controlled by controlling the number of fourth switches in the on state. Thus, by controlling different voltage rise rates, noise generated when the signal level rises during signal amplification can be reduced.

[0110] In another specific embodiment, Figure 3 Based on this, see Figure 6B This illustrates a schematic diagram of another reference control circuit 24 provided in an embodiment of this disclosure. For example... Figure 6B As shown, the reference control circuit 24 includes multiple signal processing sub-circuits (e.g., signal processing sub-circuit 242a, signal processing sub-circuit 242b, signal processing sub-circuit 242c) and multiple third control sub-circuits (e.g., third control sub-circuit 241a, third control sub-circuit 241b, third control sub-circuit 241c); wherein,

[0111] The signal processing sub-circuit includes multiple second inverters (e.g., second inverter 322a, second inverter 322b, second inverter 322c), and the second inverters are used to receive initial reference signals (e.g., initial reference signal Vpu1, initial reference signal Vpu2, initial reference signal Vpu3) and generate reference control signals (e.g., reference control signal pup1, reference control signal pup2, reference control signal pup3).

[0112] The third control sub-circuit includes a fourth switch (e.g., fourth switch 304a, fourth switch 304, fourth switch 304c). The first terminal of the fourth switch is connected to a reference control signal, the second terminal of the fourth switch is connected to a first preset power supply (e.g., first preset power supply Vblh1, first preset power supply Vblh2, first preset power supply Vblh3), and the third terminal of the fourth switch is used to output a second reference signal PCS.

[0113] Here, multiple signal processing sub-circuits and multiple third control sub-circuits correspond one-to-one.

[0114] In other words, the reference control signal is obtained from the initial control signal via a second inverter to match the control logic in different application scenarios. Put simply, an initial reference signal is input to a second inverter, which outputs a reference control signal, which is then individually input to a fourth switch.

[0115] Taking the fourth switch 304a as an example, when the initial control signal Vpu1 is at the first level and the reference control signal pup1 is at the second level, the fourth switch 304a is off; when the initial control signal Vpu1 is at the second level and the reference control signal pup1 is at the first level, the fourth switch 304a is on. Thus, the on-state fourth switch will charge the second reference signal PCS according to the first preset power supply Vblh1, thereby providing a high reference potential for the amplifier circuit 23.

[0116] The first and second reference signals are also connected to a fourth preset power supply, which can maintain the first and second reference signals at reference voltage values ​​when both the power consumption control signal and the power consumption control signal are in the second level state. Specifically, the first voltage value is lower than the reference voltage value, and the first voltage value is lower than half of the fourth voltage value, to ensure the accuracy of data reading.

[0117] It should be noted that, as Figure 6BAs shown, the input of the third inverter is also connected to the power supply signal Vpcsg. When the initial control signal is at the second level, the second inverter outputs a reference control signal at the first level based on the power supply signal; when the initial control signal is at the first level, the second inverter outputs a reference control signal at the second level. Figure 5 As shown in (b), the second inverter 322a can be implemented by an N-type field-effect transistor and a P-type field-effect transistor.

[0118] In some embodiments, such as Figure 3 As shown, the isolation circuit 22 includes a first signal determination circuit 221, a power output circuit 222, a second signal determination circuit signal 223, and an isolation control circuit 224; wherein,

[0119] The first signal determination circuit 221 is used to output a first power switching signal and / or a second power switching signal according to the preset operation command after receiving the preset operation command.

[0120] The power output circuit 222 is used to output an isolation power value according to the first power switching signal and / or the second power switching signal;

[0121] The second signal determination signal 223 is used to output a control command signal according to the preset operation command after receiving the preset operation command;

[0122] The isolation control circuit 224 is used to receive the isolation power supply value and control command signal, and generate the isolation control signal.

[0123] It should be noted that, taking DRAM as an example, the default operation command can be a read command, a write command, or a refresh command.

[0124] It should be noted that the isolation control signal is generated based on the isolation power supply value and preset operation instructions, and the voltage magnitude of the isolation power supply value can be determined based on the first power switching signal and / or the second power switching signal. Figure 3 The signal is represented in the middle and determined as a power switching signal.

[0125] In this way, the isolation power supply value can be controlled by the power switching signal. Subsequently, the specific voltage value of the isolation power supply can be adjusted by changing the power switching signal, thereby adjusting the specific voltage value of the isolation control signal, optimizing the signal amplification process, and partially improving the problems of slow signal amplification speed and easy noise generation.

[0126] The following example, taking the power switching signal as including both a first power switching signal and a second power switching signal, provides a feasible structure for a power output circuit 21.

[0127] In some embodiments, the power output circuit is configured to determine that the isolation power supply value has a third voltage value when the first power switching signal has a second level state and the second power switching signal has a first level state; or to determine that the isolation power supply value has a fourth voltage value when the first power switching signal has a first level state and the second power signal has a second level state.

[0128] Here, both the third and fourth voltage values ​​belong to the first level state, and the third voltage value is greater than the fourth voltage value.

[0129] In this way, the power output circuit 21 can output two different isolated power supply values, instead of a single fixed voltage power signal. Thus, at different operating stages of the amplifier circuit 23, more control methods can be provided by adjusting the voltage value of the isolated power supply, thereby partially improving the problems of slow signal amplification speed and high circuit noise.

[0130] In some embodiments, the isolation control circuit is specifically configured to determine that the isolation control signal has a third voltage value when the control command signal has a first level state and the isolation power supply value has a third voltage value; or

[0131] When the control command signal has a first level state and the isolation power supply value has a fourth voltage value, it is determined that the isolation control signal has a fourth voltage value; or

[0132] When the control command signal has a second level state, it is determined that the isolation control signal has a fifth voltage value;

[0133] Among them, the fifth voltage value belongs to the second level state, and the fifth voltage value is less than the fourth voltage value.

[0134] It should be noted that, for the isolation circuit 22, when the control command signal is in the first level state, the isolation control signal is in the first level state, and the voltage value of the isolation control signal is the same as that of the isolation voltage value; when the control command signal is in the second level state, the control command signal is in the second level state, or in other words, the control command signal has a fifth voltage value.

[0135] For example, in a conventional representation, the third and fourth voltage values ​​can both be represented as logic "1", and the fifth voltage value can be represented as logic "0". The above is merely illustrative and does not constitute any actual limitation.

[0136] In this way, the isolation control signal has three different voltage values, which can provide more control methods to optimize the signal amplification process and improve the problems of slow signal amplification speed and high circuit noise.

[0137] exist Figure 3 Based on this, see Figure 7 This illustrates a schematic diagram of an isolation circuit 22 provided in an embodiment of this disclosure. For example... Figure 7 As shown, the power output circuit 222 may include a second preset power supply VisoH, a third preset power supply VisoL, a fifth switching transistor 305, and a sixth switching transistor 306; wherein,

[0138] The first terminal of the fifth switching transistor 305 is connected to the first power switching signal, and the first terminal of the sixth switching transistor 306 is connected to the second power switching signal.

[0139] The second terminal of the fifth switch 305 is connected to the second preset power supply VisoH, and the second terminal of the sixth switch 306 is connected to the third preset power supply VisoL.

[0140] The third terminal of the fifth switch 305 is connected to the third terminal of the sixth switch 306 to output the isolation power supply value VisoInt.

[0141] Here, the second preset power supply VisoH is used to output the third voltage value, and the third preset power supply VisoL is used to output the fourth voltage value.

[0142] It should be noted that, as Figure 7 As shown, the fifth switch 305 and the sixth switch 306 are both P-type field-effect transistors. In the following description, the first terminal of the P-type field-effect transistor is the gate pin, the second terminal is the source pin, and the third terminal is the drain pin.

[0143] It should be noted that when the first power switching signal is at the second level and the second power switching signal is at the first level, the fifth switch 305 is turned on and the sixth switch 306 is turned off. Therefore, the isolation power supply value VisoInt is the same as the voltage value of the second preset power supply VisoH, that is, the isolation power supply value VisoInt is the third voltage value. When the first power switching signal is at the first level and the second power switching signal is at the second level, the fifth switch 305 is turned off and the sixth switch 306 is turned on. Therefore, the isolation power supply value VisoInt is the same as the voltage value of the third preset power supply VisoL, that is, the isolation power supply value VisoInt is the fourth voltage value.

[0144] In some embodiments, such as Figure 7 As shown, the isolation control circuit 224 may include a third inverter 323, a seventh switch 307, and an eighth switch 308; wherein,

[0145] The input terminal of the third inverter 323 is connected to the output terminal of the second signal determination circuit 223 to receive the control command signal output by the second signal determination circuit 223. The output terminal of the third inverter 323 is connected to the first terminal of the seventh switch 307 and the first terminal of the eighth switch 308 respectively.

[0146] The second terminal of the seventh switch 307 is connected to the isolation power supply value VisoInt, and the third terminal of the eighth switch 308 is connected to the ground signal.

[0147] The third terminal of the seventh switch 307 is connected to the second terminal of the eighth switch 308 to output the isolation control signal Iso.

[0148] It should be noted that the seventh switch 307 is a P-type field-effect transistor, and the eighth switch 308 is an N-type field-effect transistor.

[0149] Thus, when the control command signal is at the first level, the seventh switch 307 is in the on state and the eighth switch 308 is in the off state, so the voltage value of the isolation control signal Iso is the same as the voltage value VisoInt of the isolation power supply, that is, the third voltage value or the fourth voltage value; when the control command signal is at the second level, the seventh switch 307 is in the off state and the eighth switch 308 is in the on state, so the isolation control signal Iso has a fifth voltage value, which is equivalent to the ground potential.

[0150] Thus, in this embodiment of the present disclosure, under the premise that the isolation control signal Iso is in the first level state, the isolation control signal Iso can also be controlled to be a higher voltage (third voltage value) or a lower voltage (fourth voltage value) to adapt to the voltage requirements and signal transmission speed of different amplification stages, thereby optimizing the signal amplification process, improving the signal amplification speed, and reducing circuit noise.

[0151] Taking DRAM as an example, amplifier circuit 23 also needs to be connected to bit lines / complementary bit lines. Initially, the potentials on the bit lines and complementary bit lines are the same. After a memory cell on a bit line is turned on, the cell shares charge with the bit line, causing the potential on the bit line to rise or fall, forming the signal to be processed. Simultaneously, the memory cell on the complementary bit line is always off, so its potential remains unchanged, forming a reference signal to be processed. Due to the rise and fall of the potential on the bit lines, the voltage difference between the bit lines and complementary bit lines changes, causing some devices in amplifier circuit 23 to turn on, amplifying the signal to be processed to obtain the target amplified signal.

[0152] When amplifier circuit 23 begins amplification, it sets the isolation control signal Iso to the fourth voltage value, causing the voltage rise of the bit line or complementary bit line to be slow, thus preventing significant noise from affecting the stored data of adjacent memory cells. This increases the sensing amplitude of amplifier circuit 23, while the internal nodes of amplifier circuit 23 can quickly reach the low or high reference potential. In subsequent amplification stages, the isolation control signal Iso is set to the third voltage value, increasing the voltage flowing through the bit line or complementary bit line. Since the voltage of the internal nodes of amplifier circuit 23 has changed, it quickly pulls the bit line or complementary bit line high or low, increasing the signal amplification speed and suppressing noise when the potential of the bit line or complementary bit line rises.

[0153] Subsequently, amplifier circuit 23 completes the signal amplification process; see subsequent sections for details.

[0154] Based on this, in a specific implementation, in Figure 3 Based on this, see Figure 8 This illustrates a schematic diagram of the structure of an amplifier circuit 23 provided in an embodiment of this disclosure. For example... Figure 8 As shown, the amplifier circuit 23 may include a ninth switch 309, a tenth switch 310, an eleventh switch 311 and a twelfth switch 312, and the control circuit 232 includes a thirteenth switch 313 and a fourteenth switch 314.

[0155] The first terminal of the ninth switch 309 is connected to the third terminal of the thirteenth switch 313 for receiving the signal to be processed. The second terminal of the ninth switch 309, the third terminal of the eleventh switch 311, the first terminal of the twelfth switch 312, and the second terminal of the fourteenth switch 314 are connected.

[0156] The first terminal of the tenth switch 310 is connected to the third terminal of the fourteenth switch 314 to receive a reference signal to be processed. The second terminal of the tenth switch 310, the third terminal of the twelfth switch 312, the first terminal of the eleventh switch 311, and the second terminal of the thirteenth switch 313 are connected.

[0157] The third terminal of the ninth switch 309 and the third terminal of the tenth switch 310 are connected to the first reference signal NCS. The second terminal of the eleventh switch 311 and the second terminal of the twelfth switch 312 are connected to the second reference signal PCS. The first terminal of the thirteenth switch 313 and the first terminal of the fourteenth switch 314 are connected to the isolation control signal Iso.

[0158] It should be noted that the ninth switch 309, the tenth switch 310, the thirteenth switch 313 and the fourteenth switch 314 are N-type field-effect transistors, while the eleventh switch 311 and the twelfth switch 312 are P-type field-effect transistors.

[0159] Thus, when the isolation control signal Iso is at the first level (with a third or fourth voltage value), the thirteenth switch 313 and the fourteenth switch 314 are turned on, and when the isolation control signal Iso is at the second level (with a fifth voltage value), the thirteenth switch 313 and the fourteenth switch 314 in the control circuit 232 are turned off.

[0160] During signal amplification, the amplifier circuit 23 operates at different stages, requiring the transmission of the signal to be processed and the reference signal to be processed to the amplifier circuit 23 via the isolation control signal Iso to accelerate the amplification process. Therefore, the isolation control signal Iso affects the signal amplification process. The isolation control signal Iso provided in this embodiment has three voltage values. By adjusting the voltage values ​​of the isolation control signal Iso to suit the amplifier circuit 23 at different operating stages, the signal amplification process can be optimized, thereby improving the problems of slow signal amplification speed and high circuit noise.

[0161] In some embodiments, such as Figure 8 As shown, the amplifier circuit 23 also includes a pre-charging circuit, which includes a fifteenth switch 315 and a sixteenth switch 316; wherein,

[0162] The first terminal of the fifteenth switch 315 and the first terminal of the sixteenth switch 316 are connected to the precharge signal Eq;

[0163] The second terminal of the fifteenth switch 315 is connected to the fourth preset power supply, and the third terminal of the fifteenth switch 315 is connected to the second terminal of the tenth switch 310.

[0164] The third terminal of the sixteenth switch 316 is connected to the second terminal of the ninth switch 309, and the second terminal of the sixteenth switch 316 is connected to the second terminal of the tenth switch 310.

[0165] Here, both the fifteenth switch 315 and the sixteenth switch 316 are N-type field-effect transistors.

[0166] In this way, the pre-charging circuit responds to the pre-charging signal Eq and performs pre-charging processing on the amplifier circuit 23 according to the fourth preset power supply. After the pre-charging processing is completed, the circuit nodes of the amplifier circuit 23 are at the same reference voltage value.

[0167] In some embodiments, Figure 8 On the basis of, such as Figure 9 As shown, the amplifier circuit 23 also includes a noise cancellation circuit, which includes a seventeenth switching transistor 317 and an eighteenth switching transistor 318; wherein,

[0168] The first terminal of the seventeenth switch 317 and the first terminal of the eighteenth switch 318 are connected to the noise cancellation signal Nc;

[0169] The second terminal of the seventeenth switch 317 is connected to the second terminal of the ninth switch 309, and the third terminal of the seventeenth switch 317 is connected to the first terminal of the ninth switch 309.

[0170] The second terminal of the eighteenth switch 318 is connected to the second terminal of the tenth switch 310, and the third terminal of the eighteenth switch 318 is connected to the first terminal of the tenth switch 310.

[0171] Here, both the seventeenth switch 317 and the eighteenth switch 318 are N-type field-effect transistors. Therefore, when the noise cancellation signal is at the first level, the seventeenth switch 317 and the eighteenth switch 318 are turned on, shorting the first and third terminals of the ninth switch 309 and the tenth switch 310. This controls the first reference signal NCS to be at the first voltage value Vt and the second reference signal PCS to be at a high reference potential, thereby performing offset cancellation operation on the ninth switch 309 and the tenth switch 310. In this way, the threshold difference of the switches during signal amplification can be further eliminated, improving the accuracy of signal sensing during amplification.

[0172] In particular, Figures 3-9 This is merely an exemplary structure for controlling the amplifier circuit, wherein the fifth switch 305, the sixth switch 306, the seventh switch 307, the eleventh switch 311, and the twelfth switch 312 are P-channel field-effect transistors;

[0173] The first switch 301, the second switch 302, the third switch 303, the fourth switch 304, the eighth switch 308, the ninth switch 309, the tenth switch 310, the thirteenth switch 313, the fourteenth switch 314, the fifteenth switch 315, the sixteenth switch 316, the seventeenth switch 317, and the eighteenth switch 318 are N-channel field-effect transistors;

[0174] Wherein, the first terminal of the P-type field-effect transistor is the gate terminal, the second terminal of the P-type field-effect transistor is the source terminal, and the third terminal of the P-type field-effect transistor is the drain terminal; the first terminal of the N-type field-effect transistor is the gate terminal, the second terminal of the N-type field-effect transistor is the drain terminal, and the third terminal of the N-type field-effect transistor is the source terminal.

[0175] Of course, the selection of the above-mentioned switching transistors does not constitute a limitation of the embodiments of this disclosure. In actual application scenarios, the aforementioned circuit control logic can be implemented by various types of circuit devices, and specific selection can be made according to the actual application scenario.

[0176] This disclosure provides a control amplifier circuit. On one hand, by adding a power consumption control circuit, the first reference signal can be a larger voltage value (first voltage value Vt) or a smaller voltage value (second voltage value Vss) while remaining at a low reference potential. The voltage value of the first reference signal can be adjusted according to the operating stage of the amplifier circuit to reduce power consumption. On the other hand, by adding a power switching circuit, an isolation power supply value with two voltage values ​​is provided. The isolation control circuit can then output an isolation control signal with three different voltage values ​​(a third voltage value, a fourth voltage value, or a fifth voltage value) based on the isolation power supply value. When the amplifier circuit is not in operation, the voltage of the isolation power supply value can be reduced to the second voltage value to reduce leakage current in the switching transistor of the isolation control circuit, prevent switching transistor failure, and extend the service life of the isolation control circuit. Furthermore, by adjusting the voltage value of the isolation control signal to the third or fourth voltage value at different stages of amplifier circuit operation, the voltage change speed of the isolation control circuit is accelerated, optimizing the signal amplification process and improving the problems of slow signal amplification speed and high circuit noise.

[0177] In another embodiment of this disclosure, see Figure 10 This illustration shows a schematic diagram of an application scenario for a control amplifier circuit 20 provided in an embodiment of this disclosure. For example... Figure 10 As shown, in this application scenario, there are bit line Bla, complementary bit line Blb, readout bit line saBla, complementary readout bit line saBlb, and control amplifier circuit 20. A first storage cell 41 is provided on bit line Bla, and a second storage cell 42 is provided on complementary bit line Blb.

[0178] The control amplifier circuit 20 includes a power consumption control circuit 21, an isolation circuit 22, an amplifier circuit 23, and a reference control circuit 24. The power consumption control circuit 21 includes multiple first switching transistors (e.g., first switching transistors 301 and 301b), multiple second switching transistors (e.g., second switching transistors 302a and 302b), multiple switches, multiple third switching transistors (e.g., third switching transistors 303a and 303b), and multiple first inverters (e.g., first inverters 321a, 321b, 321c, and 321d). The reference control circuit 24 includes multiple fourth switching transistors (e.g., fourth switching transistors 304a, 304b, and 304c) and multiple second inverters (e.g., second inverters 322a, 322b, and 322c). The isolation circuit 22 includes a first signal determination circuit 221, a second signal determination circuit 223, a second preset power supply VisoH, a third preset power supply VisoL, a fifth switch 305, a sixth switch 306, a seventh switch 307, an eighth switch 308, and a third inverter 323. The amplifier circuit 24 includes a ninth switch 309, a tenth switch 310, an eleventh switch 311, a twelfth switch 312, a thirteenth switch 313, a fourteenth switch 314, a fifteenth switch 315, and a sixteenth switch 316.

[0179] The second terminal of the tenth switch 310, the third terminal of the twelfth switch 312, the first terminal of the eleventh switch 311, and the second terminal of the thirteenth switch 313 are all connected to the readout bit line saBla. The second terminal of the ninth switch 309, the third terminal of the eleventh switch 311, the first terminal of the twelfth switch 312, and the second terminal of the fourteenth switch 314 are all connected to the complementary readout bit line saBlb.

[0180] The third terminal of the thirteenth switch 313 is connected to the first terminal of the ninth switch 309 on the bit line Bla. The first terminal of the tenth switch 310 is connected to the third terminal of the fourteenth switch 314 on the complementary bit line Blb. The thirteenth switch 313 connects the bit line Bla to the read bit line saBla in response to the isolation control signal Iso. The fourteenth switch 314 connects the complementary bit line Blb to the complementary read bit line saBlb in response to the isolation control signal Iso.

[0181] The third terminal of the fifteenth switch 315 is connected to the complementary read bit line saBlb, the third terminal of the sixteenth switch 316 is connected to the read bit line saBla, and the second terminal of the sixteenth switch 316 is connected to the complementary read bit line saBlb. In response to the equalization signal Eq, the bit line Bla, the complementary bit line Blb, the read bit line saBla, and the complementary read bit line saBlb are equalized to the reference voltage value.

[0182] In this application scenario, the types and connections of the various devices are as follows: Figure 9 As shown, and Figure 9 For the meanings of the symbols and the working principles of the circuit, please refer to the aforementioned content, which will not be repeated here.

[0183] exist Figure 10 Based on this, see Figure 11 This illustrates a schematic diagram of an application scenario for another control amplifier circuit 20 provided in an embodiment of this disclosure. For example... Figure 11 As shown, the amplifier circuit also includes a seventeenth switch 317 and an eighteenth switch 318. The second terminal of the seventeenth switch 317 is connected to the complementary readout bit line saBlb, and the third terminal of the seventeenth switch 317 is connected to the bit line Bla. The second terminal of the eighteenth switch 318 is connected to the readout bit line saBla, and the third terminal of the eighteenth switch 318 is connected to the complementary bit line Blab. In response to the offset cancellation signal Nc, offset cancellation operation is performed on the ninth switch 309 and the tenth switch 310 by controlling the first reference signal NCS to be at the first voltage value Vt and the second reference signal PCS to be at a high reference potential.

[0184] In simple terms, the power consumption control circuit 21 outputs a first reference signal NCS as a low reference potential to the amplifier circuit 23, and the reference control circuit 24 outputs a second reference signal PCS as a high reference potential to the amplifier circuit 23. The isolation circuit 22 outputs an isolation control signal Iso to the amplifier circuit 23. The amplifier circuit amplifies the signal to be processed according to the isolation control signal Iso, the first reference signal NCS, and the second reference signal PCS to obtain the target amplified signal. In addition, the reference control circuit 24 also performs a pre-charge operation in response to the pre-charge signal and an offset cancellation operation in response to the noise cancellation signal.

[0185] Here, the first reference signal NCS can have a first voltage value Vt or a second voltage value Vss when it is a low reference potential, the isolation control signal can have a fourth voltage value or a third voltage value when it is in the first level state, and the isolation control signal can have a fifth voltage value when it is in the second level state.

[0186] It should be understood that during the signal amplification process, the amplifier circuit 23 has different operating stages. The level states of each signal (such as isolation control signal Iso / precharge signal Eq / noise cancellation signal Nc / first reference signal NCS / second reference signal PCS, etc.) are different in different operating stages so that the amplifier circuit 23 can perform different tasks.

[0187] For example, with Figure 11Taking the control amplifier circuit as an example, the amplifier circuit 23 processes the signal to be processed, including: standby stage, noise cancellation stage, first charge sharing stage, second charge sharing stage, signal amplification stage, signal write-back stage, signal stabilization stage and pre-charge stage;

[0188] If amplifier circuit 23 is in the second charge sharing stage, signal amplification stage, or pre-charge stage, then the isolation control signal maintains a third voltage value; or

[0189] If amplifier circuit 23 is in standby or signal write-back stage, the isolation control signal maintains a fourth voltage value; or

[0190] If the amplifier circuit 23 is in the noise cancellation stage or the first charge sharing stage, the isolation control signal will have a fifth voltage value.

[0191] In some embodiments, when the amplifier circuit 23 is in the signal write-back stage, the first power consumption control signal is in the first level state and the second power consumption control signal is in the second level state; when the amplifier circuit 23 is in the standby stage, noise cancellation stage, first charge sharing stage, second charge sharing stage, signal amplification stage, or pre-charge stage, the first power consumption control signal is in the second level state.

[0192] In this way, on the one hand, by adjusting the isolation control signal to have different voltage values, the signal processing process can be optimized, and the problems of slow signal amplification speed and high circuit noise can be improved; on the other hand, by adjusting the first power consumption control signal and the second power consumption control signal, the voltage value of the first reference signal can be controlled, thereby reducing circuit power consumption.

[0193] The following explains the working principle of amplifier circuit 23 in each working stage and the specific changes of each signal.

[0194] exist Figure 11 Based on this, see Figure 12 This illustrates a signal timing diagram of an amplifier circuit provided in an embodiment of the present disclosure. Figure 12In this context, VisoInt refers to the aforementioned isolation power supply value, which can be the third voltage value VisoH or the fourth voltage value VisoL; Iso refers to the aforementioned isolation control signal, which can be the fifth voltage value Vss, the third voltage value VisoH, or the fourth voltage value VisoL; Eq refers to the aforementioned precharge signal; Nc refers to the aforementioned noise cancellation signal; SanEn1 refers to the aforementioned first power consumption control signal; SanEn2 refers to the aforementioned second power consumption control signal; SapEn refers to the aforementioned reference control signal; WL is the memory cell enable signal. When WL is at the first level, the memory cell is connected to the bit line; when WL is at the second level, the memory cell is not connected to the bit line; NCS / PCS refers to the first reference signal / second reference signal. The first reference signal has a reference voltage value, a first voltage value Vt, or a second voltage value Vss, and both the first voltage value Vt and the second voltage value Vss can be called a low reference potential. The second reference signal has a reference voltage value or a high reference potential; Bla refers to the bit line; and Blb refers to the complementary bit line.

[0195] When amplifier circuit 23 is in standby mode, the isolation power supply value VisoInt maintains the fourth voltage value VisoL, the isolation control signal Iso maintains the fourth voltage value VisoL, the precharge signal Eq and the noise cancellation signal Nc are at the first level, and the first power consumption control signal SanEn1, the second power consumption control signal SanEn2, the reference control signal SapEn, and the word line enable signal WL are all at the second level. At this time, the thirteenth switch 313 to the eighteenth switch 318 are turned on, so that the fourth preset power supply charges amplifier circuit 23, so that the node voltages, bit lines BLa, complementary bit lines BLb, readout bit lines saBLa, complementary readout bit lines saBLb, first reference signal NCS and second reference signal PCS in amplifier circuit 23 are all reference voltage values, and the reference voltage values ​​are at the low reference potential and the high reference potential, which prepares for the subsequent execution of preset operation instructions.

[0196] Upon receiving the preset operation command, the amplifier circuit 23 enters the noise cancellation stage. The isolation control signal Iso is adjusted to the fifth voltage value Vss, thereby turning off the thirteenth switch 313 and the fourteenth switch 314. Simultaneously, the precharge signal Eq is adjusted to the second level, turning off the fifteenth switch 315 and the sixteenth switch 316. The noise cancellation signal Nc remains at the first level, so the seventeenth switch 317 and the eighteenth switch 318 are turned on. The reference control signal SapEn and the second power consumption control signal SanEn2 are first adjusted from the second level to the first level, turning on the third switch 303a and the fourth switch 304a. This achieves the first reference signal NCS at the second voltage value Vss and the second reference signal PCS at a high reference potential, thereby performing offset cancellation processing on the ninth switch 309 and the tenth switch 310, eliminating the threshold voltage difference between them. Furthermore, during the noise cancellation stage, the second power consumption control signal SanEn2 remains at the second level. Specifically, during this stage, the isolation power supply value VisoInt is adjusted to the third voltage value in advance, which can speed up the isolation control signal Iso when the voltage increases, thereby improving the signal processing speed.

[0197] The following explanation uses the 41-bit preset operation instruction of the first storage unit as an example.

[0198] After the noise cancellation phase ends, the reference control signal SapEn and the second power consumption control signal SanEn2 are first adjusted to the second level state, and the first reference signal NCS and the second reference signal PCS are adjusted to the reference voltage value. The amplifier circuit 23 enters the first charge sharing phase, and the memory cell enable signal WL is adjusted to the first level state, indicating that the first memory cell 41 is enabled to share charge with the bit line Bla, generating the signal to be processed. Figure 12 As shown, during this stage, a signal to be processed is generated on bit line Bla. Simultaneously, since the second memory cell 42 is not turned on, the complementary bit line Blb maintains its reference voltage value, indicating the presence of a reference signal to be processed on the complementary bit line Blb. During this process, the isolation control signal Iso maintains the fifth voltage value Vss, and the thirteenth switch 313 and the fourteenth switch 314 are turned off. Therefore, bit line Bla is not connected to the read bit line saBla, and the complementary bit line Blb is not connected to the complementary read bit line saBlb, avoiding interference with charge sharing between the first memory cell 41 and bit line Bla. Furthermore, the precharge signal Eq, noise cancellation signal Nc, first power control signal SanEn1, second power control signal SanEn2, and reference control signal SapEn remain at their second level. Both the first reference signal NCS and the second reference signal PCS have reference voltage values.

[0199] After the first charge sharing phase ends, the amplifier circuit 23 enters the second charge sharing phase. The isolation control signal Iso is adjusted to the third voltage value VisoH, and the thirteenth switch 313 and the fourteenth switch 314 are turned on, thereby connecting the bit line Bla with the read bit line saBla, and connecting the complementary bit line Blb with the complementary read bit line saBlb. Thus, the bit line Bla and the read bit line saBla share charge, and the complementary bit line Blb and the complementary read bit line saBlb share charge. The amplifier circuit 23 receives the signal to be processed from the bit line Bla, and also receives the reference signal to be processed from the complementary bit line Blb. In addition, the precharge signal Eq, the noise cancellation signal Nc, the first power consumption control signal SanEn1, the second power consumption control signal SanEn2, and the reference control signal SapEn remain at the second level. The first reference signal NCS and the second reference signal PCS both have reference voltage values.

[0200] After the second charge sharing phase ends, the control amplifier circuit 20 enters the signal amplification phase. The second power consumption control signal SanEn2 and the reference control signal SapEn are adjusted to the first level state, so that the first reference signal NCS drops from the reference voltage value to the second voltage value Vss (low reference potential), and the second reference signal PCS rises from the reference voltage value to the high reference potential. The amplifier circuit 23 amplifies the signal to be processed according to the first reference signal NCS and the second reference signal PCS, pulling the voltage value of the signal to be processed up or down to obtain the target amplified signal. In addition, the isolation control signal Iso rises from the fourth voltage value VisoL to the third voltage value VisoH to increase the charge transfer speed, and the precharge signal Eq and the noise cancellation signal Nc are both maintained at the second level state. Figure 12 As shown, during the signal amplification stage, the signal voltage difference between bit line Bla and the complementary bit line Blb increases.

[0201] After the signal amplification stage ends, the amplifier circuit 23 enters the signal write-back stage, mainly recovering the stored data in the first storage cell 41 by the voltage value of the amplified bit line Bla, thus preventing data loss. At this time, the isolation power supply value VisoInt decreases from the third voltage value VisoH to the fourth voltage value VisoL, thereby reducing the isolation control signal Iso from the third voltage value VisoH to the fourth voltage value VisoL. The first power consumption control signal SanEn1 is adjusted from the second level state to the first level state, and the second power consumption control signal SanEn1 is adjusted from the first level state to the second level state, that is, the amplifier circuit 23 enters the power saving mode (or IDD3P mode). At this time, the first reference voltage value NCS is adjusted from the second voltage value Vss to the first voltage value Vt, reducing circuit power consumption.

[0202] After the end signal write-back phase, the memory cell enable signal WL is adjusted to the second level state, indicating that the first memory cell 41 is turned off.

[0203] The power-saving mode can end earlier than the shutdown time of the first memory cell 41, accounting for approximately 80% of the write-back phase. After the power-saving mode ends, the first power consumption control signal SanEn1 changes from the first level to the second level, and the second power consumption control signal SanEn1 changes from the second level to the first level. At this time, the first reference voltage value NCS changes from the first voltage value Vt to the second voltage value Vss. If the target signal is pulled low, due to the low voltage in the bit line Bla and the first memory cell 41, it can quickly change from the second voltage value Vss back to the first voltage value Vt, rapidly restoring the stored data in the first memory cell 41 to its lowest state.

[0204] The power saving mode end time can be equal to the first storage unit 41 shutdown time. The power saving mode ends when the write-back phase ends. If the target signal is pulled low, the voltage in the first storage unit 41 will maintain the first voltage value Vt, which is lower than the reference voltage value, and will not affect the next data read operation.

[0205] When amplifier circuit 23 enters the pre-charge stage, the isolation power supply value VisoInt is first adjusted to the third voltage value VisoH and then drops to the fourth voltage value VisoL. The isolation control signal Iso is first adjusted to the third voltage value VisoH and then drops to the fourth voltage value VisoL, saving power consumption of the thirteenth switch 303 and the fourteenth switch 304 and extending device life. After the isolation control signal is adjusted to the fourth voltage value VisoL, the pre-charge signal Eq and the noise cancellation signal Nc are adjusted to the first level state. At the same time, the first power consumption control signal SanEn1 is adjusted to the second level state. The second power consumption control signal SanEn1 first rises to the first level state and then returns to the second level state. In this way, the first reference signal NCS drops from the first voltage value Vt to the second voltage value Vss and then rises to the reference voltage value. The second reference signal PCS recovers from the high reference potential to the fourth voltage value. The bit line Bla / complementary bit line Blab and the readout bit line saBla / complementary readout bit line saBlb will recover to the reference voltage value.

[0206] After the pre-charge phase ends, the amplifier circuit 23 enters the standby phase again to prepare for the next operation.

[0207] In related technologies, see Figure 13 This illustrates a signal timing diagram provided by related technologies. Because the control amplifier circuit in these related technologies lacks a power consumption control circuit, the first reference signal NCS can only be a voltage value Vss (i.e., a low reference potential) or a reference voltage value. Figure 12In this context, SanEn is the first reference control signal. When SanEn is at its first level, the first reference signal NCS is a low reference potential. When SanEn is at its second level, the first reference signal NCS is a reference voltage value. This is indicated by the first reference control signal SanEn. Figure 13 For the meanings of other signals and the principles governing their changes, please refer to [link / reference]. Figure 12 I understand, so I won't elaborate. For example... Figure 13 As shown, on the one hand, since the first reference signal NCS in the related technology needs to maintain the second voltage value Vss when it is a low reference potential, the circuit power consumption cannot be reduced. On the other hand, since the isolation power supply value (not shown) in the related technology is a fixed voltage value, the isolation control signal Iso has two voltage values, belonging to the first level state and the second level state respectively, resulting in slow signal amplification speed and large circuit noise.

[0208] This disclosure provides a control amplifier circuit and its control method. This embodiment elaborates on the specific implementation of the aforementioned embodiments. It can be seen that, on the one hand, during the pre-charge and standby phases, the isolation power supply value drops to the fourth voltage value VisoL, which can reduce device leakage and failure problems and extend the device's lifespan; during the signal write-back phase, a power-saving mode can be entered, which can reduce device leakage and failure problems and extend the device's lifespan; after entering the power-saving mode, the first reference signal NCS is the first voltage value Vt, so the amplifier circuit 23 only needs to be pulled down to Vt instead of Vss, which can save circuit power consumption; in addition, the power consumption control circuit can also reduce noise during the voltage pull-down process. For example, by first opening the sub-circuit in the first power consumption circuit and then opening the sub-circuit in the second power consumption circuit, the speed of voltage pull-down can be slowed down, reducing noise.

[0209] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 14 This illustrates a schematic diagram of the composition of a sensitive amplifier 60 provided in an embodiment of this disclosure. For example... Figure 14 As shown, the sensitive amplifier 60 may include the control amplifier circuit 20 described in any of the foregoing embodiments.

[0210] Thus, since the sensitive amplifier 60 may include the control amplifier circuit 20 described in any of the foregoing embodiments, the specific voltage value of the first reference signal can be adjusted by setting the power consumption adjustment circuit, thereby reducing the circuit power consumption; at the same time, the specific voltage value of the isolation control signal can be adjusted by the isolation circuit, thereby optimizing the signal amplification process, which not only improves the problem of slow signal amplification speed, but also reduces circuit noise.

[0211] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 15This illustrates a schematic diagram of the structural composition of a semiconductor memory 70 provided in an embodiment of this disclosure. For example... Figure 15 As shown, the semiconductor memory 70 may include the sensitive amplifier 60 described in any of the foregoing embodiments.

[0212] In this embodiment of the disclosure, the semiconductor memory 70 can be a DRAM chip.

[0213] Thus, since the semiconductor memory 70 includes the aforementioned sensitive amplifier 60, and since the sensitive amplifier 60 may include the control amplifier circuit 20 described in any of the preceding embodiments, by setting the power consumption adjustment circuit, the specific voltage value of the first reference signal can be adjusted, thereby reducing the circuit power consumption; at the same time, by using the isolation circuit, the specific voltage value of the isolation control signal can be adjusted, thereby optimizing the signal amplification process, not only improving the problem of slow signal amplification speed, but also reducing circuit noise.

[0214] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0215] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0216] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0217] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0218] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0219] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0220] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A control amplifier circuit, characterized in that, include: A power consumption control circuit is used to receive a power consumption control signal and output a first reference signal according to the power consumption control signal; An isolation circuit is used to determine a control command signal and generate an isolation control signal based on the control command signal. An amplifier circuit is used to receive the first reference signal, the isolation control signal, and the signal to be processed, and to process the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal; The power consumption control circuit includes a first control circuit and a second control circuit, and the power consumption control signal includes a first power consumption control signal and a second power consumption control signal; wherein... The first control circuit is configured to receive the first power consumption control signal and, when the first power consumption control signal is at a first level, output the first reference signal having a first voltage value. The second control circuit is used to receive the second power consumption control signal and output the first reference signal having a second voltage value when the second power consumption control signal is at a first level. Wherein, the first voltage value is higher than the second voltage value; The first control circuit includes at least one first control sub-circuit, and the first control sub-circuit includes a first switching transistor and a second switching transistor; wherein, The first terminal of the first switch is used to receive the first power consumption control signal. The third terminal of the first switch, the first terminal of the second switch, and the second terminal of the second switch are connected. The third terminal of the second switch receives a ground signal, and the second terminals of the second switches in the plurality of the first control sub-circuits are connected to each other. The second terminal of the first switch is used to output the first reference signal.

2. The control amplifier circuit according to claim 1, characterized in that, The amplifier circuit processes the signal to be processed, including a signal amplification stage and a signal write-back stage. When the amplifier circuit is in the signal write-back stage, the first power consumption control signal is in a first level state, and the second power consumption control signal is in a second level state. When the amplifier circuit is in the signal amplification stage, the first power consumption control signal is in the second level state, and the second power consumption control signal is in the first level state.

3. The control amplifier circuit according to claim 2, characterized in that, The amplifier circuit processes the signal to be processed, including a standby phase. When the amplifier circuit is in the standby stage, the first power consumption control signal is in the second level state, and the second power consumption control signal is in the second level state.

4. The control amplifier circuit according to claim 1, characterized in that, A switch is provided between the third terminal of the first switching transistor and the first terminal of the second switching transistor, and the control terminal of the switch receives a power-saving control signal; Specifically, when the first power consumption control signal is at a first level, the switch is controlled to be in a closed state by the power saving control signal.

5. The control amplifier circuit according to claim 3, characterized in that, The second control circuit includes multiple second control sub-circuits, and each second control sub-circuit includes a third switching transistor; wherein, The first terminal of the third switch is used to receive the second power consumption control signal, the third terminal of the third switch is used to receive the ground signal, and the second terminal of the third switch is used to output the first reference signal.

6. The control amplifier circuit according to claim 5, characterized in that, The power consumption control circuit further includes a control signal generation circuit; wherein... The control signal generation circuit includes multiple first inverters, and the first inverters are used to receive an initial control signal and generate a power consumption control signal; wherein, In the plurality of first inverters, the first power consumption control signal of each first control sub-circuit is output through one first inverter, and the second power consumption control signal of each second control sub-circuit is output through one first inverter.

7. The control amplifier circuit according to claim 1, characterized in that, The control amplifier circuit also includes a reference control circuit; The reference control circuit is used to determine a reference control signal and output a second reference signal according to the reference control signal; The amplification circuit is further configured to receive the first reference signal, the second reference signal, the isolation control signal, and the signal to be processed, and to process the signal to be processed based on the first reference signal, the second reference signal, and the isolation control signal to obtain the target amplified signal shown.

8. The control amplifier circuit according to claim 7, characterized in that, The reference control circuit includes multiple third control sub-circuits, and each third control sub-circuit includes a fourth switching transistor; wherein, One end of the fourth switch receives the reference control signal, the second end of the fourth switch is connected to the first preset power supply, and the third end of the fourth switch is used to output the second reference signal.

9. The control amplifier circuit according to claim 7, characterized in that, The reference control circuit includes multiple signal processing sub-circuits and multiple third control sub-circuits; wherein... The signal processing sub-circuit includes a second inverter, which is used to receive an initial reference signal and generate the reference control signal. The third control sub-circuit includes a fourth switch transistor. The first terminal of the fourth switch transistor receives the reference control signal, the second terminal of the fourth switch transistor is connected to a first preset power supply, and the third terminal of the fourth switch transistor is used to output the second reference signal. Among them, the multiple signal processing sub-circuits and the multiple third control sub-circuits correspond one-to-one.

10. The control amplifier circuit according to claim 1, characterized in that, The isolation circuit includes a first signal determination circuit, a power output circuit, a second signal determination circuit, and an isolation control circuit; wherein, The first signal determining circuit is used to output a first power switching signal and / or a second power switching signal according to the preset operation instruction after receiving the preset operation instruction. The power output circuit is used to output an isolation power value according to the first power switching signal and / or the second power switching signal; The second signal determining circuit is used to output the control command signal according to the preset operation command after receiving the preset operation command; The isolation control circuit is used to receive the isolation power supply value and the control command signal, and generate the isolation control signal.

11. The control amplifier circuit according to claim 10, characterized in that, The power output circuit is used to determine that the isolation power value has a third voltage value when the first power switching signal has a second level state and the second power switching signal has a first level state. or When the first power switching signal has a first level state and the second power switching signal has a second level state, it is determined that the isolation power value has a fourth voltage value; Wherein, both the third voltage value and the fourth voltage value belong to the first level state, and the third voltage value is greater than the fourth voltage value.

12. The control amplifier circuit according to claim 11, characterized in that, The isolation control circuit is specifically used to determine that the isolation control signal has a third voltage value when the control command signal has a first level state and the isolation power supply value has a third voltage value. or When the control command signal has a first level state and the isolation power supply value has a fourth voltage value, it is determined that the isolation control signal has a fourth voltage value. or When the control command signal has a second level state, it is determined that the isolation control signal has a fifth voltage value; The fifth voltage value belongs to the second level state, and the fifth voltage value is less than the fourth voltage value.

13. The control amplifier circuit according to claim 12, characterized in that, The power output circuit includes a second preset power supply, a third preset power supply, a fifth switching transistor, and a sixth switching transistor; wherein... The first terminal of the fifth switch receives the first power switching signal, and the first terminal of the sixth switch receives the second power switching signal. The second end of the fifth switch is connected to the second preset power supply, and the second end of the sixth switch is connected to the third preset power supply; The third terminal of the fifth switch is connected to the third terminal of the sixth switch to output the isolation power value. The second preset power supply is used to output the third voltage value, and the third preset power supply is used to output the fourth voltage value.

14. The control amplifier circuit according to claim 12, characterized in that, The isolation control circuit includes a third inverter, a seventh switch, and an eighth switch; wherein... The input terminal of the third inverter receives the control command signal, and the output terminal of the third inverter is connected to the first terminal of the seventh switch and the first terminal of the eighth switch, respectively. The second terminal of the seventh switch is connected to the isolation power supply value, and the third terminal of the eighth switch receives the ground signal; The third terminal of the seventh switch is connected to the second terminal of the eighth switch to output the isolation control signal.

15. The control amplifier circuit according to claim 12, characterized in that, The amplifier circuit includes a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch. The first terminal of the ninth switch is connected to the third terminal of the thirteenth switch for receiving the signal to be processed. The second terminal of the ninth switch, the third terminal of the eleventh switch, the first terminal of the twelfth switch, and the second terminal of the fourteenth switch are connected. The first terminal of the tenth switch is connected to the third terminal of the fourteenth switch for receiving a reference signal to be processed. The second terminal of the tenth switch, the third terminal of the twelfth switch, the first terminal of the eleventh switch, and the second terminal of the thirteenth switch are connected. The third terminal of the ninth switch and the third terminal of the tenth switch receive the first reference signal, the second terminal of the eleventh switch and the second terminal of the twelfth switch receive the second reference signal, and the first terminal of the thirteenth switch and the first terminal of the fourteenth switch receive the isolation control signal.

16. The control amplifier circuit according to claim 15, characterized in that, The amplifier circuit further includes a pre-charging circuit, and the pre-charging circuit includes a fifteenth switching transistor and a sixteenth switching transistor; wherein, The first terminal of the fifteenth switch and the first terminal of the sixteenth switch receive a precharge control signal; The second terminal of the fifteenth switch is connected to the fourth preset power supply, and the third terminal of the fifteenth switch is connected to the second terminal of the tenth switch. The second terminal of the sixteenth switch is connected to the second terminal of the tenth switch, and the third terminal of the sixteenth switch is connected to the second terminal of the ninth switch.

17. The control amplifier circuit according to claim 15, characterized in that, The amplifier circuit further includes a noise cancellation circuit, which comprises a seventeenth switching transistor and an eighteenth switching transistor; wherein, The first terminals of the seventeenth and eighteenth switching transistors receive noise cancellation signals. The second terminal of the seventeenth switch is connected to the second terminal of the ninth switch, and the third terminal of the seventeenth switch is connected to the first terminal of the ninth switch. The second terminal of the eighteenth switch is connected to the second terminal of the tenth switch, and the third terminal of the eighteenth switch is connected to the first terminal of the tenth switch.

18. The control amplifier circuit according to any one of claims 12-14, characterized in that, The amplifier circuit processes the signal to be processed, including a signal amplification stage and a signal write-back stage. If the amplifier circuit is in the signal amplification stage, then the isolation control signal is maintained at the third voltage value; or If the amplifier circuit is in the signal write-back phase, the isolation control signal is maintained with a fourth voltage value.

19. The control amplifier circuit according to claim 18, characterized in that, The amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, and a pre-charge stage; If the amplifier circuit is in the second charge sharing stage or the pre-charge stage, then the isolation control signal is maintained with a third voltage value; or If the amplifier circuit is in the standby phase, the isolation control signal is maintained at a fourth voltage value; or If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, the isolation control signal is maintained to have a fifth voltage value.

20. The control amplifier circuit according to claim 19, characterized in that, When the amplifier circuit is in the signal write-back stage, the first power consumption control signal is in a first level state, and the second power consumption control signal is in a second level state. When the amplifier circuit is in the standby stage, the noise cancellation stage, the first charge sharing stage, the second charge sharing stage, the signal amplification stage, or the pre-charge stage, the first power consumption control signal is in the second level state.

21. The control amplifier circuit according to any one of claims 3-17, characterized in that, The fifth, sixth, seventh, eleventh, and twelfth switching transistors are P-channel MOSFETs. The first, second, third, fourth, eighth, ninth, tenth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth switching transistors are N-channel MOSFETs. Wherein, the first terminal of the P-type field-effect transistor is the gate terminal, the second terminal of the P-type field-effect transistor is the source terminal, and the third terminal of the P-type field-effect transistor is the drain terminal; the first terminal of the N-type field-effect transistor is the gate terminal, the second terminal of the N-type field-effect transistor is the drain terminal, and the third terminal of the N-type field-effect transistor is the source terminal.

22. A control amplifier circuit, characterized in that, include: A power consumption control circuit is used to receive a power consumption control signal and output a first reference signal according to the power consumption control signal; An isolation circuit is used to determine a control command signal and generate an isolation control signal based on the control command signal. An amplifier circuit is used to receive the first reference signal, the isolation control signal, and the signal to be processed, and to process the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal; The isolation circuit includes a first signal determination circuit, a power output circuit, a second signal determination circuit, and an isolation control circuit; wherein, The first signal determining circuit is used to output a first power switching signal and / or a second power switching signal according to the preset operation instruction after receiving the preset operation instruction. The power output circuit is used to output an isolation power value according to the first power switching signal and / or the second power switching signal; The second signal determining circuit is used to output the control command signal according to the preset operation command after receiving the preset operation command; The isolation control circuit is used to receive the isolation power supply value and the control command signal, and generate the isolation control signal.

23. The control amplifier circuit according to claim 22, characterized in that, The power output circuit is used to determine that the isolation power value has a third voltage value when the first power switching signal has a second level state and the second power switching signal has a first level state. or When the first power switching signal has a first level state and the second power switching signal has a second level state, it is determined that the isolation power value has a fourth voltage value; Wherein, both the third voltage value and the fourth voltage value belong to the first level state, and the third voltage value is greater than the fourth voltage value.

24. The control amplifier circuit according to claim 23, characterized in that, The isolation control circuit is specifically used to determine that the isolation control signal has a third voltage value when the control command signal has a first level state and the isolation power supply value has a third voltage value. or When the control command signal has a first level state and the isolation power supply value has a fourth voltage value, it is determined that the isolation control signal has a fourth voltage value. or When the control command signal has a second level state, it is determined that the isolation control signal has a fifth voltage value; The fifth voltage value belongs to the second level state, and the fifth voltage value is less than the fourth voltage value.

25. The control amplifier circuit according to claim 24, characterized in that, The power output circuit includes a second preset power supply, a third preset power supply, a fifth switching transistor, and a sixth switching transistor; wherein... The first terminal of the fifth switch receives the first power switching signal, and the first terminal of the sixth switch receives the second power switching signal. The second end of the fifth switch is connected to the second preset power supply, and the second end of the sixth switch is connected to the third preset power supply; The third terminal of the fifth switch is connected to the third terminal of the sixth switch to output the isolation power value. The second preset power supply is used to output the third voltage value, and the third preset power supply is used to output the fourth voltage value.

26. The control amplifier circuit according to claim 24, characterized in that, The isolation control circuit includes a third inverter, a seventh switch, and an eighth switch; wherein... The input terminal of the third inverter receives the control command signal, and the output terminal of the third inverter is connected to the first terminal of the seventh switch and the first terminal of the eighth switch, respectively. The second terminal of the seventh switch is connected to the isolation power supply value, and the third terminal of the eighth switch receives the ground signal; The third terminal of the seventh switch is connected to the second terminal of the eighth switch to output the isolation control signal.

27. The control amplifier circuit according to claim 22, characterized in that, The amplifier circuit includes a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch. The first terminal of the ninth switch is connected to the third terminal of the thirteenth switch for receiving the signal to be processed. The second terminal of the ninth switch, the third terminal of the eleventh switch, the first terminal of the twelfth switch, and the second terminal of the fourteenth switch are connected. The first terminal of the tenth switch is connected to the third terminal of the fourteenth switch for receiving a reference signal to be processed. The second terminal of the tenth switch, the third terminal of the twelfth switch, the first terminal of the eleventh switch, and the second terminal of the thirteenth switch are connected. The third terminal of the ninth switch and the third terminal of the tenth switch receive the first reference signal, the second terminal of the eleventh switch and the second terminal of the twelfth switch receive the second reference signal, and the first terminal of the thirteenth switch and the first terminal of the fourteenth switch receive the isolation control signal.

28. The control amplifier circuit according to claim 27, characterized in that, The amplifier circuit further includes a pre-charging circuit, and the pre-charging circuit includes a fifteenth switching transistor and a sixteenth switching transistor; wherein, The first terminal of the fifteenth switch and the first terminal of the sixteenth switch receive a precharge control signal; The second terminal of the fifteenth switch is connected to the fourth preset power supply, and the third terminal of the fifteenth switch is connected to the second terminal of the tenth switch. The second terminal of the sixteenth switch is connected to the second terminal of the tenth switch, and the third terminal of the sixteenth switch is connected to the second terminal of the ninth switch.

29. The control amplifier circuit according to claim 27, characterized in that, The amplifier circuit further includes a noise cancellation circuit, which comprises a seventeenth switching transistor and an eighteenth switching transistor; wherein, The first terminals of the seventeenth and eighteenth switching transistors receive noise cancellation signals. The second terminal of the seventeenth switch is connected to the second terminal of the ninth switch, and the third terminal of the seventeenth switch is connected to the first terminal of the ninth switch. The second terminal of the eighteenth switch is connected to the second terminal of the tenth switch, and the third terminal of the eighteenth switch is connected to the first terminal of the tenth switch.

30. The control amplifier circuit according to any one of claims 24-26, characterized in that, The amplifier circuit processes the signal to be processed, including a signal amplification stage and a signal write-back stage. If the amplifier circuit is in the signal amplification stage, then the isolation control signal is maintained at the third voltage value; or If the amplifier circuit is in the signal write-back phase, the isolation control signal is maintained with a fourth voltage value.

31. The control amplifier circuit according to claim 30, characterized in that, The amplification circuit processes the signal to be processed, including: a standby stage, a noise cancellation stage, a first charge sharing stage, a second charge sharing stage, and a pre-charge stage; If the amplifier circuit is in the second charge sharing stage or the pre-charge stage, then the isolation control signal is maintained with a third voltage value; or If the amplifier circuit is in the standby phase, the isolation control signal is maintained at a fourth voltage value; or If the amplifier circuit is in the noise cancellation stage or the first charge sharing stage, the isolation control signal is maintained to have a fifth voltage value.

32. A control amplifier circuit, characterized in that, include: A power consumption control circuit is used to receive a power consumption control signal and output a first reference signal according to the power consumption control signal; An isolation circuit is used to determine a control command signal and generate an isolation control signal based on the control command signal. An amplifier circuit is used to receive the first reference signal, the isolation control signal, and the signal to be processed, and to process the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal; A reference control circuit is used to determine a reference control signal and output a second reference signal according to the reference control signal; The amplification circuit is further configured to receive the first reference signal, the second reference signal, the isolation control signal, and the signal to be processed, and to process the signal to be processed based on the first reference signal, the second reference signal, and the isolation control signal to obtain the target amplified signal shown. The reference control circuit includes multiple signal processing sub-circuits and multiple third control sub-circuits; wherein... The signal processing sub-circuit includes a second inverter, which is used to receive an initial reference signal and generate the reference control signal. The third control sub-circuit includes a fourth switch transistor. The first terminal of the fourth switch transistor receives the reference control signal, the second terminal of the fourth switch transistor is connected to a first preset power supply, and the third terminal of the fourth switch transistor is used to output the second reference signal. Among them, the multiple signal processing sub-circuits and the multiple third control sub-circuits correspond one-to-one.

33. The control amplifier circuit according to claim 32, characterized in that, The reference control circuit includes three of the third control sub-circuits, and the reference control signal includes a first reference control sub-signal, a second reference control sub-signal, and a third reference control sub-signal. The first preset power supply includes a first preset sub-power supply, a second preset sub-power supply, and a third preset power supply. In the first third control sub-circuit, the first terminal of the fourth switch receives the first reference control sub-signal, and the second terminal of the fourth switch is connected to the first preset sub-power supply. In the second third control sub-circuit, the first terminal of the fourth switch receives the second reference control sub-signal, and the second terminal of the fourth switch is connected to the second preset sub-power supply. In the third control sub-circuit, the first terminal of the fourth switch receives the third reference control sub-signal, and the second terminal of the fourth switch is connected to the third preset sub-power supply. The third terminals of the three fourth switching transistors are electrically connected to jointly output the second reference signal.

34. A sensitive amplifier, characterized in that, Includes the control amplifier circuit as described in any one of claims 1 to 33.

35. A semiconductor memory, characterized in that, Including the sensitive amplifier as described in claim 34.

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