Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a functional region and an edge region; forming a mask layer on the substrate, the mask layer covering a surface of the edge region; forming a first channel material layer on the functional region; forming a material layer opening in the first channel material layer, the material layer opening penetrating through the first channel material layer, the first channel material layer forming a first channel layer; forming a second channel material layer in the material layer opening, the second channel material layer being higher than a top surface of the first channel layer; and planarizing the second channel material layer to form a second channel layer, the second channel layer being higher than or flush with the top surface of the first channel layer. The method for forming the semiconductor structure reduces the possibility of the edge surface of the substrate being contaminated, improves the flatness of the surface of the semiconductor structure, reduces surface lattice defects, and thus improves the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor structure. Background Technology

[0002] With the development of semiconductor technology, the size of semiconductor devices continues to shrink, and the design of three-dimensional structures such as FinFETs has become a hot topic in this field. FinFETs generally have multiple fins extending vertically upward from the substrate, in which the channel of the FinFET is formed, the gate structure is formed on the fins, and the active region and drain region are formed in the fins on both sides of the gate structure.

[0003] As semiconductor manufacturing technology nodes continue to shrink, the low carrier mobility of traditional silicon channels has become a significant factor limiting device performance. In pFETs (p-channel MOSFETs), by replacing silicon with silicon germanium to form a silicon-germanium / silicon dual-channel, the carrier mobility of the pFET channel can be effectively improved, thereby enhancing device performance.

[0004] However, under the existing technology, during the formation of silicon-germanium channels, the substrate edge surface is easily contaminated by germanium, which affects the subsequent process window. In addition, when forming silicon-germanium channels, chemical mechanical polishing (CMP) is usually used to planarize the silicon-germanium material layer to remove the excess silicon-germanium material layer. However, the resulting silicon-germanium channel surface has more lattice defects and poor surface flatness, which affects device performance. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure that reduces the possibility of substrate edge surface contamination during the formation of a silicon-germanium channel. At the same time, it improves the flatness of the semiconductor structure surface after the planarization process of the silicon-germanium channel structure, reduces surface lattice defects, and thus improves the performance of the semiconductor device.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a functional region and an edge region; forming a mask layer on the substrate, the mask layer covering the surface of the edge region; using the mask layer as a mask, forming a first channel material layer on the functional region; forming a material layer opening in the first channel material layer, the material layer opening penetrating the first channel material layer, the first channel material layer forming a first channel layer; forming a second channel material layer in the material layer opening, the second channel material layer being higher than the top surface of the first channel layer; planarizing the second channel material layer to form a second channel layer, the second channel layer being higher than or flush with the top surface of the first channel layer.

[0007] Optionally, the functional area includes a first functional area and a second functional area.

[0008] Optionally, the first channel layer includes a first sub-channel structure located on the first functional area and a second sub-channel structure located on the second functional area, wherein the width of the first sub-channel structure is greater than the width of the second sub-channel structure.

[0009] Optionally, the mask layer includes a first mask layer located on the substrate and an upper mask layer located on the first mask layer, wherein the mask layer has a mask opening that exposes the surface of the functional area.

[0010] Optionally, the method of forming the mask layer includes: forming an initial mask layer on the substrate; forming a patterned layer on the initial mask layer, the patterned layer exposing the initial mask layer on the functional region; using the patterned layer as a mask, etching the initial mask layer until the surface of the functional region is exposed, thereby forming a mask layer with mask openings.

[0011] Optionally, the material of the first mask layer includes silicon oxide.

[0012] Optionally, the material of the upper mask layer includes silicon nitride.

[0013] Optionally, after forming the mask layer and before forming the first channel material layer, the method further includes cleaning the substrate.

[0014] Optionally, the material of the first channel material layer is silicon germanium.

[0015] Optionally, the formation process of the first channel material layer includes a selective epitaxial growth process.

[0016] Optionally, the method for forming the semiconductor structure further includes: removing the upper mask layer after forming the first channel layer and before forming the second channel material layer.

[0017] Optionally, the process for removing the upper mask layer includes a wet etching process.

[0018] Optionally, the material of the second channel material layer is silicon.

[0019] Optionally, after forming the second channel material layer, the method further includes forming a dielectric layer located on the second channel material layer and on the first mask layer.

[0020] Optionally, the material of the dielectric layer is the same as the material of the first mask layer.

[0021] Optionally, the dielectric layer is made of silicon oxide.

[0022] Optionally, after forming the dielectric layer and before planarizing the second channel material layer, the method further includes: performing initial planarization on the dielectric layer on the functional area until the surface of the second channel material layer is exposed.

[0023] Optionally, the initial planarization process includes a chemical mechanical polishing process.

[0024] Optionally, the process for planarizing the second channel material layer includes chemical mechanical polishing or dry etching.

[0025] Optionally, when the second channel layer is flush with the top surface of the first channel layer, an epitaxial layer is formed on the first channel layer and the second channel layer after the second channel layer is formed.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the semiconductor structure formation method provided by the present invention, the mask layer covers the surface of the edge region of the substrate. Therefore, during the formation of the first channel material layer, the mask layer protects the surface of the edge region, preventing the first channel material layer from forming on the edge region surface and reducing the possibility of edge region contamination. Furthermore, since the first channel layer is formed first, followed by the formation of a second channel material layer higher than the first channel layer, a semiconductor structure with good surface flatness can be formed by subsequently planarizing the second channel material layer without needing to planarize the first channel layer. This avoids lattice defects introduced by the planarization process of the first channel layer and improves the planarization effect of the semiconductor structure. Therefore, it improves the surface flatness of the semiconductor structure and enhances device performance.

[0028] Furthermore, after forming the second channel material layer, a dielectric layer is formed on the second channel material layer; the material of the second channel material layer is silicon, and the material of the dielectric layer is silicon oxide. Since the planarization processes for silicon oxide and silicon are relatively mature and highly controllable, and the device surface flatness is good after planarization, a relatively flat second channel layer can be formed by subsequently planarizing the dielectric layer and the second channel material layer, thereby improving the surface flatness of the semiconductor structure. Simultaneously, since it is not necessary to planarize the first channel layer, lattice defects introduced by the planarization process of the first channel layer are avoided, thus improving the process window for semiconductor structure formation and enhancing device performance. Attached Figure Description

[0029] Figures 1 to 4 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0030] Figures 5 to 10 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0031] As described in the background art, in the prior art, during the formation of silicon-germanium channels, the substrate edge surface is easily contaminated by germanium, which affects the subsequent process window; after the silicon-germanium channel structure is planarized, the flatness of the semiconductor structure surface is poor, and the planarization process of the silicon-germanium channel structure is prone to introducing lattice defects, thereby reducing device performance.

[0032] Figures 1 to 4 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure.

[0033] Please refer to Figure 1 A substrate 100 is provided; a first mask layer 101 and a second mask layer 102 located on the first mask layer 101 are formed on the substrate 100, the second mask layer 102 being made of silicon nitride; a first trench (not shown) and a second trench (not shown) are formed in the substrate 100, the first mask layer 101, and the second mask layer 102, the opening width of the first trench being greater than the opening width of the second trench, the first trench and the second trench penetrating the second mask layer 102 and the first mask layer 101 and extending into the substrate 100; a first channel structure 103 is formed in the first trench, and a second channel structure 104 is formed in the second trench, the first channel structure 103 and the second channel structure 104 being made of silicon germanium.

[0034] Please refer to Figure 2 Remove the second mask layer 102, and the first mask layer 101 exposes the top surfaces of the first channel structure 103 and the second channel structure 104, and an oxide layer 105 is formed on the exposed surfaces of the first channel structure 103 and the second channel structure 104.

[0035] After removing the second mask layer 102, the first channel structure 103, the second channel structure 104, and the first mask layer 101 are planarized until the substrate surface is exposed. The process of planarizing the first channel structure 103, the second channel structure 104, and the first mask layer 101 is as follows: Figure 3 and Figure 4 As shown.

[0036] Please refer to Figure 3 , Figure 3This is a cross-sectional schematic diagram of the semiconductor structure during the planarization process. During the planarization process, the top protrusions of the first channel structure 103 and the second channel structure 104, namely regions A and C, are first planarized, thereby removing the oxide layer 105 on regions A and C and exposing portions of the first channel structure 103 and the second channel structure 104.

[0037] Please refer to Figure 4 , Figure 4 This is a cross-sectional view of the semiconductor structure after planarization. After planarization, the top surface of the first channel structure 103 is convex and higher than the top surface of the substrate 100, while the top surface of the second channel structure 104 is flush with the top surface of the substrate 100.

[0038] Since the material of the second mask layer 102 is silicon nitride, the etching solution used in the process of removing the second mask layer 102 includes hydrogen peroxide. The etching solution oxidizes the surfaces of the first channel structure 103 and the second channel structure 104 to form an oxide layer 105. During the planarization process, the top protrusions (regions A and C) of the first channel structure 103 and the second channel structure 104 are planarized first, and the oxide layer 105 on them is removed, while other regions on the top of the first channel structure 103 (such as region B) are still covered by the oxide layer 105. Therefore, in the first channel structure 103, the planarization rate of region B is less than that of region A, resulting in poor local flatness of the surface of the first channel structure 103 after planarization, and its surface is higher than the top surface of the substrate 100. Furthermore, since the width of the second channel structure 104 is smaller than the width of the first channel structure 103, the surface structure of the second channel structure 104 has little difference. Therefore, the planarization rate of the surface of the second channel structure 104 is relatively uniform. After planarization, the top surface of the second channel structure 104 is flush with the top surface of the substrate 100, resulting in a height difference between the surfaces of the first channel structure 103 and the second channel structure 104. This leads to poor overall flatness of the semiconductor structure and reduces the process window for semiconductor structure formation. In addition, the materials of the first channel structure 103 and the second channel structure 104 are silicon and germanium. The planarization process for silicon and germanium has poor controllability and is prone to introducing lattice defects.

[0039] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. By forming a mask layer covering the surface of the edge region on the substrate, the possibility of contamination of the edge region surface during the formation of the first channel material layer is reduced. Simultaneously, by forming the first channel layer first and then forming a second channel material layer higher than the channel structure, a semiconductor structure with good surface flatness can be formed by planarizing the second channel material layer without needing to planarize the first channel layer. This avoids lattice defects introduced by the planarization process of the first channel layer and improves the planarization effect of the semiconductor structure. Therefore, the surface flatness of the semiconductor structure is improved, and device performance is enhanced.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 5 to 10 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 5 A substrate 200 is provided, the substrate 200 including a functional region (not shown) and an edge region III.

[0043] The substrate 200 is made of materials including silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), and germanium-on-insulator (GOI). In this embodiment, the substrate 200 is made of silicon.

[0044] The functional regions provide a platform for the subsequent formation of the first and second channel layers. The functional regions include a first functional region I and a second functional region II. The first functional region I and the second functional region II are used to form device structures of different sizes.

[0045] Please continue to refer to this. Figure 5 A mask layer 201 is formed on the substrate 200. The mask layer 201 includes a first mask layer 202 located on the substrate 200 and an upper mask layer 203 located on the first mask layer 202. The mask layer 201 has a mask opening 204 that exposes the surface of the functional area. The mask layer covers the surface of the edge region III.

[0046] The mask opening 204 in the mask layer 201 provides space for the subsequent formation of the first trench layer and the second trench layer.

[0047] Furthermore, the mask layer 201 also serves to protect the substrate 200 outside the functional region from contamination during subsequent semiconductor structure formation processes. The mask layer 201 covers the surface of edge region III of the substrate 200; therefore, during the subsequent formation of the first channel material layer, the mask layer 201 protects the surface of edge region III, preventing the formation of the first channel material layer on the surface of edge region III and reducing the possibility of contamination of edge region III.

[0048] Specifically, during the subsequent formation of the first channel material layer, the upper mask layer 203 reduces the damage to the first mask layer 202, thereby protecting the uniformity and integrity of the first mask layer 202, and consequently reducing the possibility of edge region III on the substrate 200 being exposed and contaminated, thereby improving the process window for semiconductor structure formation.

[0049] The first mask layer 202 is located between the substrate 200 and the upper mask layer 203, thereby achieving better stress matching.

[0050] In this embodiment, the material of the first mask layer 202 includes silicon oxide.

[0051] In this embodiment, the upper mask layer 203 is a single-layer structure. The material of the upper mask layer 203 includes silicon nitride.

[0052] In this embodiment, the method for forming the mask layer 201 includes: forming an initial mask layer (not shown) on the substrate 200; forming a patterned layer (not shown) on the initial mask layer, the patterned layer exposing the initial mask layer on the functional region; using the patterned layer as a mask, etching the initial mask layer until the surface of the functional region is exposed, thereby forming a mask layer 201 with a mask opening 204.

[0053] After the mask layer 201 is formed, the substrate 200 is cleaned to remove impurities remaining from the etching process.

[0054] The presence of the upper mask layer 203 reduces the damage to the first mask layer 202 caused by the cleaning solution during the cleaning process, thereby improving the integrity of the first mask layer 202. This prevents the subsequent formation of the first channel material layer from growing on the surface of edge region III, reduces the possibility of contamination on the surface of edge region III on the substrate 200, and thus improves the process window for semiconductor structure formation and enhances the performance of semiconductor devices.

[0055] In other embodiments, the upper mask layer has a multi-layer structure, thereby providing better protection for the substrate.

[0056] Please refer to Figure 6 Using the mask layer 201 as a mask, a first channel material layer 205 is formed on the functional area.

[0057] The first channel material layer 205 provides raw materials for the subsequently formed first channel layer.

[0058] In this embodiment, the first channel material layer 205 fills the mask opening 204, and the top surface of the first channel material layer 205 is higher than the top surface of the mask layer 201.

[0059] During the formation of the first channel material layer 205, since the structure of the mask layer 201 is intact, the mask layer 201 protects the surface of the edge region III, preventing the first channel material layer 205 from growing on the surface of the edge region III and preventing the edge region III on the substrate 200 from being contaminated, thereby improving the process window of the semiconductor structure formation process.

[0060] In this embodiment, the material of the first channel material layer 205 is silicon-germanium. The method for forming the first channel material layer 205 includes a selective epitaxial growth process.

[0061] Please refer to Figure 7 An opening 218 is formed in the first channel material layer 205, the opening 218 penetrating the first channel material layer 205, and the first channel material layer 205 forms a first channel layer 215.

[0062] Due to the presence of the opening 218 in the material layer, the first channel material layer 205 is transformed into several discrete channel structures, thereby forming the first channel layer 215 as the PMOS region of the semiconductor structure. The width and position of the opening 218 in the material layer control the width and position of the channel structure. Simultaneously, the opening 218 in the material layer provides space for the subsequently formed second channel layer.

[0063] Specifically, the first channel layer 215 includes a first sub-channel structure 216 located on the first functional region I and a second sub-channel structure 217 located on the second functional region II. The width of the first sub-channel structure 216 is greater than the width of the second sub-channel structure 217, thereby providing a channel structure with different dimensions and functions for the semiconductor device.

[0064] In this embodiment, the method for forming the opening 218 in the material layer includes: forming a patterned layer (not shown) on the first channel material layer 205, the patterned layer exposing a portion of the surface of the first channel material layer 205; using the patterned layer as a mask, etching the first channel material layer 205 until the surface of the functional area is exposed, thereby forming the first channel layer 215.

[0065] In this embodiment, the method for etching the first channel material layer 205 includes dry etching.

[0066] After the first trench layer 215 is formed, a cleaning process is performed to remove impurities remaining from the etching process.

[0067] During the etching of the first channel material layer 205 and the cleaning process, the presence of the upper mask layer 203 reduces the damage to the first mask layer 202, protects the uniformity and integrity of the first mask layer 202, and thereby reduces the possibility of the edge region III on the substrate 200 being exposed and contaminated.

[0068] Please refer to Figure 8 Remove the upper mask layer 203 to expose the surface of the first mask layer 202.

[0069] The purpose of removing the upper mask layer 203 is to simplify the structure of the mask layer and expose the first mask layer 202, so that a dielectric layer of the same material as the first mask layer 202 can be formed on its surface. Subsequently, the first mask layer 202 and the dielectric layer thereon can be removed using the same process conditions to expose the complete surface of the substrate 200, thereby simplifying the process steps.

[0070] Since the upper mask layer 203 protects the first mask layer 202, the exposed first mask layer 202 still maintains good integrity after the upper mask layer 203 is removed. Thus, the first mask layer 202 can continue to protect the edge region III on the substrate 200 from contamination.

[0071] Specifically, the method for removing the upper mask layer 203 includes a wet etching process.

[0072] Please refer to Figure 9 A second channel material layer 206 is formed within the opening 218 of the material layer, and the second channel material layer 206 is higher than the top surface of the first channel layer 215.

[0073] The second channel material layer 206 provides raw materials for the subsequently formed second channel layer 216 to form the NMOS region of the semiconductor structure.

[0074] Since the second channel material layer 206 is higher than the top surface of the first channel layer 215, a semiconductor structure with good surface flatness can be formed by subsequently planarizing the second channel material layer 206 without needing to planarize the first channel layer 215. This avoids lattice defects introduced by the planarization process of the first channel layer 215, improves the planarization effect of the semiconductor structure, improves the surface flatness of the semiconductor structure, and thus improves device performance.

[0075] In this embodiment, the material of the second channel material layer 206 is silicon. The method for forming the second channel material layer 206 includes: chemical vapor deposition, furnace tube process, or epitaxial growth process.

[0076] Please continue to refer to this. Figure 9 A dielectric layer 207 is formed on the second channel material layer 206 and on the first mask layer 202.

[0077] By introducing the dielectric layer 207, the subsequent planarization process of the second channel material layer 206 can be better assisted, thereby improving the planarization effect of the second channel material layer 206 to form a second channel layer with better surface flatness. Furthermore, fewer defects are introduced during the planarization process, thereby improving device performance.

[0078] In this embodiment, the material of the dielectric layer 207 is the same as the material of the first mask layer 202. Specifically, the material of the dielectric layer 207 is silicon oxide.

[0079] Since the material of the dielectric layer 207 is the same as that of the first mask layer 202, the first mask layer 202 and the dielectric layer 207 thereon can be removed simultaneously using the same process conditions to expose the complete surface of the substrate 200, thereby simplifying the process steps.

[0080] In this embodiment, the method for forming the dielectric layer 207 includes chemical vapor deposition or furnace tube process.

[0081] Please refer to Figure 10 The dielectric layer 207 on the functional area is initially planarized until the surface of the second channel material layer 206 is exposed; then, the second channel material layer 206 is planarized to form a second channel layer 219, which is higher than the top surface of the first channel layer 215.

[0082] Since the dielectric layer 207 is made of silicon oxide and the second channel material layer 206 is made of silicon, and the planarization process for silicon oxide and silicon is relatively mature and highly controllable, and the device structure surface flatness is good after the planarization process is completed, a relatively flat second channel layer 219 can be formed by subsequently planarizing the dielectric layer 207 and the second channel material layer 206, thereby improving the surface flatness of the semiconductor structure. In addition, since it is not necessary to planarize the silicon-germanium material of the first channel layer 215, the lattice defects introduced by the silicon-germanium material planarization process are avoided, thereby improving the process window of the semiconductor structure formation process and improving device performance.

[0083] In this embodiment, the initial planarization process includes a chemical mechanical polishing process.

[0084] In this embodiment, the process of planarizing the second channel material layer 206 includes a chemical mechanical polishing process or a dry etching process.

[0085] In this embodiment, since the second channel layer 219 is higher than the top surface of the first channel layer 215 after the planarization is completed, the second channel layer 219 acts as a protective layer, reducing the contamination and damage to the first channel layer 215. Therefore, there is no need to form an additional protective layer on the first channel layer 215 to protect it, simplifying the process steps.

[0086] In other embodiments, the second channel layer is flush with the top surface of the first channel layer. After the second channel layer is formed, an epitaxial layer is formed on both the first and second channel layers to protect the first channel layer and to facilitate subsequent processes.

[0087] In this embodiment, after the second channel layer 219 is formed, the first mask layer 202 and the dielectric layer 207 on the surface of the substrate 200 outside the functional area are removed to expose the complete surface of the substrate 200.

[0088] Since the material of the first mask layer 202 is the same as that of the dielectric layer 207, both can be removed simultaneously using the same process conditions, thereby simplifying the process steps for forming the semiconductor structure and improving the fabrication efficiency.

[0089] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a functional region and an edge region, the functional region including a first functional region and a second functional region; A mask layer is formed on the substrate, the mask layer covering the surface of the edge region; Using the mask layer as a mask, a first channel material layer is formed on the functional area; An opening is formed in the first channel material layer, the opening penetrating the first channel material layer, the first channel material layer forming a first channel layer, the first channel layer including a first sub-channel structure located on the first functional area and a second sub-channel structure located on the second functional area, the width of the first sub-channel structure being greater than the width of the second sub-channel structure. A second channel material layer is formed within the opening of the material layer, and the second channel material layer is higher than the top surface of the first channel layer; The second channel material layer is planarized to form a second channel layer, which is higher than or flush with the top surface of the first channel layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The mask layer includes a first mask layer located on the substrate and an upper mask layer located on the first mask layer, wherein the mask layer has a mask opening that exposes the surface of the functional area.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method of forming the mask layer includes: forming an initial mask layer on the substrate; forming a patterned layer on the initial mask layer, the patterned layer exposing the initial mask layer on the functional region; using the patterned layer as a mask, etching the initial mask layer until the surface of the functional region is exposed, thereby forming a mask layer with mask openings.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the first mask layer includes silicon oxide.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the upper mask layer includes silicon nitride.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the mask layer and before forming the first channel material layer, the method further includes cleaning the substrate.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first channel material layer is silicon germanium.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The formation process of the first channel material layer includes a selective epitaxial growth process.

9. The method for forming a semiconductor structure as described in claim 2, characterized in that, After the formation of the first channel layer and before the formation of the second channel material layer, the process further includes: removing the upper mask layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for removing the upper mask layer includes a wet etching process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second channel material layer is silicon.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the second channel material layer, the method further includes forming a dielectric layer located on the second channel material layer and on the first mask layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the dielectric layer is the same as that of the first mask layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The dielectric layer is made of silicon oxide.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, After the dielectric layer is formed and before the second channel material layer is planarized, the method further includes: performing initial planarization on the dielectric layer on the functional area until the surface of the second channel material layer is exposed.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The initial planarization process includes chemical mechanical polishing.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for planarizing the second channel material layer includes chemical mechanical polishing or dry etching.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, When the second channel layer is flush with the top surface of the first channel layer, an epitaxial layer is formed on the first channel layer and the second channel layer after the second channel layer is formed.

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