Circuit for realizing peak current mode boost current limit value not changing with duty cycle by dynamic clamp

Abstract

The circuit for realizing peak current mode BOOST current limiting value not changing with duty ratio by dynamic clamping, through integrating slope compensation current circuit, slope compensation peak current circuit, voltage to current circuit and sample and hold circuit on the sampling node and clamping node of the control pulse width modulation comparator switch, can on one hand sample the peak value of the slope compensation voltage as a direct current with the error amplifier superimposed on the clamping voltage by the sample and hold circuit, so as to ensure that the slope compensation does not affect the peak value of the inductor current under the current limiting condition, on the other hand, the upper clamping voltage of the error amplifier is the dynamic clamping value superimposed on the slope compensation peak current, and the clamping value changes with the duty ratio, so as to realize the effect that the maximum peak current of the BOOST converter does not change with the duty ratio.

Description

Technical Field

[0001] This invention relates to peak current mode BOOST current limiting technology, and in particular to a circuit that dynamically clamps the peak current mode BOOST current limiting value so that it does not change with the duty cycle. Background Technology

[0002] In peak current-mode boost converters, when the duty cycle is greater than 50%, slope compensation is needed in the current loop to eliminate subharmonic oscillations. However, adding slope compensation reduces the peak inductor current, resulting in a lower boost current limit. A common solution is to change the slope compensation gradient, transforming the fixed-slope compensation current into a segmented-slope compensation current; the larger the duty cycle, the larger the slope. This approach mitigates the reduction in maximum peak current caused by slope compensation, but it cannot completely eliminate it. Figure 2 This is a schematic diagram of a traditional superimposed slope compensation current-limiting comparator circuit. (Example) Figure 2 As shown, the conventional superimposed slope compensation current-limiting comparator circuit includes a first PMOS transistor MP0 and a third PMOS transistor MP2 (with a mirror ratio of 1:1) using a common source and common gate configuration. The source of MP2 is connected to the power supply voltage terminal VDD. The gate and drain of MP0 are interconnected and then connected to the drain of the second NMOS transistor MN1. The gate of MN1 is connected to the sawtooth wave voltage terminal VRAMP generated by the internal clock. The source of MN1 is connected to the first node A, which is grounded through the first resistor R1. The drain of MP2 is connected to the sampling node sum. The slope compensation current Islope flows from the drain of MP2 into sum. sum is connected to VDD through the current sampling terminal Ics of the lower transistor. The sampling current Ics of the BOOST lower transistor flows into the sampling node sum. sum is grounded through the third resistor R3. sum is connected to the pulse width modulation comparator. The positive input (+) and negative input (-) of PWM_COMP are connected to the clamping node eaout, which is the output of error amplifier EA. The output of PWM_COMP is connected to the main flip signal terminal MAIN_TRIP (or output the main flip signal MAIN_TRIP). The positive input (+) of error amplifier EA is connected to the reference voltage terminal VREF. The negative input (-) of error amplifier EA is connected to the feedback voltage terminal FB. The clamping node eaout is connected to the source of the fourth PMOS transistor MP3 and the negative input (-) of the first operational amplifier AMP1. The positive input (+) of AMP1 is connected to the upper clamping voltage terminal Clamp_H. The output of AMP1 is connected to the gate of MP3. The drain of MP3 is grounded. Figure 2This is a traditional current-limiting comparator circuit with superimposed slope compensation. The sawtooth wave generated by the VRAMP's internal clock produces a current with a fixed slope across resistor R1. This slope-compensated current is superimposed on the sampling current Ics of the lower transistor through the mirror image of MP2, and converted into a sum-point voltage across R3. This sum-point voltage is compared with the output eaout of the error amplifier, thereby controlling the switching of the PWM comparator. Op-amps AMP1 and MP3 form an upper clamping circuit for eaout through negative feedback. When the load is light or medium, the eaout voltage is low and insufficient to turn on MP3, so the upper clamping circuit does not work. As the load increases, the eaout voltage gradually rises. When the load increases to the point where the inductor current reaches its maximum peak current, MP3 turns on, and the upper clamping circuit begins to function. At this time, the negative feedback clamps the eaout voltage to the Clamp_H value. Only when the inductor current increases to the point where (Ics + Islope) * R3 = Clamp_H does the PWM comparator flip and turn off the BOOST lower transistor. Analysis shows that the larger the duty cycle, the larger the slope compensation current Islope, which in turn results in a smaller effective maximum peak current Ics and a smaller BOOST current limit value. Summary of the Invention

[0003] This invention addresses the defects or deficiencies in existing technologies by providing a circuit that uses dynamic clamping to ensure that the peak current mode BOOST current limit value does not change with the duty cycle.

[0004] The technical solution of the present invention is as follows:

[0005] A circuit for dynamically clamping to ensure that the peak current modulus BOOST current limit does not change with the duty cycle is characterized by comprising a sampling node and a clamping node for controlling the switch of a pulse width modulation comparator. The sampling node has a first path connected to the power supply voltage terminal via the current sampling terminal of the lower transistor, a second path grounded via a third resistor, and a third path connected to the output terminal of a slope compensation current circuit. The clamping node has a first path connected to the output terminal of an error amplifier, a second path connected to the negative input terminal of a first operational amplifier and the source of a fifth PMOS transistor, with the drain of the fifth PMOS transistor grounded and the gate of the fifth PMOS transistor connected to the output terminal of the first operational amplifier. The positive input terminal of the first operational amplifier is connected to a sixth node. The sixth node has a first path connected to the output terminal of a slope compensation peak current circuit, and a second path connected via a fourth resistor to the positive input terminal of a second operational amplifier and the drain of a third NMOS transistor, with the gate of the third NMOS transistor connected to the output terminal of the second operational amplifier and the source of the third NMOS transistor grounded. The negative input terminal of the second operational amplifier is connected to the upper clamping voltage terminal. The slope compensation peak current circuit is connected to a sample-and-hold circuit via a voltage-to-current converter.

[0006] The slope compensation current circuit includes a first PMOS transistor and a third PMOS transistor with a common source and common gate. The source of the third PMOS transistor is connected to the power supply voltage terminal, and the drain of the third PMOS transistor is connected to the sampling node. The gate and drain of the first PMOS transistor are interconnected and then connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the sawtooth wave voltage terminal generated by the internal clock. The source of the first NMOS transistor is connected to the first node, and the first node is grounded through a first resistor.

[0007] The sample-and-hold circuit includes a first switch, one end of which is connected to the first node and the other end of which is connected to the second node. The second node is grounded through a first capacitor and the second path is connected to a fourth node through a second switch. The fourth node is grounded through a second capacitor and the second path is connected to the voltage-to-current circuit.

[0008] The voltage-to-current conversion circuit includes a third operational amplifier. The positive input terminal of the third operational amplifier is connected to the fourth node, and the negative input terminal of the third operational amplifier is connected to the fifth node. The fifth node has a first path grounded through a second resistor, a second path connected to the source of a second NMOS transistor, the gate of the second NMOS transistor connected to the output terminal of the third operational amplifier, and the drain of the second NMOS transistor connected to the slope compensation peak current circuit.

[0009] The slope compensation peak current circuit includes a second PMOS transistor and a fourth PMOS transistor with a common source and common gate. The source of the fourth PMOS transistor is connected to the power supply voltage terminal, and the drain of the fourth PMOS transistor is connected to the sixth node. The slope compensation peak current flows from the drain of the fourth PMOS transistor through the sixth node and through the fourth resistor. The gate and drain of the second PMOS transistor are interconnected and then connected to the drain of the second NMOS transistor.

[0010] Let the resistance of the first resistor be R1 and the resistance of the second resistor be R2, then R1 = R2.

[0011] Let the voltage of the sixth node be VF, the voltage of the upper clamping voltage terminal be Clamp_H, and the slope compensation peak current be I_slope_DC, then VF = Clamp_H + Islope_DC * R4.

[0012] The sampling node is connected to the positive input of the pulse width modulation comparator, the clamping node is connected to the negative input of the pulse width modulation comparator, and the output of the pulse width modulation comparator is connected to the main flip signal terminal to output the main flip signal MAIN_TRIP.

[0013] The technical effects of this invention are as follows: This invention achieves a circuit where the peak current of the BOOST converter does not change with the duty cycle by dynamically clamping the circuit. By integrating a slope compensation current circuit, a slope compensation peak current circuit, a voltage-to-current circuit, and a sample-and-hold circuit at the sampling and clamping nodes of the control pulse width modulation comparator switch, it can, on the one hand, use the sample-and-hold circuit to sample the peak value of the slope compensation voltage and use it as a DC current to superimpose it with the clamping voltage on the error amplifier, thereby ensuring that the slope compensation does not affect the peak value of the inductor current under current limiting conditions. On the other hand, the clamping voltage on the error amplifier is the dynamic clamping value after superimposing the slope compensation peak current. The clamping value changes with the duty cycle, thereby achieving the effect that the maximum peak current of the BOOST converter does not change with the duty cycle.

[0014] The advantages of this invention compared to the prior art are: simple circuit structure, ingenious design, and the maximum peak current of BOOST does not change with slope compensation. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit structure and principle of implementing the dynamic clamping of the present invention to achieve the peak current mode BOOST current limit value not changing with the duty cycle.

[0016] Figure 2 This is a schematic diagram of a current-limiting comparator circuit with traditional superimposed slope compensation.

[0017] The reference numerals in the attached diagram are listed below: VDD - Power supply voltage terminal; PWM_COMP - Pulse width modulation comparator; EA - Error amplifier; AMP1~AMP3 - First operational amplifier to third operational amplifier; MAIN_TRIP - Main flip signal terminal; sum - Sampling node; VREF - Reference voltage terminal; FB - Feedback voltage terminal; eaout - Clamping node; Clamp_H - Upper clamping voltage terminal; Ics - Lower transistor current sampling terminal or BOOST lower transistor sampling current (BOOST refers to the boost converter, and the lower transistor is also called the lower switching transistor). R1~R4 - First resistor to fourth resistor; C1~C2 - First capacitor to second capacitor; S1~S2 - First switch to second switch; I_slope - Slope compensation current; I_slope_DC - Peak current of slope compensation current; MP0~MP4 - First PMOS transistor to fifth PMOS transistor; MN0~MN2 - First NMOS transistor to third NMOS transistor; VRAMP - Sawtooth wave voltage terminal for internal clock generation; A~B - First node to second node; D~F - Fourth node to sixth node; 1:1 - Mirror ratio. Detailed Implementation

[0018] The following is in conjunction with the attached diagram ( Figure 1 The present invention will be described below.

[0019] Figure 1This is a schematic diagram illustrating the structural principle of the circuit implementing the dynamic clamping of this invention to ensure that the peak current modulus BOOST current limiting value does not change with the duty cycle. (Reference) Figure 1 As shown, the circuit for dynamically clamping to ensure that the peak current modulus BOOST current limit does not change with the duty cycle includes a sampling node sum and a clamping node eaout that control the pulse width modulation comparator switch. The sampling node sum has a first path connected to the power supply voltage terminal VDD through the current sampling terminal Ics of the lower transistor, a second path grounded through the third resistor R3, and a third path connected to the output terminal of the slope compensation current circuit. The clamping node eaout has a first path connected to the output terminal of the error amplifier EA, and a second path connected to the negative input terminal (-) of the first operational amplifier AMP1 and the source of the fifth PMOS transistor MP4. The drain of the fifth PMOS transistor MP4 is grounded, and the gate of the fifth PMOS transistor MP4 is connected to the first... The output terminal of operational amplifier AMP1 is connected to the sixth node F. The sixth node F is connected to the output terminal of the slope compensation peak current circuit in the first path and to the positive input terminal (+) of the second operational amplifier AMP2 and the drain of the third NMOS transistor MN2 through the fourth resistor R4. The gate of the third NMOS transistor MN2 is connected to the output terminal of the second operational amplifier AMP2 and the source of the third NMOS transistor MN2 is grounded. The negative input terminal (-) of the second operational amplifier AMP2 is connected to the clamping voltage terminal Clamp_H. The slope compensation peak current circuit is connected to the sample-and-hold circuit through a voltage-to-current conversion circuit.

[0020] The slope compensation current circuit includes a first PMOS transistor MP0 and a third PMOS transistor MP2 with a common source and common gate. The source of the third PMOS transistor MP2 is connected to the power supply voltage terminal VDD, and the drain of the third PMOS transistor MP2 is connected to the sampling node sum. The gate and drain of the first PMOS transistor MP0 are interconnected and connected to the drain of the first NMOS transistor MN0. The gate of the first NMOS transistor MN0 is connected to the sawtooth wave voltage terminal VRAMP generated by the internal clock. The source of the first NMOS transistor MN0 is connected to the first node A, and the first node A is grounded through the first resistor R1. The sample-and-hold circuit includes a first switch S1. One end of the first switch S1 is connected to the first node, and the other end is connected to the second node B. The second node B is grounded through the first capacitor C1 and the second path is connected to the fourth node D through the second switch S2. The fourth node D is grounded through the second capacitor C2 and the second path is connected to the voltage-to-current circuit. The voltage-to-current conversion circuit includes a third operational amplifier AMP3. The positive input terminal (+) of the third operational amplifier AMP3 is connected to the fourth node D, and the negative input terminal (-) of the third operational amplifier AMP3 is connected to the fifth node E. The fifth node E is grounded through a second resistor R2 in the first path and connected to the source of a second NMOS transistor MN1 in the second path. The gate of the second NMOS transistor MN1 is connected to the output terminal of the third operational amplifier AMP3, and the drain of the second NMOS transistor MN2 is connected to the slope compensation peak current circuit.

[0021] The slope compensation peak current circuit includes a second PMOS transistor MP1 and a fourth PMOS transistor MP3, both based on a common source and common gate. The source of the fourth PMOS transistor MP3 is connected to the power supply voltage terminal VDD, and its drain is connected to the sixth node F. The slope compensation peak current flows from the drain of the fourth PMOS transistor MP3 through the sixth node F and through the fourth resistor R4. The gate and drain of the second PMOS transistor MP1 are interconnected and connected to the drain of the second NMOS transistor MN1. Let the resistance of the first resistor be R1 and the resistance of the second resistor be R2, then R1 = R2. Let the voltage at the sixth node be VF, the voltage at the upper clamping voltage terminal be Clamp_H, and the slope compensation peak current be I_slope_DC, then VF = Clamp_H + Islope_DC * R4. The sampling node sum is connected to the positive input (+) of the pulse width modulation comparator PWM_COMP, the clamping node eaout is connected to the negative input (-) of the pulse width modulation comparator PWM_COMP, and the output of the pulse width modulation comparator PWM_COMP is connected to the main flip signal terminal to output the main flip signal MAIN_TRIP.

[0022] Peak current mode BOOST converters are widely used in BOOST converter architectures due to their relatively simple loop compensation method. When the duty cycle is greater than 50%, slope compensation needs to be added to the current loop to eliminate subharmonic oscillations. However, after adding slope compensation, the peak inductor current decreases, resulting in a lower BOOST load-carrying capacity. To address this, this invention employs slope compensation recovery circuit technology. By raising the clamping voltage on the error amplifier when current limiting occurs and canceling out the peak value of the slope compensation current during current limiting, the maximum peak current of the BOOST converter is not affected by slope compensation, achieving the effect that the maximum peak current of the BOOST converter does not change with the duty cycle.

[0023] The circuit designed in this article is as follows: Figure 1 As shown, resistors R1 and R2, along with switches S1 and S2 and capacitors C1 and C2, form a sample-and-hold circuit. This circuit transmits the peak value of the slope compensation current as a DC current to point E. The buffer formed by AMP3, MN1, and R2 converts voltage to current. Through the mirror relationship between MP3 and MP1, the peak slope compensation current I_slope_DC is superimposed onto R4 as a DC current. AMP2, MN2, R4, AMP1, and MP4 constitute the dynamic clamping circuit for eaout. The voltage at point F is the peak value of the slope compensation superimposed on the fixed clamping value Clamp_H of eaout. The expression for the voltage at point F is:

[0024] VF = Clamp_H + Islope_DC * R4

[0025] The higher the duty cycle, the higher the slope compensation peak value, which in turn results in a higher voltage at point F, ensuring a larger eaout clamping value.

[0026] Under medium load, eaout is low, MP4 is insufficient to conduct, the upper clamping circuit composed of AMP1 and MP4 does not function, and dynamic clamping does not affect the normal value of eaout.

[0027] When the load increases to the point where MP4 is turned on, eaout is clamped to the same voltage as point F. This ensures that the dynamic clamping on eaout completely cancels out the peak value of Islope*R3, the slope compensation information at the sum point. At the PWM comparator, this is equivalent to comparing two quantities that are completely unrelated to the slope compensation peak value. Therefore, after adopting the slope recovery technology in this design, the peak value of the inductor current when the current limit value is reached is unrelated to the magnitude of the slope compensation current, thus ensuring that the current limit value of BOOST does not change with the duty cycle.

[0028] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A circuit that dynamically clamps the peak current modulus BOOST current limit value so that it does not change with the duty cycle, characterized in that, The system includes a sampling node and a clamping node for controlling the switching of a pulse width modulation comparator. The sampling node has a first path connected to the power supply voltage terminal via the lower transistor current sampling terminal, a second path grounded via a third resistor, and a third path connected to the output terminal of a slope compensation current circuit. The clamping node has a first path connected to the output terminal of an error amplifier, a second path connected to the negative input terminal of a first operational amplifier and the source of a fifth PMOS transistor, with the drain of the fifth PMOS transistor grounded. The gate of the fifth PMOS transistor is connected to the output terminal of the first operational amplifier. The positive input terminal of the first operational amplifier is connected to a sixth node. The sixth node has a first path connected to the output terminal of a slope compensation peak current circuit, and a second path connected via a fourth resistor to the positive input terminal of a second operational amplifier and the drain of a third NMOS transistor, with the gate of the third NMOS transistor connected to the output terminal of the second operational amplifier and the source of the third NMOS transistor grounded. The negative input terminal of the second operational amplifier is connected to the upper clamping voltage terminal. The slope compensation peak current circuit is connected to a sample-and-hold circuit via a voltage-to-current converter.

2. The circuit for achieving peak current mode BOOST current limiting value that does not change with duty cycle through dynamic clamping as described in claim 1, characterized in that, The slope compensation current circuit includes a first PMOS transistor and a third PMOS transistor with a common source and common gate. The source of the third PMOS transistor is connected to the power supply voltage terminal, and the drain of the third PMOS transistor is connected to the sampling node. The gate and drain of the first PMOS transistor are interconnected and then connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the sawtooth wave voltage terminal generated by the internal clock. The source of the first NMOS transistor is connected to the first node, and the first node is grounded through a first resistor.

3. The circuit for achieving peak current mode BOOST current limiting value that does not change with duty cycle through dynamic clamping as described in claim 2, characterized in that, The sample-and-hold circuit includes a first switch, one end of which is connected to the first node and the other end of which is connected to the second node. The second node is grounded through a first capacitor and the second path is connected to a fourth node through a second switch. The fourth node is grounded through a second capacitor and the second path is connected to the voltage-to-current circuit.

4. The circuit for achieving peak current mode BOOST current limiting value that does not change with duty cycle through dynamic clamping according to claim 3, characterized in that, The voltage-to-current conversion circuit includes a third operational amplifier. The positive input terminal of the third operational amplifier is connected to the fourth node, and the negative input terminal of the third operational amplifier is connected to the fifth node. The fifth node has a first path grounded through a second resistor, a second path connected to the source of a second NMOS transistor, the gate of the second NMOS transistor connected to the output terminal of the third operational amplifier, and the drain of the second NMOS transistor connected to the slope compensation peak current circuit.

5. The circuit for achieving peak current mode BOOST current limiting value that does not change with duty cycle through dynamic clamping according to claim 4, characterized in that, The slope compensation peak current circuit includes a second PMOS transistor and a fourth PMOS transistor with a common source and common gate. The source of the fourth PMOS transistor is connected to the power supply voltage terminal, and the drain of the fourth PMOS transistor is connected to the sixth node. The slope compensation peak current flows from the drain of the fourth PMOS transistor through the sixth node and through the fourth resistor. The gate and drain of the second PMOS transistor are interconnected and then connected to the drain of the second NMOS transistor.

6. The circuit for achieving peak current mode BOOST current limiting value that does not change with duty cycle through dynamic clamping according to claim 5, characterized in that, Let the resistance of the first resistor be R1 and the resistance of the second resistor be R2, then R1 = R2.

7. The circuit for achieving peak current modulus BOOST current limiting value that does not change with duty cycle through dynamic clamping according to claim 6, characterized in that, Let the voltage of the sixth node be VF, the voltage of the upper clamping voltage terminal be Clamp_H, and the slope compensation peak current be I_slope_DC, then VF = Clamp_H + Islope_DC * R4.

8. The circuit for achieving peak current mode BOOST current limiting value that does not change with duty cycle through dynamic clamping according to claim 1, characterized in that, The sampling node is connected to the positive input of the pulse width modulation comparator, the clamping node is connected to the negative input of the pulse width modulation comparator, and the output of the pulse width modulation comparator is connected to the main flip signal terminal to output the main flip signal MAIN_TRIP.

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