Displaying by on-chip cache flush

Abstract

Using on-chip cache to refresh a display is disclosed, including determining that a static display condition has been met; storing first display data in a cache memory of a processor; and displaying the first display data from the cache memory.

Description

BACKGROUND

[0001] When a display is in a static screen state, the display still needs to be periodically refreshed. Typically, to refresh the display, display data is loaded from memory by a display controller and presented on the display. In cases where the memory subsystem is in an idle low power state due to system or user inactivity, the memory subsystem must be woken up in order to load the display data. Thus, the memory subsystem likely saves less power due to entering a low power state because it is difficult to enter or remain in a low power state. BRIEF DESCRIPTION OF DRAWINGS

[0002] Figure 1 is a block diagram of an exemplary apparatus for refreshing a display through an on-chip cache according to some embodiments.

[0003] Figure 2 is a flowchart of an exemplary method for refreshing a display through an on-chip cache according to some embodiments.

[0004] Figure 3 is a flowchart of an exemplary method for refreshing a display through an on-chip cache according to some embodiments.

[0005] Figure 4 is a flowchart of an exemplary method for refreshing a display through an on-chip cache according to some embodiments.

[0006] Figure 5 is a flowchart of an exemplary method for refreshing a display through an on-chip cache according to some embodiments.

[0007] Figure 6 is a flowchart of an exemplary method for refreshing a display through an on-chip cache according to some embodiments. DETAILED DESCRIPTION

[0008] In some embodiments, a method of refreshing a display through an on-chip cache is disclosed, the method comprising: determining that a static display condition has been met; storing first display data in a cache memory of a processor; and displaying the first display data from the cache memory.

[0009] In some embodiments, determining that the static display condition has been met comprises determining that a static image is to be displayed and determining that one or more clients of the memory subsystem are idle. In some embodiments, the cache memory comprises last level cache (LLC) memory. In some embodiments, the method further comprises causing the memory subsystem to enter a reduced power state. In some embodiments, determining that the static display condition has been met is performed by an operating system, and the method further comprises the operating system sending an indication to the processor that the static display condition has been met. In some embodiments, the method further comprises determining that the static display condition is no longer met, loading second display data from memory, and displaying the second display data. In some embodiments, the method further comprises loading the first display data from memory.

[0010] In some embodiments, an apparatus for refreshing a display through on-chip cache is disclosed, the apparatus performing steps comprising: determining that a static display condition has been met; storing first display data in cache memory of a processor; and displaying the first display data from the cache memory.

[0011] In some embodiments, determining that the static display condition has been met comprises determining that a static image is to be displayed and determining that one or more clients of the memory subsystem are idle. In some embodiments, the cache memory comprises last level cache (LLC) memory. In some embodiments, the steps further comprise causing the memory subsystem to enter a reduced power state. In some embodiments, determining that the static display condition has been met is performed by an operating system, and the steps further comprise the operating system sending an indication to the processor that the static display condition has been met. In some embodiments, the steps further comprise determining that the static display condition is no longer met, loading second display data from memory, and displaying the second display data. In some embodiments, the steps further comprise loading the first display data from memory.

[0012] In some embodiments, a computer program product is disclosed, the computer program product being stored on a non-transitory computer readable medium, the computer program product storing computer program instructions for refreshing a display through on-chip cache, the computer program instructions, when executed, causing a computer system to perform steps comprising: determining that a static display condition has been met; storing first display data in cache memory of a processor; and displaying the first display data from the cache memory.

[0013] In some embodiments, determining that the static display condition has been satisfied comprises determining that a static image is to be displayed and determining that one or more clients of the memory sub-system are idle. In some embodiments, the cache memory comprises last level cache (LLC) memory. In some embodiments, the steps further comprise causing the memory sub-system to enter a reduced power state. In some embodiments, determining that the static display condition has been satisfied is performed by an operating system, and the steps further comprise the operating system sending an indication to the processor that the static display condition has been satisfied. In some embodiments, the steps further comprise determining that the static display condition is no longer satisfied, loading second display data from memory, and displaying the second display data. In some embodiments, the steps further comprise loading the first display data from memory.

[0014] When a display is in a static screen condition, it is still necessary to periodically refresh the display. A display is considered to be in a static screen condition when it is presenting a static, unchanging image for some period of time. Typically, to refresh a display, display data is loaded from memory by a display controller and presented on the display. In the case where a memory sub-system is in an idle, low power state due to system or user inactivity, the memory sub-system must be awakened in order to load the display data. The rate at which the memory sub-system is awakened and the display data is loaded depends on the resolution of the display, the refresh rate of the display, the number of displays used, and the size of the on-chip display buffer. Memory sub-systems are one of the major consumers of system power. Because the display must be periodically refreshed, large resolution displays, particularly when multiple displays are used, prevent the memory sub-system from entering or remaining in a low power state. Thus, the memory sub-system likely saves less power from entering a low power state because it is difficult to enter or remain in a low power state.

[0015] To address the memory sub-system power consumption problem caused by periodically refreshing a display, Figure 1 is a block diagram of a non-limiting exemplary apparatus 100 for refreshing a display through an on-chip cache. Exemplary apparatus 100 can be implemented in various ways, such as a motherboard of a computing device or as a graphics processor (GPU). Thus, apparatus 100 can be operatively coupled to various other components or devices and implemented in various devices or systems, including computing devices, such as mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like. Apparatus 100 can also be implemented as multiple operative components in the same system, such as the computing devices described above.

[0016] The device 100 includes a processor 102. The processor 102 is a die that includes various integrated circuits, functions, and logic components. For example, in some embodiments, the processor 102 includes a central processing unit (CPU). In other embodiments, the processor 102 includes a hardware accelerator such as a GPU or other component. In some embodiments, the processor 102 includes a system on a chip.

[0017] The processor 102 includes a display controller 104. The display controller 104 includes one or more integrated circuits or logic components that generate a video signal for output to a display 106. For example, the display controller 104 generates a video signal based on display data that encodes an image or frame to be displayed. To do so, the display controller 104 loads a portion of the display data into a display buffer 108 and generates a video signal for the display 106 based on the portion of the display data 107 in the display buffer 108. The display buffer 108 is a dedicated portion of memory (e.g., on-chip memory) into which the portion of the display data 107 is loaded to be encoded into a video signal. Thus, to generate a single frame or refresh of the display, in some embodiments, the portion of the display data 107 must be repeatedly loaded into the display buffer 108, thereby overwriting the previously loaded portion of the display data 107. Although the display controller 104 and the display buffer 108 are shown as components of the processor 102, it should be understood that, in some embodiments, the device 100 includes the display controller 104 and the display buffer 108 separate from the processor 102 (e.g., as separate components of a motherboard or other components that operably couple the processor 102 to the display controller 104 and the display buffer 108).

[0018] The device 100 also includes a memory subsystem 110. The memory subsystem 110 includes functional components for storing data in memory. For example, the memory subsystem 110 includes one or more memory controllers 112. The memory controllers 112 perform received read and write operations on memory modules 114. The memory controllers 112 also refresh the memory modules 114 as necessary in order to maintain data integrity. The memory modules 114 are random access memories (RAMs) that include dynamic random access memories (DRAMs) or other types of RAMs as can be appreciated.

[0019] Returning to the processor 102, the processor 102 also includes a cache 116. The cache 116 is on-chip or on-die memory used to store data so that the processor 102 can access it quickly. Thus, data stored in the cache 116 frequently mirrors data stored in the memory module 114. In some embodiments, the cache 116 includes last level cache (LLC) memory. The LLC memory is the highest level of the cache 116 and is shared by multiple functional units of the chip (e.g., by multiple functional components of the processor 102).

[0020] The processor 102 also includes a power management controller 118. The power management controller 118 is a microcontroller or logic block that controls the power functions of the device 100. For example, the power management controller 118 monitors power connections and battery charging, controls power to various components including the processor 102 and the memory subsystem 110, powers down idle system components, controls the operating power mode (e.g., full power, low power) of system components, etc. For example, as will be described in further detail below, the power management controller 118 controls whether the memory subsystem 110 is operating in a full power consumption mode or a reduced or low power consumption mode if idle.

[0021] To refresh the display 106 during normal operation (e.g., when the display data 107 is dynamic across frames and various clients of the cache 116 are active), the display controller 104 loads the display data 107 from the memory module 114. For example, the display data 107 is generated by the operating system 120 according to various operations or applications being executed and stored in the memory module 114. The display controller 104 then loads portions of the display data 107 from the memory module 114 into the display buffer 108 and generates a video signal based on the buffered display data 107 to output to the display 106.

[0022] The device 100 determines whether the static display condition has been satisfied. The static display condition is satisfied when the display data 107 that is to be displayed over time is a static (e.g., unchanging) image. Thus, determining whether the static display condition has been satisfied includes determining that a static image is to be displayed. For example, in some embodiments, determining that a static image is to be displayed includes determining that a mouse, cursor, or other user interface element is idle. Determining that a user interface element is idle includes determining that no input has been received from a mouse, keyboard, or other input device for some period of time (e.g., within a time window or threshold). In some embodiments, determining that a static image is to be displayed includes determining that one or more multimedia or graphics clients (e.g., a video player, a game, etc.) are not executing, are idle, or are not rendering any display data 107. Because no clients are rendering changing display data 107 and because no user interface elements are changing, the display data 107 will reflect a static image.

[0023] Because the methods described herein rely on the use of the on-chip cache 116, in some embodiments, determining that the static display condition has been satisfied further includes determining that one or more clients of the memory subsystem 100 are idle. A client of the memory subsystem 110 is any software or hardware component that is able to access the memory subsystem 110 to facilitate its operation. Thus, such clients include graphics processes, multimedia processes (e.g., encoding or decoding engines), or any other clients as can be appreciated.

[0024] In some embodiments, determining that the static display condition is satisfied is performed by the operating system 120. For example, the operating system 120 monitors input devices to determine that a cursor, mouse pointer, or other user interface element is not changing or moving. As another example, the operating system 120 monitors active processes or services that are being executed to determine whether a client of the cache 116 is idle. Thus, in some embodiments, in response to determining that the static display condition is satisfied, the operating system 120 generates a signal or other indication to the processor 102 that the static display condition is satisfied.

[0025] The display controller 104 then loads the display data 107 from the memory module 114 (e.g., in response to an indication from the operating system 120 that the static display condition is satisfied). The loaded display data 107 corresponds to a static image to be displayed on the display 106. The display controller 104 then stores the display data 107 in the cache 116 (e.g., in LLC memory). Since the client of the cache 116 is idle, and thus not actively accessing the cache 116, storing the display data 107 in the cache 116 does not interfere with the operation of any clients of the cache 116. The display controller 104 then displays the display data 107 from the cache 116. For example, the display controller 104 generates a video signal based on the display data 107 stored in the cache 116.

[0026] As described above, the display data 107 presented by the display controller 104 is loaded from the cache 116. Thus, the memory subsystem 110 does not need to be in an active or awake state for the display controller 104 to load the display data 107 from the memory module 114. Accordingly, in some embodiments, in response to an indication from the operating system 120 that the static display condition has been satisfied, the power management controller 118 causes the memory subsystem 110 to enter a reduced power state. By entering the reduced power state, the memory subsystem 110 generally consumes less power. For example, in response to an indication from the display controller 104 that the display data 107 has been loaded from the memory module 114 into the cache 116, the power management controller 118 causes the memory subsystem 110 to enter the reduced power state.

[0027] The device 100 also determines (e.g., by the operating system 120, by other processes or functional components) that the static display condition is no longer satisfied. For example, in response to input to an input device such as a keyboard or mouse that causes a user interface element (e.g., a cursor or mouse pointer) to move, the static display condition is no longer satisfied. As another example, the static display condition is no longer satisfied when an application, service, or other software module (e.g., a multimedia software) causes updated display data 107 to be presented. As another example, the static display condition is no longer satisfied when the client of the cache 116 is no longer idle. Accordingly, the display controller 104 reverts to loading the display data 107 from the memory module 114 and displaying the display data 107 loaded from the memory module 114. Thus, the client of the cache 116 is free to use the cache 116 to perform its operations. In embodiments in which the power management controller 118 caused the memory subsystem 110 to enter a reduced power state, the power management controller 118 causes the memory subsystem 110 to exit the reduced power state so that display data 107 can be loaded from the memory module 114.

[0028] By displaying display data 107 from cache 116 while in a static display state (e.g., when a static display condition is satisfied), the refresh of display 106 does not require access to memory subsystem 110. Accordingly, memory subsystem 110 is able to enter a reduced power state, thereby reducing overall power consumption while in a static display state. Moreover, because the size of cache 116 tends to be relatively large compared to display buffer 108, cache 116 is able to store the entire static display data 107, even when multiple displays 106 are used and have high resolutions.

[0029] To further explain, Figure 2 A flowchart illustrating an example method for refreshing a display through an on-chip cache is set forth, the example method including determining 202 (e.g., by apparatus 100) that a static display condition has been satisfied. The static display condition is satisfied when the display data 107 to be displayed over time is a static (e.g., unchanging) image. Accordingly, for a static image to be displayed, a mouse pointer, cursor, or other user interface element must remain static over time. Additionally, no multimedia, graphics, or other dynamic content is being displayed. When the static display condition has been satisfied, the display data 107 to be displayed will remain unchanged.

[0030] Figure 2 The method of FIG. 1 further includes storing 204 first display data 107 in cache 116 memory of processor 102. The first display data 107 corresponds to a static image to be displayed on display 106. In some embodiments, storing 204 the first display data 107 in cache 116 includes loading the first display data 107 from memory (e.g., from memory module 114). Display controller 104 then stores the display data 107 in cache 116 (e.g., in LLC memory).

[0031] Figure 2 The method of FIG. 1 further includes displaying 206 the first display data 107 from cache 116 memory. For example, display controller 104 generates a video signal based on the display data 107 stored in cache 116. As long as the static display condition continues to be satisfied, the first display data 107 is continued to be displayed from cache 116. Accordingly, the attached display 106 is able to be refreshed without accessing memory subsystem 110.

[0032] To further explain, Figure 3A flowchart illustrating an exemplary method for refreshing a display via an on-chip cache is provided. The exemplary method includes (e.g., by device 100) determining that 202 has met static display conditions; storing 204 first display data 107 in cache 116 memory of processor 102; and displaying 206 the first display data 107 from cache 116 memory.

[0033] Figure 3 and Figure 2 The difference lies in that determining 202 that the static display condition has been met includes determining 302 that a static image will be displayed. For example, in some embodiments, determining that a static image will be displayed includes determining that the mouse, cursor, or other user interface element is idle. Determining that a user interface element is idle includes determining that no input has been received from the mouse, keyboard, or other input device for a certain period of time (e.g., within a time window or threshold). In some embodiments, determining that a static image will be displayed includes determining that one or more multimedia or graphical clients (e.g., video players, games, etc.) are not running, are idle, or are not presenting any display data 107. Since no client is presenting changing display data 107 and since no user interface element is changing, the display data 107 will reflect a static image.

[0034] Figure 3 and Figure 2 The difference lies in that determining 202 that the static display condition has been met includes determining 304 that one or more clients of the memory of the memory subsystem 110 are idle. Clients of the memory subsystem 110 are any software or hardware components capable of accessing the memory subsystem 110 to facilitate its operation. Therefore, such clients include graphics processes, multimedia processes (e.g., encoding or decoding engines), or any other understandable client. When such clients are idle, the memory subsystem 110 can enter a power-reduction state, thereby saving more power.

[0035] To further explain, Figure 4 A flowchart illustrating an exemplary method for refreshing a display via an on-chip cache is provided. The exemplary method includes (e.g., by device 100) determining that 202 has met static display conditions; storing 204 first display data 107 in cache 116 memory of processor 102; and displaying 206 the first display data 107 from cache 116 memory.

[0036] Figure 4 and Figure 2 The difference is that, Figure 4The method includes putting the memory subsystem 110 into a power-reducing state. As described above, first display data 107 presented by the display controller 104 is loaded from cache 116. Therefore, the memory subsystem 110 does not need to be in an active or wake-up state for the display controller 104 to load the first display data 107 from the memory module 114. By entering a power-reducing state, the memory subsystem 110 consumes less power overall. For example, in response to an indication from the display controller 104 indicating that the first display data 107 has been loaded from the memory module 114 into the cache 116, the power management controller 118 puts the memory subsystem 110 into a power-reducing state.

[0037] To further explain, Figure 5 A flowchart illustrating an exemplary method for refreshing a display via an on-chip cache is provided. The exemplary method includes (e.g., by device 100) determining that 202 has met static display conditions; storing 204 first display data 107 in cache 116 memory of processor 102; and displaying 206 the first display data 107 from cache 116 memory.

[0038] Figure 5 and Figure 2 The difference is that, Figure 5 The method includes the operating system 120 sending an indication 502 that the static display condition has been met to the processor 102. In some embodiments, determining 202 that the static display condition is met is performed by the operating system 120. For example, the operating system 120 monitors the input device to determine that the cursor, mouse pointer, or other user interface elements have not changed or moved. As another example, the operating system 120 monitors active processes or services that are being executed to determine whether the client in cache 116 is idle. Therefore, in some embodiments, in response to determining that the static display condition is met, the operating system 120 generates a signal or other indication to the processor 102 that the static display condition is met.

[0039] To further explain, Figure 6 A flowchart illustrating an exemplary method for refreshing a display via an on-chip cache is provided. The exemplary method includes (e.g., by device 100) determining that 202 has met static display conditions; storing 204 first display data 107 in cache 116 memory of processor 102; and displaying 206 the first display data 107 from cache 116 memory.

[0040] Figure 6 and Figure 2 The difference is that, Figure 6The method includes determining that the static display condition is no longer met at 602. For example, the static display condition is no longer met in response to input from an input device such as a keyboard or mouse, which causes a user interface element (e.g., a cursor or mouse pointer) to move. As another example, the static display condition is no longer met when an application, service, or other software module (e.g., multimedia software) causes updated second display data 107 to be presented. As yet another example, the static display condition is no longer met when the client in cache 116 is no longer idle.

[0041] Figure 6 The method also includes loading 604 of second display data 107 from memory (e.g., from memory module 114). In an embodiment where the power management controller 118 causes the memory subsystem 110 to enter a reduced power state, loading 604 of the second display data 107 from memory includes causing the memory subsystem 110 to exit the reduced power state (e.g., "wake up" the memory subsystem 110). The second display data 107 is loaded from memory into display buffer 108. Figure 6 The method also includes displaying second display data 107. For example, display controller 104 generates a video signal based on the second display data 107 stored in display buffer 108. Therefore, when static display conditions are not met, display data 107 loaded from memory is used to refresh display 106.

[0042] Based on the explanations above, the reader will recognize that the beneficial effects of refreshing the display through on-chip cache include:

[0043] • By ensuring that the display can be refreshed without accessing or waking the memory subsystem, the performance of computing systems with reduced power usage during idle static screen scenarios is improved.

[0044] The exemplary embodiments of this disclosure are described primarily in the context of a full-featured computer system for refreshing a display via an on-chip cache. However, those skilled in the art will recognize that this disclosure can also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium can be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include disks in hard disk drives or floppy disks, optical disks in optical disk drives, magnetic tapes, and other media conceivable to those skilled in the art. Those skilled in the art will readily recognize that any computer system with appropriate programming means will be able to perform the steps of the methods of this disclosure as embodied in a computer program product. Those skilled in the art will also recognize that while some exemplary embodiments described in this specification are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or hardware are also within the scope of this disclosure.

[0045] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to perform aspects of this disclosure.

[0046] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be (e.g., but not limited to) electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A less complete list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanically encoded devices (such as punched cards or raised structures in slots on which instructions are recorded), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as instantaneous signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0047] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0048] Computer-readable program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet through an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions, specifically by using state information from the computer-readable program instructions to personalize the electronic circuitry to perform aspects of this disclosure.

[0049] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0050] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to obtain a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, form components for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of writing containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0051] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to obtain a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0052] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible specific implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may not occur in the order shown in the figures. For example, depending on the functions involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0053] As will be understood from the foregoing description, modifications and changes can be made to various embodiments of this disclosure. The description in this specification is for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is defined only by the language of the appended claims.

Claims

1. A method for refreshing a display using an on-chip cache, the method comprising: It has been determined that the conditions for static display have been met; In response to determining that the static display conditions have been met, the first display data is stored in the processor's cache memory; Receive an indication from the display controller that the first display data has been stored in the cache memory by the display controller; In response to receiving the instruction, the memory subsystem enters a power reduction state; as well as The first display data is displayed from the cache memory.

2. The method according to claim 1, wherein determining that the static display condition has been met includes: The image will be displayed as static. as well as It is determined that one or more clients of the memory subsystem are idle.

3. The method according to claim 1, wherein the cache memory includes a last-level cache (LLC) memory.

4. The method according to claim 1, wherein the cache memory is contained within the processor.

5. The method of claim 1, wherein the determination that the static display condition has been met is performed by the operating system, and the method further comprises the operating system sending an indication to the processor that the static display condition has been met.

6. The method according to claim 1, further comprising: It has been determined that the static display condition is no longer met; Load the second display data from memory; as well as The second set of display data is displayed.

7. The method of claim 1, further comprising loading the first display data from memory.

8. An apparatus for refreshing a display via an on-chip cache, the apparatus comprising: processor; and a memory operatively coupled to the processor, the memory including a computer program that, when executed by the processor, is configured to: It has been determined that the conditions for static display have been met; In response to determining that the static display conditions have been met, the first display data is stored in the processor's cache memory; Receive an indication from the display controller that the first display data has been stored in the cache memory; In response to receiving the instruction, the memory subsystem enters a power reduction state; as well as The first display data is displayed from the cache memory.

9. The apparatus of claim 8, wherein determining that the static display condition has been met includes: The image will be displayed as static. as well as It is determined that one or more clients of the memory subsystem are idle.

10. The apparatus of claim 8, wherein the cache memory includes a last-level cache (LLC) memory.

11. The apparatus of claim 8, wherein the cache memory is contained within the processor.

12. The apparatus of claim 8, wherein the determination that the static display condition has been met is performed by an operating system, and the apparatus further comprises computer program instructions, which, when executed by the processor, are configured to send an indication to the processor via the operating system that the static display condition has been met.

13. The apparatus of claim 8, further comprising computer program instructions, which, when executed by the processor, are configured to... It has been determined that the static display condition is no longer met; Load the second display data from memory; as well as The second set of display data is displayed.

14. The apparatus of claim 8, further comprising computer program instructions, which, when executed by the processor, are configured to load the first display data from memory.

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