Layer 2 data processing apparatus and method using flexible layer 2 circuits

Abstract

According to one aspect of the present disclosure, a baseband chip may include a plurality of layer 2 circuits, each layer 2 circuit being configured to perform layer 2 data processing operations associated with a first radio access technology (RAT) and a second RAT. In some aspects, the first RAT and the second RAT may be different. The baseband chip may also include a microcontroller unit (MCU) configured to program the plurality of layer 2 circuits to perform layer 2 data processing operations associated with the first RAT or the second RAT.

Description

Background Art

[0001] Embodiments of the present disclosure relate to apparatus and methods for wireless communications.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services, such as telephony, video, data, messaging, and broadcasting. Radio access technology (RAT) is the underlying physical connection method for radio-based communication networks. Many modern terminal devices, such as mobile devices, support multiple RATs in one device. In cellular communications such as fourth generation (4G) long term evolution (LTE) and fifth generation (5G) new radio (NR), the third generation partnership project (3GPP) defines radio layer 2 (herein referred to as "layer 2") as part of a cellular protocol stack structure corresponding to the data plane (DP) (also referred to as the "user plane"), which includes a packet data convergence protocol (PDCP) layer, a radio link control (RLC) layer, and a media access control (MAC) layer from high to low in the stack. In some wireless communications (e.g., Wi-Fi), the Institute of Electrical and Electronics Engineers (IEEE) Standards Committee (802.11) defines Layer 2 as a part of the Wi-Fi protocol stack structure corresponding to the data plane, which includes a MAC packet data unit (MPDU), a block acknowledgement (BA), and an aggregated MAC packet data unit (AMPDU) from high to low in the stack. Summary of the invention

[0003] Embodiments of apparatus and methods for layer 2 data processing are disclosed herein.

[0004] According to one aspect of the present disclosure, a baseband chip may include a plurality of layer 2 circuits, each layer 2 circuit being configured to perform layer 2 data processing operations associated with a first RAT and a second RAT. In some aspects, the first RAT and the second RAT may be different. The baseband chip may also include a microcontroller unit (MCU) configured to program the plurality of layer 2 circuits to perform layer 2 data processing operations associated with the first RAT or the second RAT.

[0005] According to another aspect of the present disclosure, a baseband chip includes a first layer 2 circuit configured to control a MAC operation associated with a first RAT and an AMPDU operation associated with a second RAT. The baseband chip may also include a second layer 2 circuit configured to perform an RLC operation associated with the first RAT and a BA operation associated with the second RAT. The baseband chip may also include a third layer 2 circuit configured to perform a PDCP operation associated with the first RAT and an MPDU operation associated with the second RAT.

[0006] According to another aspect of the present disclosure, a method of layer 2 data processing may include: identifying whether a data packet is associated with a first RAT or a second RAT. The method may also include: in response to determining that the data packet is associated with the first RAT, programming a plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT. The method may also include: in response to determining that the data packet is associated with the second RAT, programming a plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0008] Figure 1 An exemplary wireless network according to some embodiments of the present disclosure is shown.

[0009] Figure 2 A block diagram of a device including a baseband chip, a radio frequency (RF) chip, and a host chip according to some embodiments of the present disclosure is shown.

[0010] Figure 3 A block diagram of an exemplary baseband chip according to some embodiments of the present disclosure is shown.

[0011] FIG. 4A to FIG. 4C The use of some embodiments of the present disclosure is shown Figure 3 The baseband chip's uplink (UL) layer 2 data processing data stream.

[0012] FIG. 5A to FIG. 5C The use of some embodiments of the present disclosure is shown Figure 3 The baseband chip's downlink (DL) layer 2 data processes the data flow.

[0013] Figure 6 A flow chart of an exemplary method for layer 2 data processing according to some embodiments of the present disclosure is shown.

[0014] Figure 7 A block diagram of an exemplary node according to some embodiments of the present disclosure is shown.

[0015] Figure 8 A block diagram of a conventional baseband chip is shown.

[0016] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0017] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0018] It should be noted that when the specification refers to "one embodiment", "an embodiment", "an example embodiment", "some embodiments", "certain embodiments", etc., it indicates that the described embodiment may include a particular feature, structure or characteristic, but every embodiment may not necessarily include the particular feature, structure or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure or characteristic is described in conjunction with an embodiment, it would be within the knowledge of a person skilled in the relevant art to implement such feature, structure or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0019] Typically, a term can be understood, at least in part, from its use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "an" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey a set of exclusive factors, but can allow for the presence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0020] Various aspects of the wireless communication system will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the detailed description below and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether these elements are implemented as hardware, firmware, or software depends on the specific application and the design constraints imposed on the overall system.

[0021] The techniques described herein can be used in various wireless communication networks, such as code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single carrier frequency division multiple access (SC-FDMA) systems, wireless local area network (WLAN) systems, and other networks. The terms "network" and "system" are often used interchangeably. A CDMA network can implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), Evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network can implement a RAT, such as GSM. An OFDMA network can implement a first RAT, such as LTE or NR. A WLAN system can implement a second RAT, such as Wi-Fi. The techniques described herein can be used in the above wireless networks and RATs, as well as other wireless networks and RATs.

[0022] In cellular and / or Wi-Fi communications, Layer 2 is the protocol stack layer responsible for ensuring a reliable, error-free data link for the UE's wireless modem (referred to herein as the "baseband chip"). More specifically, Layer 2 interfaces with Radio Layer 1 (also referred to as "Layer 1" or "Physical (PHY) Layer") and Radio Layer 3 (also referred to as "Layer 3" or "Internet Protocol (IP) Layer"), passing packets up or down the protocol stack structure depending on whether the packet is associated with an uplink (UL) transmission or a downlink (DL) transmission.

[0023] In addition, Layer 2 can perform demultiplexing / multiplexing, segmentation / reassembly, aggregation / deaggregation, and sliding window automatic repeat request (ARQ) techniques, etc., to ensure reliable end-to-end data integrity and in-order error-free delivery of data packets. For UL data packets, L3 data packets (e.g., IP data packets) can be input into the L2 protocol stack and encoded into MAC layer packets (e.g., 5GNR) or AMPDU layer packets (e.g., Wi-Fi) for transmission to the PHY layer. For DL ​​data packets, Layer 1 data packets (e.g., PHY layer data packets) can be input into the L2 protocol stack, where Layer 2 data processing operations are performed on the data packets before passing the data packets up to Layer 3.

[0024] Conventionally, baseband chips can be designed as single-mode or multi-mode. An independent baseband chip can be designed with a single RAT-specific protocol data stack. On the other hand, a multi-mode baseband chip can be designed with multiple RAT-specific protocol stacks. That is, a multi-mode baseband chip includes different protocol stacks, one for each RAT supported by the baseband chip.

[0025] Figure 8 8 shows a block diagram of a conventional baseband chip 800. Figure 8As seen in the figure, a conventional baseband chip 800 may include: a PHY subsystem 802, configured to send and / or receive data packets over an air interface; an L2 buffer 808, configured to buffer data packets between layer 1 and layer 2; a layer 2 subsystem 804, including a limited number of layer 2 hardware (HW) accelerators 806, a general-purpose main processor 828, the general-purpose main processor 828 including a layer 2 processor for multiple RATs and / or layer 2 software (SR) 836; a control plane device 826, external to the layer 2 main processor 828; a layer 3 (L3) external DDR memory 830; a layer 3 and / or layer 4 subsystem 832; and an application processor (AP) host 834.

[0026] Figure 8 The conventional baseband chip 800 shown in FIG. 8 uses a software-centric layer 2 protocol data stack. That is, the data stack processing resides on the layer 2 host processor 828 and uses a limited number of HW accelerators 806. Using the conventional baseband chip 800, the layer 2 host processor 828 can access data packets from the PHY layer memory at one or more PHY subsystems 802 through direct memory access (DMA). In addition, the HW accelerator 806 can DMA the UL data packets to the layer 3 external DDR memory 830.

[0027] In a conventional baseband chip 800, layer 2 data processing (e.g., processing a transport block received from layer 1 (e.g., PHY subsystem 802) in a DL user plane, or processing a data packet received from layer 3 in a UL user plane) is typically implemented using a software module executed on a general-purpose baseband processor such as a central processing unit (CPU) or a digital signal processor (DSP). During processing, data may be frequently transferred between a general-purpose main processor 828 and an external memory (e.g., layer 3 external DDR memory or layer 2 buffer 808), for example, to buffer between each layer. Therefore, known solutions for layer 2 data processing have problems such as high power consumption, large data buffers, and long processing delays. In addition, due to the increased number of processors and / or HW accelerators 806 dedicated to different RATs, the conventional baseband chip 800 may occupy an undesirable amount of area. Further, the different layer 2 protocol data stacks in the conventional baseband chip 800 may be inflexible because they may not be able to adapt to changes in the 3GPP and / or IEEE 802.11 standards.

[0028] Therefore, there is an unmet need for a baseband chip including a single set of layer 2 protocol data stack components that are configurable to perform data processing operations associated with a first RAT and a second RAT.

[0029] The baseband chip of the present invention provides a solution using the same set of layer 2 circuits that are dynamically configurable to perform high-performance, low-latency layer 2 data processing associated with multiple RATs. In addition, using one or more microcontroller units (MCUs), a single set of layer 2 circuits can be used to design the sequence and timing triggers for each layer 2 data processing pipeline stage for each use case, technology, and mode. By using the same set of layer 2 circuits, the baseband chip of the present disclosure uses a reduced amount of power and occupies a smaller amount of area compared to conventional baseband chips, for example, as shown below in combination with Figures 1 to 7 Just as described.

[0030] Figure 1 1 shows an exemplary wireless network 100 in accordance with some embodiments of the present disclosure, in which certain aspects of the present disclosure may be implemented. Figure 1 As shown, the wireless network 100 may include a node network, such as UE 102, access node 104, and core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle-to-everything (V2X) network, a cluster network, a smart grid node, or an Internet of Things (IoT) node. It should be understood that, as an illustration and not a limitation, user equipment 102 is simply shown as a mobile phone.

[0031] The access node 104 may be a device that communicates with the user equipment 102, such as a wireless access point, a base station (BS), a node B, an enhanced node B (eNodeB or eNB), a next generation node B (gNodeB or gNB), a cluster master node, etc. The access node 104 may have a wired connection to the user equipment 102, a wireless connection to the user equipment 102, or any combination thereof. The access node 104 may be connected to the user equipment 102 via multiple connections, and the user equipment 102 may be connected to other access nodes in addition to the access node 104. The access node 104 may also be connected to other user equipment. It should be understood that the access node 104 is shown as a radio tower as an illustration and not limitation.

[0032] The core network element 106 can serve the access node 104 and the user equipment 102 to provide core network services. Examples of the core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system (which is the core network of an LTE system). Other core network elements may be used in LTE and other communication systems. In some embodiments, the core network element 106 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device of the core network of the NR system. It will be appreciated that, as an illustration and not limitation, the core network element 106 is shown as a rack server group.

[0033] Core network element 106 may be connected to a larger network, such as Internet 108 or another Internet Protocol (IP) network, to transmit packet data over any distance. In this way, data from user device 102 may be transmitted to other user devices connected to other access points, such as computer 110 connected to Internet 108 (e.g., using a wired connection or a wireless connection), or tablet computer 112 connected to Internet 108 wirelessly via router 114. Thus, computer 110 and tablet computer 112 provide additional examples of possible user devices, while router 114 provides another example of a possible access node.

[0034] A general example of a rack-mounted server is provided as an illustration of the core network element 106. However, there may be multiple elements in the core network, including a database server (e.g., database 116) and a security and authentication server (e.g., authentication server 118). For example, database 116 can manage data related to a user's subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Similarly, authentication server 118 can handle authentication of users, sessions, etc. In an NR system, an authentication server function (AUSF) device can be a specific entity that performs user equipment authentication. In some embodiments, a single server rack can handle multiple such functions, so that the connection between the core network element 106, the authentication server 118, and the database 116 can be a local connection within a single rack.

[0035] Figure 1 Each element in the wireless network 100 may be considered a node. More details on possible implementations of the nodes are provided by way of example in Figure 7 Node 700 may be configured as Figure 1 102, access node 104 or core network element 106 in the embodiment. Similarly, node 700 may also be configured as Figure 1 Computer 110, router 114, tablet computer 112, database 116 or authentication server 118. Figure 7 As shown, the node 700 may include a processor 702, a memory 704, and a transceiver 706. These components are shown as being connected to each other via a bus, but other connection types are also allowed. When the node 700 is a user device 102, additional components may also be included, such as a user interface (UI), a sensor, etc. Similarly, when the node 700 is configured as a core network element 106, the node 700 may be implemented as a blade in a server system. Other implementations are also possible.

[0036] The transceiver 706 may include any suitable device for sending and / or receiving data. The node 700 may include one or more transceivers, although only one transceiver 706 is shown for simplicity of illustration. The antenna 708 is shown as a possible communication mechanism of the node 700. Multiple antennas and / or antenna arrays may be utilized. In addition, examples of the node 700 may communicate using wired technology instead of wireless technology (or may communicate using wired technology in addition to wireless technology). For example, the access node 104 may communicate wirelessly with the user equipment 102 and may communicate with the core network element 106 via a wired connection (e.g., via an optical cable or a coaxial cable). Other communication hardware may also be included, such as a network interface card (NIC).

[0037] like Figure 7 As shown, node 700 may include a processor 702. Although only one processor is shown, it should be understood that multiple processors may be included. Processor 702 may include a microprocessor, MCU, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), programmable logic device (PLD), state machine, gated logic, discrete hardware circuit, and other suitable hardware configured to perform various functions described in the full text of this disclosure. Processor 702 may be a hardware device with one or more processing cores. Processor 702 may execute software. Software should be broadly interpreted as referring to instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, etc., whether referring to software, firmware, middleware, microcode, hardware description language or other. Software may include computer instructions written in an interpreted language, a compiled language, or a machine code. Other techniques for indicating hardware are also allowed under a wide range of software categories.

[0038] like Figure 7As shown, node 700 may also include a memory 704. Although only one memory is shown, it should be understood that multiple memories may be included. Memory 704 may broadly include both memory and storage devices. For example, memory 704 may include random access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage devices, hard disk drives (HDD) (e.g., magnetic disk storage devices or other magnetic storage devices), flash drives, solid-state drives (SSD) or any other medium, which may be used to carry or store the desired program code in the form of instructions that can be accessed and executed by processor 702. Broadly speaking, memory 704 may be embodied by any computer-readable medium (e.g., non-temporary computer-readable medium).

[0039] The processor 702, the memory 704, and the transceiver 706 can be implemented in various forms in the node 700 to perform wireless communication functions. In some embodiments, the processor 702, the memory 704, and the transceiver 706 of the node 700 are implemented (e.g., integrated) on one or more systems on a chip (SoC). In one example, the processor 702 and the memory 704 can be integrated on an application processor (AP) SoC (sometimes referred to as a "host", referred to herein as a "host chip"), which handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, the processor 702 and the memory 704 can be integrated on a baseband processor (BP) SoC (sometimes referred to as a "modem", referred to herein as a "baseband chip"), which converts raw data from, for example, a host chip into a signal and vice versa, which can be used to modulate a carrier frequency for transmission, and the baseband processor (BP) SoC can run a real-time operating system (RTOS). In yet another example, the processor 702 and the transceiver 706 (and in some cases, the memory 704) can be integrated on an RF SoC (sometimes referred to as a "transceiver", herein referred to as an "RF chip"), which transmits and receives RF signals using an antenna 708. It will be appreciated that in some examples, some or all of the host chip, baseband chip, and RF chip can be integrated into a single SoC. For example, the baseband chip and the RF chip can be integrated into a single SoC that manages all radio functions for cellular communications.

[0040] Return to reference Figure 1In some embodiments, any suitable node of the wireless network 100 (e.g., the user device 102 or the access node 104) can use the same set of layer 2 circuits on the baseband chip (sometimes controlled by the MCU) to process layer 2 packets for the first RAT and the second RAT when transmitting a signal to another node (e.g., from the user device 102 to the access node 104, or vice versa), as described in detail below. Therefore, compared to known solutions that use software modules implemented on a general-purpose processor in conjunction with system memory to process layer 2 data, data speed can be increased due to hardware acceleration, chip cost can be reduced by reducing memory usage, and power consumption can also be reduced.

[0041] Figure 2 2 shows a block diagram of a device 200 including a baseband chip 202, an RF chip 204, and a host chip 206 according to some embodiments of the present disclosure. The device 200 may be Figure 1 Examples of any suitable node (e.g., user equipment 102 or network node 104) of the wireless network 100. Figure 2 As shown, the device 200 may include a baseband chip 202, an RF chip 204, a host chip 206, and one or more antennas 210. In some embodiments, the baseband chip 202 is implemented by a processor 702 and a memory 704, and the RF chip 204 is implemented by a processor 702, a memory 704, and a transceiver 706, as described above. Figure 7 In addition to the on-chip memory (also referred to as "internal memory", such as registers, buffers, or caches) on each chip 202, 204, or 206, the device 200 may also include an external memory 208 (e.g., system memory or main memory) that can be shared by each chip 202, 204, or 206 via a system / main bus. Figure 2 204 can be integrated into one SoC; in another example, the baseband chip 202 and the host chip 206 can be integrated into one SoC; in yet another example, the baseband chip 202, the RF chip 204 and the host chip 206 can be integrated into one SoC, as described above.

[0042] In the uplink, the host chip 206 can generate raw data and send it to the baseband chip 202 for encoding, modulation and mapping. The baseband chip 202 can also access the raw data generated by the host chip 206 and stored in the external memory 208, for example, using direct memory access (DMA). The baseband chip 202 can first encode (e.g., by source coding and / or channel coding) the raw data, and then modulate the encoded data using any suitable modulation technology (e.g., multi-phase pre-shared key (MPSK) modulation or orthogonal amplitude modulation (QAM)). The baseband chip 202 can perform any other functions (e.g., symbol or layer mapping) to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, the baseband chip 202 can send the modulated signal to the RF chip 204. The RF chip 204 can convert the modulated signal in digital form into an analog signal (i.e., RF signal) through a transmitter, and perform any suitable front-end RF functions, such as filtering, up-conversion, or sampling rate conversion. The antenna 210 (eg, an antenna array) may transmit RF signals provided by a transmitter of the RF chip 204 .

[0043] In the downlink, the antenna 210 can receive the RF signal and pass the RF signal to the receiver (Rx) of the RF chip 204. The RF chip 204 can perform any suitable front-end RF functions (e.g., filtering, down-conversion, or sampling rate conversion) and convert the RF signal into a low-frequency digital signal (baseband signal) that can be processed by the baseband chip 202. In the downlink, the baseband chip 202 can demodulate and decode the baseband signal to extract the original data that can be processed by the host chip 206. The baseband chip 202 can perform additional functions, such as error checking, demapping, channel estimation, descrambling, etc. The original data provided by the baseband chip 202 can be sent directly to the host chip 206 or stored in the external memory 208.

[0044] In some embodiments, one or more components of the device 200 (e.g., baseband chip 202, RF chip 204, host chip 206, external memory 208, etc.) can use the same set of layer 2 circuits on the baseband chip (sometimes controlled by the MCU) to process layer 2 packets for the first RAT and the second RAT, as described in detail below. Therefore, compared with known solutions that use software modules implemented on a general-purpose processor in conjunction with system memory to process layer 2 data, data speed can be increased due to hardware acceleration, chip cost can be reduced by reducing memory usage, and power consumption can also be reduced.

[0045] Figure 3A block diagram of an exemplary baseband chip 300 according to some embodiments of the present disclosure is shown. The baseband chip 300 may belong to a node (UE 102 or access node 104) that implements a protocol stack defined in a standard (e.g., a protocol stack defined by 3GPP or IEEE 802.11), which includes a group of network protocol layers that work together to provide networking capabilities.

[0046] In some implementations, the baseband chip 300 can be dynamically programmed to use the same set of layer 2 circuits 312 and / or layer 2 engines 316 to perform operations associated with layer 2 data processing for the first RAT and the second RAT. In some implementations, multiple MCUs (uCs) 306 can program the layer 2 circuits 312 and / or layer 2 engines 316 to perform layer 2 data processing for the first RAT data path (e.g., 5G NR) and the second RAT data path (e.g., Wi-Fi 5, Wi-Fi 6, Wi-Fi 7, Wi-Fi 8, and later products). In addition, the baseband chip 300 can support concurrent 5G+Wi-Fi mode, or a 5G / Wi-Fi selective mode with a dynamic command interface and stateless processing. In some other implementations, the baseband chip 300 can be configured to operate as an independent 5G-only mode or Wi-Fi-only mode.

[0047] refer to Figure 3 , the baseband chip 300 may include a first PHY subsystem 302a associated with a first RAT (e.g., 5G NR), a second PHY subsystem 302b associated with a second RAT (e.g., Wi-Fi), a layer 2 subsystem 304, a control plane circuit 326, a main processor 328, a DDR memory 330, one or more layer 2 quality of service (QoS) queues 336, one or more layer 3 and layer 4 circuits 332, and an application processor (AP) host 334, etc. The layer 2 subsystem 304 may include multiple MCUs (e.g., uCs), multiple layer 2 circuits 312, and multiple layer 2 engines 316, etc.

[0048] Multiple MCUs 306 (hereinafter referred to as "MCUs" or "uCs") may include an MCU cluster, a UL scheduler, and a DL director, etc. More specifically, the MCU 306 may include a UL uC cluster 308a and a DL uC cluster 308b. The MCU 306 may include grouped functions (e.g., UL functions and DL functions), which may configure a layer 2 circuit 312, and a UL scheduler (see FIG. 4A to FIG. 4C ), DL guide (see Figures 5A to 5C) and routing tasks. These UL and DL functions can control the layer 2 circuit 312 and one or more layer 2 engines 316 through the command / status queues 310a and 310b, respectively. Each command can contain a command descriptor with specific parameters or instructions for the data packet. When the layer 2 circuit 312 completes processing of the data packet, the layer 2 circuit can output the status of the data packet in the command / status queues 310a and 310b. The MCU 306 can process the status descriptor and decide how to proceed to the next pipeline stage of the layer 2 processing of the data packet. The layer 2 pipeline stages in 5G NR include, for example, the MAC layer stage, the RLC layer stage, and the PDCP layer stage. The layer 2 pipeline stages in Wi-Fi include, for example, the AMPDU layer stage, the BA layer stage, and the MPDU layer stage. In response to determining how to proceed to the next pipeline stage, the MCU 306 can send a signal to one or more of, for example, the UL command / status queue 310a, the DL command / status queue 310b, the one or more layer 2 circuits 312, and / or the one or more layer 2 engines 316.

[0049] The MAC_AMPDU circuit 314a may perform layer 2 data processing operations associated with lower layers in the layer 2 protocol stack for both the first RAT and the second RAT. More specifically, the MAC_AMPDU circuit 314a may perform MAC layer processing of the layer 2 protocol, which may include multiplexing / demultiplexing, header extraction, or generation of MAC layer packet data units (PDUs) for both the first RAT and the second RAT. In addition, the MAC_AMPDU circuit 314a may interface with the PHY subsystems 302a, 302b to send / receive data packets (e.g., data byte streams). In addition, the MAC_AMPDU circuit 314a may coordinate operations associated with the first set of layer 2 engines 316.

[0050] The RLC_BA circuit 314b may perform layer 2 data processing operations associated with the middle layer of the layer 2 protocol stack for both the first RAT and the second RAT. More specifically, the RLC_BA circuit 314b may be responsible for RLC or BA layer processing of layer 2 protocols for 5G NR and Wi-Fi, respectively. For example, the RLC_BA circuit 314b may perform functions to ensure reliable data transmission (e.g., ARQ), window checks, sliding window moves, replication, and window out-of-window discards using bitmaps to track packet transmissions. Additionally and / or alternatively, the RLC_BA circuit 314b may also perform segmentation and reassembly of segmented radio frames, subframes, data packets, and the like. In certain implementations, the RLC_BA circuit 314b may perform aggregation and deaggregation of radio frames, subframes, PDUs, service data units (SDUs), data packets, and the like. That is, the RLC_BA circuit 314b may coordinate operations associated with the second set of layer 2 engines 316.

[0051] The PDCP_MDPU circuit 314c may perform layer 2 data processing operations associated with upper layers of a layer 2 protocol stack associated with both the first RAT and the second RAT. More specifically, the PDCP_MPDU circuit 314c may perform PDU packet processing on an extracted user data packet, which may include an IP layer 3 data packet. The functionality of the PDCP_MPDU circuit 314b may include encryption / decryption, integrity / de-integrity, data compression, robust header compression (ROHC), and reordering operations prior to delivery to layer 3 for DL ​​cases or to the RLC_BA circuit 314b for UL cases. Depending on whether the operation is associated with the first RAT or the second RAT, and the mode (e.g., 5G standalone mode, Wi-Fi standalone mode, concurrent 5G and Wi-Fi multi-mode, dynamic 5G or Wi-Fi mode), the PDCP_MPDU circuit 314c may perform secondary aggregation / de-aggregation of service data units (SDUs), where the SDUs may be aggregated to obtain optimal high throughput. That is, the PDCP_MDPU 314 c may coordinate operations associated with the third set of layer 2 engines 316 .

[0052] The layer 2 engine 316 may include multiple hardware engines that may be dynamically triggered by the layer 2 circuits 314a, 314b, 314c or the MCU 306 in any order, depending on the mode of operation. More specifically, the layer 2 engine 316 may include a multiplexing engine 318a, a demultiplexing engine 318b, a header generation engine 318c, a header extraction engine 318d, a segmentation engine 320a, a reassembly 320b, a window operation engine 320c, a decryption / de-integrity engine 322a, an encryption / integrity engine 322b, a ROHC engine 322c, a reordering engine 322d, a data compression engine 322e, an aggregation engine 322f, and a de-aggregation engine 322g. Each of the multiple hardware engines may be a stateless, modular layer 2 hardware unit block. Each of the layer 2 engines 316 may be a packet processing engine that performs specific functions common to the first RAT and the second RAT. By commanding each of the plurality of layer 2 engines 316 to perform their specific per-packet operations in the packet processing pipeline, the UL uC cluster 308a and / or the DL uC cluster 308b can chain together an entire layer 2 packet processing pipeline. Additional details describing each of the plurality of layer 2 engines 316 are set forth below.

[0053] The header extraction engine 318d can extract the header of one or more data packets from the PHY subsystem 302a or 302b. More specifically, the header extraction engine 318d can extract the header based on a lookup table with an index that includes the RAT type (e.g., 5G NR, Wi-Fi, LTE, 3G, Bluetooth, etc.), the identity of the logical channel, the radio bearer identification, the MAC subframe type (to name a few), etc. Using the extracted header and the lookup table, the header extraction engine 318d can identify a specific decoding template associated with the received data packet, etc. After extracting the header, the header extraction engine 318d can update the UL command / status queue 310a to indicate that the header was extracted.

[0054] The multiplexing engine 318a may multiplex together multiple PDUs from different locations indicated by the input data buffer pointer and trigger a DMA engine (not shown) to move the data packets to the inline buffer 324. In some implementations, the multiplexing engine 318a may interface with a PHY layer (e.g., PHY subsystem 302a or 302b) to transmit packet data.

[0055] The demultiplexing engine 318b demultiplexes the incoming PHY code blocks, data packets, or data frames. In addition, the demultiplexing engine 318b can perform inline buffer management to reorder the incoming PHY code blocks and stream the reordered PHY code blocks out for processing by the next pipeline stage, or store the reordered PHY code blocks in external memory.

[0056] The header generation engine 318c may accept input index parameters for lookup tables and header fields. Additionally, the header generation engine 318c may generate a header for inclusion in the UL data packet.

[0057] The segmentation engine 320a can segment the input data packet into one or more segment packets according to the grant size of the transmission data packet. In addition, the segmentation engine 320a can output the header fields of all segments after segmentation.

[0058] The reassembly engine 320b may check the corresponding packet sequence numbers and offsets of the incoming input fragmented packets and reassemble the original packets. In some implementations, the reassembly engine 320b may look up the format of the fragmented packet header, for example, using input index parameters (e.g., logical channel identifier, mode, and RAT type) to look up the format of the fragmented packet header.

[0059] The window operation engine 320c can perform sliding window ARQ procedures to ensure reliable data transmission. The sliding window ARQ procedures include duplicate packet detection and discarding, out-of-window detection and discarding, bitmap update when a packet is received, generating status reports and ARQ acknowledgments that can be sent to communication nodes (e.g., Wi-Fi nodes, base stations, gNBs, eNBs, IoT devices, etc.), processing status reports and ARQ acknowledgments received from communication nodes, performing window sliding operations by updating upper and lower limit variables of the sliding window, and managing abort timers, which are just a few examples.

[0060] The decryption / de-integrity engine 322a can decrypt incoming packets (e.g., incoming byte streams) based on the input key, sequence number, and any other decryption inputs. Additionally and / or alternatively, the decryption / de-integrity engine 322a can perform integrity checks and output the status of the decryption / de-integrity procedure to, for example, the DL command / status queue 310b.

[0061] The encryption / integrity engine 322b can encrypt incoming packets (e.g., incoming byte streams) based on the input key, sequence number, and any other encryption inputs. Additionally and / or alternatively, the encryption / integrity engine 322b can perform integrity checks and output the status of the encryption / integrity operation and integrity bits to, for example, the UL command / status queue 310a.

[0062] The ROHC engine 322c may receive a layer 3 data packet as input. In addition, the ROHC engine 322c may perform IP header compression associated with ROHC operations, such as defined by the ROHC standard. The IP header parameters on which the ROHC engine 322c may perform IP header compression include one or more of a context identifier (ID) and / or a packet sequence ID (e.g., a packet count value in a 5G NR PDCP layer of a layer 2 data protocol stack), etc. Additionally and / or alternatively, the output compressed header may be written to a location buffer specified by the MCU 306.

[0063] The reordering engine 322d may reorder the DL packets that have been received from the communication node and checked in the bitmap so that the DL packets are delivered to layer 3 in sequence.

[0064] The data compression engine 322e can perform data compression on the incoming data packets (e.g., the incoming byte stream). In addition, the data compression engine 322e can output compressed data packets (e.g., compressed bytes). To optimize high throughput performance, the incoming data packets can be routed to the data compression engine 322e from one or more other engines in the layer 2 engine 316 (e.g., the encryption / integrity engine 322b). Additionally and / or alternatively, the data compression engine 322e can route the compressed data to one or more other engines in the layer 2 engine 316 (e.g., the encryption / integrity engine 322b).

[0065] The aggregation engine 322f may aggregate the PDUs based on operations associated with the first RAT and the second RAT. In addition, the aggregation engine 322f may aggregate the PDUs based at least in part on the input grant size. Aggregation of PDUs may occur more than once in the packet processing pipeline chain. For example, when performing operations associated with Wi-Fi, two different levels of aggregation may occur for MAC SDUs (MSDUs) and MPDUs.

[0066] The de-aggregation engine 322g may perform de-aggregation of the aggregated PDUs to extract each PDU in the aggregation. The extracted PDUs may be output one at a time to the DL command / status queue 310b.

[0067] FIG. 4A to FIG. 4C A data flow 400 is shown that may be used to perform UL layer 2 data processing for a first RAT and a second RAT in accordance with certain aspects of the present disclosure. FIG. 4A to FIG. 4C The data flow 400 shown in FIG. 4 may be generated by, for example, Figure 3 The baseband chip 300 performs the FIG. 4A to FIG. 4C , operations 409-455 may be associated with UL layer 2 data processing for 5G NR (e.g., a first RAT), and operations 457-475 may be associated with UL layer 2 data processing for Wi-Fi (e.g., a second RAT).

[0068] refer to Figure 4A, the control plane circuit 326 may perform (at 401) a RAT system selection process. That is, the control plane circuit 326 may determine whether to perform UL layer 2 data processing for 5G NR or Wi-Fi communication. The control plane circuit 326 may send (at 403) layer 2 configuration information (L2_Config) indicated to the configuration unit 340 of the UL uC cluster 308a. The UL uC cluster 308a may send (at 405a, 405b, 405c, respectively) a layer 2 configuration command (L2_ConfigCmd) to each of the PDCP_MPDU circuit 314c, the RLC_BA 314b, and the MAC_AMPDU 314a. L2_ConfigCmd may program the MAC_AMPDU circuit 314a, the RLC_BA circuit 314b, and the PDCP_MPDU circuit 314c to perform operations associated with layer 2 data processing for a first RAT (e.g., 5G NR) or a second RAT (e.g., Wi-Fi).

[0069] The layer 3 circuitry 332 may send (at 407) the layer 3 IP datagram to one or more layer 2 QoS queues 336, which may be located at or remote from the DDR memory 330. The one or more layer 2 QoS queues 336 may maintain and / or store incoming and / or outgoing datagram descriptors between layer 2 applications and layer 3 applications. The layer 3 IP datagram may undergo layer 2 data processing before being sent to the PHY subsystems 302a, 302b.

[0070] 5G UL Data Processing

[0071] When the L2_Config sent (at 403) indicates that layer 2 data processing is associated with 5G NR, the data flow 400 is from Figure 4A Operation 407 in moves to operation 409. The pipeline stages associated with 5G UL Layer 2 data processing include a PDCP stage, an RLC stage, and a MAC stage, as described below.

[0072] refer to Figure 4A, the scheduler 342 of the UL uC cluster 308a can receive (at 409) an UL resource grant from the PHY subsystem 302a. After the UL grant arrives from the base station via the downlink control information (DCI) in the physical downlink control channel (PDCCH), the UL uC cluster 308a can process the grant information and perform logical channel prioritization (LCP) priority scheduling for UL packets from one or more layer 2 QoS queues 336. Grant resources (e.g., bytes) can be allocated to each logical channel based on the LCP algorithm until the UL resource grant is exhausted. The UL scheduler 342 can ensure that low-latency data packets are given the highest priority to proceed to the next pipeline stage first. The UL resource grant can also provide a time when the UL packet can be sent to the PHY subsystem 302a for encoding and air transmission. After establishing a connection with the base station, all necessary bearers, logical channels, ARQ mode configurations, and carrier channel parameters may be configured and stored in a lookup table accessible by each of the PDCP_MPDU circuit 314c, RLC_BA 314b, and MAC_AMPDU 314a.

[0073] After dequeuing the data packet from one or more Layer 2 QoS queues 336, the UL uC cluster 308a may prepare the data packet to be sent to the Layer 2 circuit 312 and / or the Layer 2 engine 316 for 5G NR Layer 2 data processing. For example, the UL uC cluster 308a may determine whether PDCP processing should be performed on the data packet. If so, the UL uC cluster may enqueue a PDCP command (PDCP_Cmd) descriptor, which may be sent (at 417) to the PDCP_MPDU circuit 314c. The PDCP_Cmd descriptor may include, among other things, a data packet sequence number, encryption / integrity algorithms and parameters, and ROHC or data compression parameters. The PDCP_MPDU circuit 314c may process the PDCP_Cmd and instruct the ROHC engine 322c, the data compression engine 322e, and / or the encryption / integrity engine 322b to perform their respective operations on the data packet. Once the task is completed, the PDCP_MPDU circuit 314c may send (at 419) a PDCP status complete (PDCP_Status) to the UL command / status queue 310a and / or the scheduler 342 in the UL uC cluster 308a for further processing. The PDCP_MPDU circuit 314c may send the PDCP processed packet to the RLC_BA circuit 314b.

[0074] The UL uC cluster 308a may determine parameters and functions associated with the next pipeline stage (e.g., the RLC stage). In certain implementations, for example, in an unacknowledged (UACK) mode (UM), the UL uC cluster 308a may determine that segmentation may be relevant. In certain other implementations, for example, in an acknowledged (ACK) mode (AM), the UL uC cluster 308a may determine that one or more of sliding window operations, segmentation, and / or aggregation may be relevant. A status report using a bitmap may also be determined to be sent to the base station. The UL uC cluster 308a may send (at 421) an RLC command descriptor (RLC_Cmd) to the RLC_BA circuit 314b (e.g., via the UL command / status queue 310a), wherein the RLC_Cmd may trigger a sequence of operations performed by, for example, one or more of the window operation engine 320c, the aggregation engine 322f, and / or the segmentation engine 320a. Reference Figure 4B After completing the RLC operation, the RLC_BA engine 314b may send (at 423) an RLC_Status signal to the UL command / status queue 310a and / or the scheduler 342 in the UL uC cluster 308a. The RLC processed data packet may be sent to the MAC_AMPDU circuit 314a.

[0075] Finally, at the last pipeline stage, the UL uC cluster 308a enqueues the RLC command descriptor (MAC_Cmd) to the UL command / status queue 310a. The MAC_AMPDU circuit 314a may receive and / or access (at 425) the MAC_Cmd from the UL command / status queue 310a. The MAC_Cmd may command the MAC_AMPDU circuit 314a to instruct, for example, the multiplexing engine 318a and / or the header generation engine 318c to perform MAC layer operations on the data packet (e.g., MAC PDU). The header parameters may be included in the MAC_Cmd, or the MAC_AMPDU circuit 314a may access a lookup table that indicates the header parameters based on a given logical channel and radio bearer identity. After generating the header and multiplexing the packet byte stream, the MAC_AMPDU circuit 314a may send (at 427) a MAC_Status to the UL uC cluster 308a. Additionally, the MAC_AMPDU 314a may send (at 429 ) a layer 2 data packet (eg, a data byte stream) to the PHY subsystem 302a via an inline buffer 324 .

[0076] Wi-Fi UL data processing

[0077] When the L2_Config sent (at 403) indicates that layer 2 data processing is associated with Wi-Fi, data flow 400 is Figure 4A Operation 407 in Move to Figure 4B Operation 455 in .

[0078] refer to Figure 4B , upon receiving (at 455) a UL resource grant from a Wi-Fi node, the UL uC cluster 308a may perform (at 457) transmission priority scheduling for UL packets from one or more layer 2 QoS queues 336 until the grant is exhausted. The UL scheduler 342 ensures that low latency packets are given the highest priority to proceed to the next pipeline stage first. The UL resource grant may also provide a time when the UL layer 2 packet should be sent to the PHY subsystem 302b for encoding and transmission over the air. The layer 3 circuit 332 may send (at 459) an IP packet to the DDR memory 330. The IP packet (hereinafter referred to as a "packet") may be sent (at 461) to one or more layer 2 QoS queues 336.

[0079] After dequeuing the data packet from one or more layer 2 QoS queues 336, the UL uC cluster 308a may prepare the data packet to be sent to the layer 2 circuit 312 and / or the layer 2 engine 316 for Wi-Fi layer 2 data processing. For example, the UL uC cluster 308a may determine whether encryption / integrity operations and / or data compression should be performed on the data packet. Additionally and / or optionally, the UL uC cluster 308a may determine whether to aggregate the data packet at the AMSDU layer. The UL uC cluster 308a may generate an MSDU command (MPDU_Cmd) descriptor that is sent (at 463) to the PDCP_MDPU circuit 314c. The MPDU_Cmd descriptor may include a data packet sequence number, encryption / integrity algorithms and parameters, ROHC parameters, data compression parameters, etc. Optionally, when the UL uC cluster 308a determines that the aggregation of the data packet is at the MPDU level, the MPDU_Cmd may include aggregation parameters. The PDCP_MPDU circuit 314c may process the MPDU_Cmd and instruct one or more of, for example, the ROHC engine 322c, the data compression engine 322e, the encryption / integrity engine 322b, and / or the aggregation engine 322f to perform their respective operations on the data packet. Once the task is completed, the PDCP_MPDU circuit 314c may send (at 465) an MPDU status complete (MPDU_Status) to the UL command / status queue 310a and / or the scheduler 342 in the UL uC cluster 308a. The PDCP_MPDU circuit 314c may send the MDPU processed data packet to the RLC_BA circuit 314b.

[0080] The UL uC cluster 308a may determine whether to perform BA on the data packet at the BA level. After determining to perform BA, the ULuC cluster 308a may generate a BA command descriptor (BA_Cmd) to the RLC_BA circuit 314b. The BA_Cmd may include a data packet sequence number and / or window operation parameters, etc. The RLC_BA circuit 314b may process the BA_Cmd and instruct the window operation engine 320c, etc. to perform their respective operations on the data packet. Additionally and / or alternatively, the RLC_BA circuit 314b may update and / or generate a bitmap state of the data packet to be sent to the Wi-Fi node. In either case, refer to Figure 4C , the RLC_BA circuit 314b may send (at 469) a BA status complete (BA_Status) to the UL command / status queue 310a and / or the scheduler 342 in the UL uC cluster 308a.

[0081] The UL uC cluster 308a may determine whether to perform segmentation on the data packet at the AMPDU level. The UL uC cluster 308a may enqueue an AMPDU command descriptor (AMPDU_Cmd) into the UL command / status queue 310a. The AMPDU_Cmd may include header generation parameters, aggregation parameters, segmentation parameters, and / or multiplexing parameters, among others. The MAC_AMPDU circuit 314a may access and / or receive (at 471) the AMPDU_Cmd. The MAC_AMPDU circuit 314a may process the AMPDU_Cmd and instruct the header generation engine 318c, the aggregation engine 322f, the segmentation engine 320a, and the multiplexing engine 318a to perform their respective functions on the data packet. The MAC_AMPDU circuit 314a may send (at 473) an AMPDU status complete (AMPDU_Status) to the UL command / status queue 310a and / or the scheduler 342 in the UL uC cluster 308a. The layer 2 data packet may be sent (at 475) to the PHY subsystem 302b.

[0082] FIG. 5A to FIG. 5C A data flow 500 is shown that may be used to perform DL layer 2 data processing for a first RAT and a second RAT in accordance with certain aspects of the present disclosure. FIG. 5A to FIG. 5C The data flow 500 shown in FIG. 5 may be generated by, for example, Figure 3 The baseband chip 300 performs the FIG. 5A to FIG. 5C , operations 507-527 may be associated with DL layer 2 data processing for 5G NR (e.g., a first RAT), and operations 529-549 may be associated with DL layer 2 data processing for Wi-Fi (e.g., a second RAT).

[0083] refer to Figure 5A , the control plane circuit 326 may perform (at 501) a RAT system selection process. That is, the control plane circuit 326 may determine whether to perform DL layer 2 data processing for 5G NR or Wi-Fi communication. The control plane circuit 326 may send (at 503) layer 2 configuration information (L2_Config) to the configuration unit 340 of the DL uC cluster 308b, indicating whether to perform DL layer 2 data processing operations associated with 5G NR or Wi-Fi. The DL uC cluster 308b may send (at 505a, 505b, 505c, respectively) a layer 2 configuration command (L2_ConfigCmd) to each of the PDCP_MPDU circuit 314c, the RLC_BA circuit 314b, and the MAC_AMPDU circuit 314a.

[0084] 5G DL data processing

[0085] The DL uC cluster 308b may generate a MAC command descriptor (MAC_Cmd) that is sent (at 507) to the MAC_AMPDU circuit 314a. The MAC_Cmd may include relevant carrier and channel information, etc., which may enable the header extraction engine 318d to look up the packet format for decoding. A packet (e.g., one or more code blocks (CBs) or data byte streams) may be sent (at 509) from the PHY subsystem 302a to the header extraction engine 318d via the inline buffer 324. The header extraction engine 318d may extract packet descriptors, such as header parameters, logical channel IDs, lookup table-specific decoding formats for subsequent layers (e.g., RLC and PDCP). The packet may be sent from the header extraction engine 318d to the demultiplexing engine 318b, which demultiplexes one or more packets. The demultiplexing engine 318b may send (at 511) the packet descriptor, such as in an MDPU control packet, to the MAC_AMPDU 314a. The MAC_AMPDU circuit 314a may send (at 513) a MAC status complete (MAC_Status) to the DL command / status queue 310b and / or the director 344 of the DLuC cluster 308b. The PHY subsystem 302a may send one or more packets to the inline buffer 324, which may send (at 515) one or more packets to the MAC_AMPDU circuit 314a.

[0086] The DL uC cluster 308b may send (at 517) an RLC command descriptor (RLC_Cmd) to the RLC_BA circuit 314b. The RLC_Cmd may include, among other things, a packet sequence number, window operation parameters, deaggregation parameters, and reassembly parameters. The RLC_BA circuit 314b may instruct one or more of the deaggregation engine 322g, the reassembly engine 320b, and / or the window operation engine 320c, etc., to perform their respective operations on the packet. Upon completion, the RLC_BA circuit 314b may send (at 519) an RLC status complete (RLC_Status) to the DL command / status queue 310b and / or the director 344 of the DL uC cluster 308b. The RLC_BA circuit 314b may send one or more packets to the PDCP_MPDU circuit 314c.

[0087] refer to Figure 5B , the DL uC cluster 308b may enqueue a PDCP command descriptor (PDCP_Cmd) in the DL command / status queue 310b. The PDCP_Cmd may include a packet sequence number, a decryption parameter, a de-integrity parameter, a ROHC parameter, a window operation parameter, and / or a reordering parameter, etc. The PDCP_MPDU circuit 314c may access and / or receive the PDCP_Cmd from the DL command / status queue 310b. The PDCP_MPDU circuit 314c may instruct one or more of the decryption / de-integrity engine 322a, the ROHC engine 322c, the window operation engine 320c, and / or the reordering engine 322d, etc. to perform their respective operations. Upon completion, the PDCP_MPDU circuit 314c may send (at 523) a PDCP status complete (PDCP_Status) to the DL command / status queue 310b and / or the director 344 of the DL uC cluster 308b.

[0088] The DL uC cluster 308b may send the packet descriptor to one or more layer 2 QoS queues 336 for retrieval by the layer 3 circuitry 332 at 525. The packet payload may be sent from the internal buffers at the L2 circuitry 312 and the L2 engine 316 to the DDR memory 330 at 527. The layer 3 circuitry 332 may retrieve the packet payload from the DDR memory 330.

[0089] Wi-Fi DL data processing

[0090] The DL uC cluster 308b may generate an AMPDU command descriptor (AMPDU_Cmd) that is sent (at 529) to the MAC_AMPDU circuit 314a. The AMPDU_Cmd may include relevant carrier and channel information, etc., which may enable the header extraction engine 318d to look up the AMPDU frame format and / or AMPDU subframe format for decoding. A data packet (e.g., one or more code blocks (CBs) or data byte streams) may be sent (at 531) from the PHY subsystem 302b to the header extraction engine 318d via the inline buffer 324. The header extraction engine 318d may extract the packet descriptor, such as header parameters, logical channel IDs, lookup table specific decoding formats for subsequent layers (e.g., BA and MPDU), and continue the process for AMPDU, MPDU, AMSDU, and MSDU. The data packet may be sent from the header extraction engine 318d to the demultiplexing engine 318b, which demultiplexes one or more data packets. The demultiplexing engine 318b may send (at 533) a packet descriptor, such as in an MDPU control packet, to the MAC_AMPDU 314a. The MAC_AMPDU circuit 314a may send (at 535) an AMPDU status complete (AMPDU_Status) to the DL command / status queue 310b and / or the director 344 of the DL uC cluster 308b. The PHY subsystem 302a may send one or more packets to the inline buffer 324, which may send (at 537) one or more packets to the MAC_AMPDU circuit 314a.

[0091] The DL uC cluster 308b may send (at 539) a BA command descriptor (BA_Cmd) to the RLC_BA circuit 314b. The BA_Cmd may include, among other things, a packet sequence number and window operation parameters. The RLC_BA circuit 314b may instruct the window operation engine 320c, etc., to perform its corresponding operation on the packet. Figure 5C , the RLC_BA circuit 314b may send (at 519) a BA status complete (BA_Status) to the DL command / status queue 310b and / or the director 344 of the DL uC cluster 308b. The RLC_BA circuit 314b may send one or more packets to the PDCP_MPDU circuit 314c.

[0092] The DL uC cluster 308b may enqueue an MDPU command descriptor (MPDU_Cmd) in the DL command / status queue 310b. The MPDU_Cmd may include a packet sequence number, decryption parameters, de-integrity parameters, de-aggregation parameters, and / or re-ordering parameters, etc. The PDCP_MPDU circuit 314c may access and / or receive the MPDU_Cmd from the DL command / status queue 310b. The PDCP_MPDU circuit 314c may instruct one or more of the decryption / de-integrity engine 322a, the de-aggregation engine 322g, the re-assembly engine 320b, and / or the re-ordering engine 322d, etc. to perform their respective operations. Upon completion, the PDCP_MPDU circuit 314c may send (at 545) an MPDU status complete (MPDU_Status) to the DL command / status queue 310b and / or the director 344 of the DL uC cluster 308b.

[0093] The DL uC cluster 308b may send the packet descriptor to one or more layer 2 QoS queues 336 for retrieval by the layer 3 circuitry 332 at 547. The packet payload may be sent from the internal buffers at the L2 circuitry 312 and the L2 engine 316 to the DDR memory 330 at 549. The layer 3 circuitry 332 may retrieve the packet payload from the DDR memory 330.

[0094] Figure 6 600 for layer 2 data processing according to some embodiments of the present disclosure. Examples of devices that can perform the operations of method 600 include, for example, a Figure 3 The baseband chip 300 depicted in the method 600 or any other suitable device disclosed herein. It is understood that the operations shown in the method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 6 The different orders are shown.

[0095] refer to Figure 6 At 602, the baseband chip may identify whether the data packet is associated with the first RAT or the second RAT. Figure 4A , the control plane circuit 326 may perform (at 401) a RAT system selection process. That is, the control plane circuit 326 may determine whether to perform UL layer 2 data processing for 5G NR communication or for Wi-Fi communication.

[0096] At 604, the baseband chip may program a plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT in response to determining that the data packet is associated with the first RAT. Figure 4A, the UL uC cluster 308a may send (at 405a, 405b, 405c, respectively) a layer 2 configuration command (L2_ConfigCmd) to each of the PDCP_MPDU circuit 314c, the RLC_BA circuit 314b, and the MAC_AMPDU 314a. The L2_ConfigCmd may program the MAC_AMPDU circuit 314a, the RLC_BA circuit 314b, and the PDCP_MPDU circuit 314c to perform operations associated with layer 2 data processing for the first RAT (e.g., 5G NR).

[0097] At 606, the baseband chip may program the plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT in response to determining that the data packet is associated with the second RAT. Figure 4A , the UL uC cluster 308a may send (at 405a, 405b, 405c, respectively) a layer 2 configuration command (L2_ConfigCmd) to each of the PDCP_MPDU circuit 314c, the RLC_BA circuit 314b, and the MAC_AMPDU 314a. The L2_ConfigCmd may program the MAC_AMPDU circuit 314a, the RLC_BA circuit 314b, and the PDCP_MPDU circuit 314c to perform operations associated with layer 2 data processing for the second RAT (e.g., Wi-Fi).

[0098] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media include computer storage media. Storage media may be a computer program that can be accessed by a computing device (e.g., Figure 7 Any available medium accessed by the node 700 in . As an example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage device, HDD (e.g., disk storage device or other magnetic storage device), flash drive, SSD or any other medium, which can be used to carry or store the desired program code in the form of instructions or data structures accessible by a processing system (e.g., a mobile device or a computer). Disks and discs as used herein include CDs, laser discs, optical discs, DVDs and floppy disks, wherein the disks usually reproduce data magnetically, while the discs reproduce data optically using lasers. The above combination should also be included in the scope of computer-readable media.

[0099] According to one aspect of the present disclosure, a baseband chip may include a plurality of layer 2 circuits, each layer 2 circuit being configured to perform layer 2 data processing operations associated with a first RAT and a second RAT. In some aspects, the first RAT and the second RAT may be different. The baseband chip may also include an MCU configured to program the plurality of layer 2 circuits to perform layer 2 data processing operations associated with the first RAT or the second RAT.

[0100] In certain aspects, the baseband chip may also include a buffer configured to receive a layer 1 transport block from a first layer 1 circuit associated with the first RAT or from a second layer 1 circuit associated with the second RAT.

[0101] In certain other aspects, in response to the buffer receiving the layer 1 transport block, the MCU may be configured to identify whether the layer 1 transport block was received from a first layer 1 circuit associated with the first RAT or from a second layer 1 circuit associated with the second RAT.

[0102] In certain other aspects, in response to identifying that the layer 1 transport block was received from the first layer 1 circuit, the MCU may be further configured to program the plurality of layer 2 circuits to perform layer 2 data processing operations associated with the first RAT on the layer 1 transport block.

[0103] In certain other aspects, in response to identifying that the layer 1 transport block was received from a second layer 1 circuit, the MCU may be further configured to program the plurality of layer 2 circuits to perform layer 2 data processing operations associated with the second RAT on the layer 1 transport block.

[0104] In certain other aspects, the plurality of layer 2 circuits may include a first layer 2 circuit configured to control MAC operations associated with the first RAT and AMPDU operations associated with the second RAT.

[0105] In certain other aspects, the plurality of layer 2 circuits may include a second layer 2 circuit configured to perform RLC operations associated with the first RAT and BA operations associated with the second RAT.

[0106] In certain other aspects, the plurality of layer 2 circuits may include a third layer 2 circuit configured to perform PDCP operations associated with the first RAT and MPDU operations associated with the second RAT.

[0107] In certain other aspects, the first layer 2 circuit may be configured to control MAC operations and AMPDU operations performed by a first set of layer 2 engines associated with the first layer 2 circuit.

[0108] In certain other aspects, the second layer 2 circuit may be configured to control RLC operations and BA operations performed by a second set of layer 2 engines associated with the second layer 2 circuit.

[0109] In certain other aspects, the third layer 2 circuit may be configured to control PDCP operations and MPDU operations performed by a third set of layer 2 engines associated with the third layer 2 circuit.

[0110] In certain other aspects, the first set of layer 2 engines may include one or more of a multiplexing engine, a demultiplexing engine, a header extraction engine, or a header generation engine.

[0111] In certain other aspects, the second set of layer 2 engines may include one or more of a segmentation engine, a reassembly engine, or a window operation engine.

[0112] In certain other aspects, the third set of layer 2 engines may include one or more of an encryption / integrity engine, a decryption / de-integrity engine, a data compression engine, a ROHC engine, a reorder operation engine, an aggregation engine, or a de-aggregation engine.

[0113] In certain other aspects, the baseband chip may further include a memory operably coupled to the MCU and the plurality of layer 2 circuits and configured to store the plurality of groups of commands into a plurality of command queues for retrieval by at least one of the plurality of layer 2 circuits.

[0114] In certain other aspects, the memory may be further configured to receive multiple sets of result status from at least one of the layer 2 circuits and store the multiple sets of result status in the multiple state queues, respectively.

[0115] In certain other aspects, the MCU may be further configured to retrieve multiple sets of result states from the memory.The MCU may be further configured to generate each set of commands for controlling a respective one of the layer 2 circuits based on the corresponding set of result states.

[0116] In some aspects, the corresponding set of result states may be from another layer 2 circuit that is at a lower layer in the layer 2 protocol stack than the corresponding one of the layer 2 circuits.

[0117] According to another aspect of the present disclosure, a baseband chip includes a first layer 2 circuit configured to control a MAC operation associated with a first RAT and an AMPDU operation associated with a second RAT. The baseband chip may also include a second layer 2 circuit configured to perform an RLC operation associated with the first RAT and a BA operation associated with the second RAT. The baseband chip may also include a third layer 2 circuit configured to perform a PDCP operation associated with the first RAT and an MPDU operation associated with the second RAT.

[0118] In certain aspects, the first layer 2 circuit may be configured to control MAC operations and AMPDU operations by controlling a first set of layer 2 engines associated with the first layer 2 circuit.

[0119] In certain other aspects, the second layer 2 circuit may be configured to control RLC operations and BA operations by controlling a second set of layer 2 engines associated with the second layer 2 circuit.

[0120] In certain other aspects, the third layer 2 circuit may be configured to control PDCP operations and MPDU operations by controlling a third set of layer 2 engines associated with the third layer 2 circuit.

[0121] In certain other aspects, the first set of layer 2 engines may include one or more of a multiplexing engine, a demultiplexing engine, a header extraction engine, or a header generation engine.

[0122] In certain other aspects, the second set of layer 2 engines may include one or more of a segmentation engine, a reassembly engine, or a window operation engine.

[0123] In certain other aspects, the third set of layer 2 engines may include one or more of an encryption / integrity engine, a decryption / de-integrity engine, a data compression engine, a ROHC engine, a reorder operation engine, an aggregation engine, or a de-aggregation engine.

[0124] According to another aspect of the present disclosure, a method of layer 2 data processing may include: identifying whether a data packet is associated with a first RAT or a second RAT. The method may also include: in response to determining that the data packet is associated with the first RAT, programming a plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT. The method may also include: in response to determining that the data packet is associated with the second RAT, programming a plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT.

[0125] In certain other aspects, the plurality of layer 2 circuits may include a first layer 2 circuit configured to control MAC operations associated with the first RAT and AMPDU operations associated with the second RAT.

[0126] In certain other aspects, the plurality of layer 2 circuits may include a second layer 2 circuit configured to perform RLC operations associated with the first RAT and BA operations associated with the second RAT.

[0127] In certain other aspects, the plurality of layer 2 circuits may include a third layer 2 circuit configured to perform PDCP operations associated with the first RAT and MPDU operations associated with the second RAT.

[0128] In certain other aspects, the first layer 2 circuit may be configured to control MAC operations and AMPDU operations performed by a first set of layer 2 engines associated with the first layer 2 circuit.

[0129] In certain other aspects, the second layer 2 circuit may be configured to control RLC operations and BA operations performed by a second set of layer 2 engines associated with the second layer 2 circuit.

[0130] In certain other aspects, the third layer 2 circuit may be configured to control PDCP operations and MPDU operations performed by a third set of layer 2 engines associated with the third layer 2 circuit.

[0131] In certain other aspects, programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT may include programming the first layer 2 circuit to control MAC operations performed by the first set of layer 2 engines. In certain other aspects, programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT may include programming the second layer 2 circuit to control RLC operations performed by the second set of layer 2 engines. In certain other aspects, programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT may include programming the third layer 2 circuit to control PDCP operations performed by the third set of layer 2 engines.

[0132] In certain other aspects, programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT may include programming the first layer 2 circuit to control AMPDU operations performed by the first set of layer 2 engines. In certain other aspects, programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT may include programming the second layer 2 circuit to control BA operations performed by the second set of layer 2 engines. In certain other aspects, programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT may include programming the third layer 2 circuit to control MPDU operations performed by the third set of layer 2 engines.

[0133] In certain other aspects, the first set of layer 2 engines may include one or more of a multiplexing engine, a demultiplexing engine, a header extraction engine, or a header generation engine.

[0134] In certain other aspects, the second set of layer 2 engines may include one or more of a segmentation engine, a reassembly engine, or a window operation engine.

[0135] In certain other aspects, the third set of layer 2 engines may include one or more of an encryption / integrity engine, a decryption / de-integrity engine, a data compression engine, a ROHC engine, a reorder operation engine, an aggregation engine, or a de-aggregation engine.

[0136] The above describes specific embodiments, revealing the general nature of the present disclosure, so that others can easily modify and / or adapt various applications of such specific embodiments by applying the knowledge within the art without excessive experimentation and without departing from the general concept of the present disclosure. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for the purpose of description rather than limitation, so that the terms or wording of this specification will be interpreted by those skilled in the art based on the teachings and guidance.

[0137] The embodiments of the present disclosure have been described above with the aid of functional building blocks, which illustrate the implementation of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may also be defined as long as the specified functions and their relationships can be appropriately performed.

[0138] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0139] Various functional blocks, modules and steps are disclosed above. The specific arrangements provided are illustrative rather than restrictive. Therefore, the functional blocks, modules and steps may be reordered or combined in a manner different from that in the examples provided above. Likewise, some embodiments include only a subset of the functional blocks, modules and steps, and any such subset is permitted.

[0140] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A baseband chip, comprising: a plurality of layer 2 circuits, each layer 2 circuit configured to perform layer 2 data processing operations associated with a first radio access technology (RAT) and a second radio access technology (RAT), the first RAT and the second RAT being different; and a microcontroller unit MCU configured to program the plurality of layer 2 circuits to perform layer 2 data processing operations associated with the first RAT or the second RAT, wherein The plurality of layer 2 circuits include at least a first layer 2 circuit, the first layer 2 circuit being associated with a first set of layer 2 engines, and The first set of layer 2 engines comprises at least a header extraction engine configured to extract a header according to a lookup table having an index, the index comprising a RAT type.

2. The baseband chip according to claim 1, further comprising: A buffer is configured to receive a layer 1 transport block from a first layer 1 circuit associated with the first RAT or from a second layer 1 circuit associated with the second RAT.

3. The baseband chip according to claim 2, wherein: In response to the buffer receiving the layer 1 transport block, the MCU is configured to: Identify whether the layer 1 transport block is received from a first layer 1 circuit associated with the first RAT or from a second layer 1 circuit associated with the second RAT.

4. The baseband chip according to claim 3, wherein: In response to identifying that the layer 1 transport block is received from the first layer 1 circuit, the MCU is further configured to: The plurality of layer 2 circuits are programmed to perform layer 2 data processing operations associated with the first RAT on the layer 1 transport blocks.

5. The baseband chip according to claim 3, wherein: In response to identifying that the layer 1 transport block is received from the second layer 1 circuit, the MCU is further configured to: The plurality of layer 2 circuits are programmed to perform layer 2 data processing operations associated with the second RAT on the layer 1 transport block.

6. The baseband chip according to claim 1, wherein: The first layer 2 circuit is configured to control medium access control (MAC) operations associated with the first RAT and aggregate MAC packet data unit (AMPDU) operations associated with the second RAT, The plurality of layer 2 circuits further include: a second layer 2 circuit configured to perform a radio link control, RLC, operation associated with the first RAT and a block acknowledgement, BA, operation associated with the second RAT, and A third layer 2 circuit is configured to perform a Packet Data Convergence Protocol (PDCP) operation associated with the first RAT and a MAC Packet Data Unit (MPDU) operation associated with the second RAT.

7. The baseband chip according to claim 6, wherein: The first layer 2 circuit is configured to control MAC operations and AMPDU operations performed by the first set of layer 2 engines, The second layer 2 circuit is configured to control RLC operations and BA operations performed by a second set of layer 2 engines associated with the second layer 2 circuit, and The third layer 2 circuit is configured to control PDCP operations and MPDU operations performed by a third set of layer 2 engines associated with the third layer 2 circuit.

8. The baseband chip according to claim 7, wherein: The first set of layer 2 engines also includes one or more of a multiplexing engine, a demultiplexing engine, or a header generation engine, The second set of layer 2 engines includes one or more of a segmentation engine, a reassembly engine, or a window operation engine, and The third set of layer 2 engines includes one or more of an encryption / integrity engine, a decryption / de-integrity engine, a data compression engine, a robust header compression ROHC engine, a reordering operation engine, an aggregation engine or a de-aggregation engine.

9. The baseband chip according to claim 1 further includes a memory, which is operably coupled to the MCU and the multiple layer 2 circuits and is configured to store multiple groups of commands in multiple command queues for extraction by at least one layer 2 circuit among the multiple layer 2 circuits.

10. The baseband chip according to claim 9, wherein: The memory is further configured to receive a plurality of sets of result status from the at least one layer 2 circuit and store the plurality of sets of result status in a plurality of status queues, respectively.

11. The baseband chip according to claim 10, wherein: The MCU is also configured to: retrieving the plurality of sets of result states from the memory; and A set of commands for controlling a corresponding one of the layer 2 circuits is generated based on a corresponding set of result states from another layer 2 circuit at a lower layer than the corresponding one of the layer 2 circuits in a layer 2 protocol stack.

12. A baseband chip, comprising: a first layer 2 circuit configured to control medium access control, MAC, operations associated with a first radio access technology, RAT, and aggregated MAC packet data unit, AMPDU, operations associated with a second RAT; a second layer 2 circuit configured to perform a radio link control, RLC, operation associated with the first RAT and a block acknowledgement, BA, operation associated with the second RAT; as well as a third layer 2 circuit configured to perform packet data convergence protocol (PDCP) operations associated with the first RAT and MAC packet data unit (MPDU) operations associated with the second RAT, wherein The first layer 2 circuit is associated with a first set of layer 2 engines, and The first set of layer 2 engines comprises at least a header extraction engine configured to extract a header according to a lookup table having an index, the index comprising a RAT type.

13. The baseband chip according to claim 12, wherein: The first layer 2 circuit is configured to control MAC operations and AMPDU operations by controlling the first set of layer 2 engines, the second layer 2 circuit being configured to control RLC operations and BA operations by controlling a second set of layer 2 engines associated with the second layer 2 circuit, and The third layer 2 circuit is configured to control PDCP operations and MPDU operations by controlling a third group of layer 2 engines associated with the third layer 2 circuit.

14. The baseband chip according to claim 13, wherein: The first set of layer 2 engines also includes one or more of a multiplexing engine, a demultiplexing engine, or a header generation engine, The second set of layer 2 engines includes one or more of a segmentation engine, a reassembly engine, or a window operation engine, and The third set of layer 2 engines includes one or more of an encryption / integrity engine, a decryption / de-integrity engine, a data compression engine, a robust header compression ROHC engine, a reordering operation engine, an aggregation engine or a de-aggregation engine.

15. A method of layer 2 data processing, comprising: Identify whether the data packet is associated with a first radio access technology RAT or a second RAT; responsive to determining that the data packet is associated with the first RAT, programming a plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT; as well as In response to determining that the data packet is associated with the second RAT, programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT, wherein The plurality of layer 2 circuits include at least a first layer 2 circuit, the first layer 2 circuit being associated with a first set of layer 2 engines, and The first set of layer 2 engines comprises at least a header extraction engine configured to extract a header according to a lookup table having an index, the index comprising a RAT type.

16. The method of claim 15, wherein: The first layer 2 circuit is configured to control medium access control, MAC, operations associated with a first radio access technology, RAT, and aggregated MAC packet data unit, AMPDU, operations associated with a second RAT; The plurality of layer 2 circuits further include: a second layer 2 circuit configured to perform a radio link control, RLC, operation associated with the first RAT and a block acknowledgement, BA, operation associated with a second RAT; as well as A third layer 2 circuit is configured to perform a Packet Data Convergence Protocol (PDCP) operation associated with the first RAT and a MAC Packet Data Unit (MPDU) operation associated with the second RAT.

17. The method of claim 16, wherein: The first layer 2 circuit is configured to control MAC operations and AMPDU operations performed by the first set of layer 2 engines, The second layer 2 circuit is configured to control RLC operations and BA operations performed by a second set of layer 2 engines associated with the second layer 2 circuit, and The third layer 2 circuit is configured to control PDCP operations and MPDU operations performed by a third set of layer 2 engines associated with the third layer 2 circuit.

18. The method according to claim 17, wherein: Programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the first RAT includes: programming the first layer 2 circuit to control MAC operations performed by the first set of layer 2 engines, programming the second layer 2 circuit to control RLC operations performed by a second set of layer 2 engines, and The third layer 2 circuit is programmed to control PDCP operations performed by a third set of layer 2 engines.

19. The method according to claim 18, wherein: Programming the plurality of layer 2 circuits to perform layer 2 data processing associated with the second RAT includes: programming the first layer 2 circuit to control AMPDU operations performed by the first set of layer 2 engines, programming the second layer 2 circuitry to control BA operations performed by a second set of layer 2 engines, and The third layer 2 circuit is programmed to control MPDU operations performed by a third set of layer 2 engines.

20. The method of claim 19, wherein: The first set of layer 2 engines also includes one or more of a multiplexing engine, a demultiplexing engine, or a header generation engine, The second set of layer 2 engines includes one or more of a segmentation engine, a reassembly engine, or a window operation engine, and The third set of layer 2 engines includes one or more of an encryption / integrity engine, a decryption / de-integrity engine, a data compression engine, a robust header compression ROHC engine, a reordering operation engine, an aggregation engine or a de-aggregation engine.

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