High precision zero current detection circuit for wide input range improved ky converter

Abstract

The application discloses a high-precision zero-current detection circuit for a wide-input-range improved KY converter, wherein a main power switch tube is connected with an input end of a resistance voltage division network and a compensation network and an input end of an error amplifier, a zero-current detection circuit is connected with a seventh switch tube in the main power switch tube, an output end of the compensation network and an output end of the error amplifier are connected with input ends of comparators, output ends of the comparators and an output end of the zero-current detection circuit are connected with input ends of a driving and dead zone generation circuit, an input end of an adaptive mode switching circuit is connected with a signal input end, an output end of the adaptive mode switching circuit is connected with an input end of the driving and dead zone generation circuit, and an output end of the driving and dead zone generation circuit is connected with the main power switch tube. The circuit can accurately detect the zero-crossing point of a reverse current in the improved KY converter under a light load condition, and completely eliminates the reverse current.

Description

Technical Field

[0001] This invention belongs to the field of power management technology and relates to a high-precision zero-current detection circuit for an improved KY converter with a wide input range. Background Technology

[0002] Power management modules are essential components in integrated circuit applications. In traditional power management modules, boost converters are often used to implement the function of boosting the output voltage. However, due to the discontinuous inductor current (L) of the boost converter, its output voltage ripple is relatively large. Using an additional coupling inductor (L) on top of the boost converter can effectively reduce the output ripple, but the boost converter itself has a right-half-plane zero, so the control loop requires a complex compensation network. The KY structure is a newly proposed boost converter structure in recent years. Its main power stage circuit does not have a right-half-plane zero, which greatly reduces the difficulty of compensation. Moreover, compared with the boost structure, the KY structure has better transient response and lower output ripple. Therefore, recent research has mainly focused on improving the KY structure converter. However, when the load current of the converter is small, the reverse current is difficult to completely eliminate due to the multiple reverse current paths and RLC series resonant circuit in the KY structure. Especially in applications with a wide load range, the detection difficulty of reverse current is further increased due to the small on-state voltage drop of large-size power switches. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-precision zero-current detection circuit for an improved KY converter with a wide input range. This circuit can accurately detect the zero-crossing point of the reverse current in the improved KY converter under light load conditions and completely eliminate the reverse current.

[0004] To achieve the above objectives, the high-precision zero-current detection circuit for a wide-input-range improved KY converter described in this invention includes a signal input terminal, a main power switch, a resistor divider network, a drive and dead-time generation circuit, and a logic control circuit. The logic control circuit includes an adaptive mode switching circuit, an error amplifier, a comparator, a compensation network, and a zero-current detection circuit.

[0005] The main power switch is connected to the input of the compensation network and the input of the error amplifier through a resistor divider network. The zero current detection circuit is connected to the seventh switch in the main power switch. The output of the compensation network and the output of the error amplifier are connected to the input of the comparator. The output of the comparator and the output of the zero current detection circuit are connected to the input of the drive and dead time generation circuit.

[0006] The input terminal of the adaptive mode switching circuit is connected to the signal input terminal, the output terminal of the adaptive mode switching circuit is connected to the input terminal of the drive and dead-time generation circuit, and the output terminal of the drive and dead-time generation circuit is connected to the main power switch.

[0007] The main power switching transistors include an inductor, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, a first capacitor, and a second capacitor;

[0008] The signal input terminal is connected to one end of the second switch and one end of the third switch. The other end of the second switch is connected to one end of the first switch, one end of the fourth switch, and one end of the second capacitor. One end of the third switch is connected to one end of the inductor, one end of the first capacitor, and one end of the sixth switch. The other end of the fourth switch is connected to the other end of the first capacitor and one end of the fifth switch. The other end of the fifth switch is connected to the other end of the second capacitor and the other end of the sixth switch. One end of the seventh switch is connected to the other end of the inductor. The other end of the seventh switch is connected to the signal output terminal. The signal output terminal is connected to the resistor divider network.

[0009] The first, second, third, fourth, fifth, sixth, and seventh switching transistors, as well as the first and second capacitors, are all power MOSFET switching transistors.

[0010] The first output terminal of the drive and dead-time generation circuit is connected to the control terminal of the first switch transistor. The second output terminal of the drive and dead-time generation circuit is connected to the control terminal of the second switch transistor. The third output terminal of the drive and dead-time generation circuit is connected to the control terminal of the third switch transistor. The fourth output terminal of the drive and dead-time generation circuit is connected to the control terminal of the fourth switch transistor. The fifth output terminal of the drive and dead-time generation circuit is connected to the control terminal of the fifth switch transistor. The sixth output terminal of the drive and dead-time generation circuit is connected to the control terminal of the sixth switch transistor. The seventh output terminal of the drive and dead-time generation circuit is connected to the control terminal of the sixth switch transistor.

[0011] By controlling the on and off of the first, second, third, fourth, fifth, sixth, and seventh switching transistors through the drive and dead-time generation circuit, a boost ratio of up to (1+2D) times can be achieved.

[0012] For the boost ratio of (1+D), the three stages are:

[0013] Phase 1: The second, fourth, sixth, and seventh switches are turned on, while the first, third, and fifth switches are turned off. The inductor is charged by the input voltage and the flying capacitor, which includes the first and second capacitors.

[0014] Phase 2: The first, third, fourth, sixth, and seventh switches are turned on, the second and fifth switches are turned off, the flying capacitor is charged by the input voltage, and the inductor is discharged.

[0015] Phase 3: The first, second, third, fourth, fifth, sixth, and seventh switches are turned off, and the improved KY converter operates in discontinuous conduction mode, completely eliminating reverse current.

[0016] For the (1+2D) boost ratio, the three stages are:

[0017] Phase 1: The second, fifth, and seventh switches are turned on, while the first, third, fourth, and sixth switches are turned off. The inductor is charged by the input voltage and the flying capacitor.

[0018] Phase 2: The first, third, fourth, sixth, and seventh switches are turned on, the second and fifth switches are turned off, the flying capacitor is charged by the input voltage, and the inductor is discharged.

[0019] Phase 3: The first, second, third, fourth, fifth, sixth, and seventh switches are turned off, and the improved KY converter operates in discontinuous conduction mode, completely eliminating reverse current.

[0020] The resistor divider network includes a third capacitor, a first resistor, a second resistor, and a third resistor. One end of the inductor is connected to the third switch, the first capacitor, and the sixth switch. The seventh switch is connected to one end of the third capacitor, one end of the third resistor, and one end of the first resistor. The other ends of the third capacitor, the third resistor, and the second resistor are all grounded. The other ends of the first resistor and the second resistor are connected to the input terminals of the logic control circuit.

[0021] The present invention has the following beneficial effects:

[0022] The high-precision zero-current detection circuit for the wide-input-range improved KY converter described in this invention, in practical operation, can achieve a boost ratio of up to (1+2D) times by controlling the turn-on and turn-off sequence of the main power switches, and completely eliminates reverse circuitry in discontinuous conduction mode (DCM). Furthermore, the drive and dead-time generation circuits are used to generate control signals for the power MOS switches. The dead-time control circuit generates a non-overlapping clock, preventing MOS switches controlled by opposite-phase signals from simultaneously turning on when the clock flips. It should be noted that the improved KY converter operates in continuous conduction mode (CCM) under a wide load current. At load currents below 150mA, the zero-current detection circuit can accurately detect the zero-crossing point of the inductor L current, enabling the improved KY converter to operate in discontinuous conduction mode (DCM), eliminating reverse current and improving energy conversion efficiency. Attached Figure Description

[0023] Figure 1 This is a topological diagram of the present invention;

[0024] Figure 2 This is a schematic diagram of the main power switch 1 in this invention;

[0025] Figure 3 This is a circuit diagram of the adaptive mode switching circuit in this invention;

[0026] Figure 4 This is a circuit diagram of the zero-current detection circuit in this invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, not all embodiments, and are not intended to limit the scope of the present invention. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion regarding the concepts disclosed in the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the scope of protection of the present invention.

[0028] The accompanying drawings show structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not drawn to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0029] refer to Figure 1 The high-precision zero-current detection circuit for a wide-input-range improved KY converter described in this invention includes a main power switch 1, a resistor divider network, a drive and dead-time generation circuit 2, and a logic control circuit 3. The logic control circuit 3 includes an adaptive mode switching circuit, a pulse width modulation circuit, a compensation network, and a zero-current detection circuit. The main power switch 1 is connected to the input of the compensation network and the input of the error amplifier through the resistor divider network. The zero-current detection circuit is connected to the seventh switch S7 in the main power switch 1. The output of the compensation network and the output of the error amplifier are connected to the input of the comparator. The output of the comparator and the output of the zero-current detection circuit are connected to the input of the drive and dead-time generation circuit 2.

[0030] The input terminal and signal input terminal V of the adaptive mode switching circuit IN The output of the adaptive mode switching circuit is connected to the input of the drive and dead-time generation circuit 2, and the output of the drive and dead-time generation circuit 2 is connected to the main power switch 1 to control the turn-off of each switch in the main power switch 1, thereby realizing the boost function of the improved KY converter.

[0031] refer to Figure 1 and Figure 2 The main power switch 1 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, a first capacitor C1, and a second capacitor C2. The first switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, sixth switch S6, seventh switch S7, first capacitor C1, and second capacitor C2 are all power MOS switches. The signal input terminal V... IN One end of the second switch S2 and one end of the third switch S3 are connected. The other end of the second switch S2 is connected to one end of the first switch S1, one end of the fourth switch S4, and one end of the second capacitor C2. One end of the third switch S3 is connected to one end of the inductor L, one end of the first capacitor C1, and one end of the sixth switch S6. The other end of the fourth switch S4 is connected to the other end of the first capacitor C1 and one end of the fifth switch S5. The other end of the fifth switch S5 is connected to the other end of the second capacitor C2 and the other end of the sixth switch S6. One end of the seventh switch S7 is connected to the other end of the inductor L. The other end of the seventh switch S7 is connected to the signal output terminal V. OUT Connected, signal output terminal V OUT It is connected to a resistor divider network.

[0032] refer to Figure 1 and Figure 2 The first output terminal of the drive and dead-time generation circuit 2 is connected to the control terminal of the first switch S1; the second output terminal of the drive and dead-time generation circuit 2 is connected to the control terminal of the second switch S2; the third output terminal of the drive and dead-time generation circuit 2 is connected to the control terminal of the third switch S3; the fourth output terminal of the drive and dead-time generation circuit 2 is connected to the control terminal of the fourth switch S4; the fifth output terminal of the drive and dead-time generation circuit 2 is connected to the control terminal of the fifth switch S5; the sixth output terminal of the drive and dead-time generation circuit 2 is connected to the control terminal of the sixth switch S6; the seventh output terminal of the drive and dead-time generation circuit 2 is connected to the control terminal of the sixth switch S7; and the input terminal of the adaptive mode switching circuit is connected to the signal input terminal V. IN The zero-current detection circuit is connected to the two ends of the seventh switch S7. The three input terminals of the drive and dead-time generation circuit 2 are respectively connected to the output terminal of the adaptive mode switching circuit, the output terminal of the zero-current detection circuit, and the output terminal of the comparator.

[0033] In this invention, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7 are controlled by the drive and dead-time generation circuit 2 to achieve a maximum boost ratio of (1+2D). Under light load conditions, this invention operates in a discontinuous conduction mode, and each cycle is divided into three operating stages at boost ratios of (1+D) and (1+2D).

[0034] For the boost ratio of (1+D), the three stages are:

[0035] Phase 1: The second switch S2, the fourth switch S4, the sixth switch S6 and the seventh switch S7 are turned on, the first switch S1, the third switch S3 and the fifth switch S5 are turned off, and the inductor L is charged by the input voltage and the flying capacitor, wherein the flying capacitor includes the first capacitor C1 and the second capacitor C2.

[0036] Phase 2: The first switch S1, the third switch S3, the fourth switch S4, the sixth switch S6 and the seventh switch S7 are turned on, the second switch S2 and the fifth switch S5 are turned off, the flying capacitor is charged by the input voltage, and the inductor L is discharged.

[0037] Phase 3: Switches S1, S2, S3, S4, S5, S6 and S7 are turned off, and the improved KY converter operates in discontinuous conduction mode, completely eliminating reverse current.

[0038] For the (1+2D) boost ratio, the three stages are:

[0039] Phase 1: The second switch S2, the fifth switch S5, and the seventh switch S7 are turned on, while the first switch S1, the third switch S3, the fourth switch S4, and the sixth switch S6 are turned off. The inductor L is charged by the input voltage and the flying capacitor.

[0040] Phase 2: The first switch S1, the third switch S3, the fourth switch S4, the sixth switch S6 and the seventh switch S7 are turned on, the second switch S2 and the fifth switch S5 are turned off, the flying capacitor is charged by the input voltage, and the inductor L is discharged.

[0041] Phase 3: Switches S1, S2, S3, S4, S5, S6 and S7 are turned off, and the improved KY converter operates in discontinuous conduction mode, completely eliminating reverse current.

[0042] refer to Figure 2 The main power switching transistor 1 of the present invention includes the first switching transistor S1, the second switching transistor S2, the third switching transistor S3, the fourth switching transistor S4, and the fifth switching transistor S5. 及 The sixth switch S6 completes the boost function of the improved KY converter through switching. The seventh switch S7 is used to block the reverse current from the series path of the inductor L, preventing the reverse current from flowing to the multiple reverse current paths formed by the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6, which can fundamentally eliminate the reverse current.

[0043] refer to Figure 3 The adaptive mode switching circuit includes a first voltage divider resistor R. 11 Second voltage divider resistor R 12 The circuit includes a comparator, a first D flip-flop, a first inverter, and a first OR gate, wherein the signal input terminal V... IN With the first voltage divider resistor R 11 One end is connected to the D pin and VDD pin of the first D flip-flop, and the first voltage divider resistor R 11 The other end is connected to the second voltage divider resistor R 12 One end of the first input is connected to the negative input of the comparator, and the output of the comparator is connected to the CLK pin of the first D flip-flop. The two inputs of the first OR gate are connected to the inverting output of the first D flip-flop and the output of the first inverter, respectively. The first input V... REFThe first input terminal is connected to the positive input terminal of the comparator. The second input terminal EN_1D_CTRL is connected to the RESET pin of the first D flip-flop. The third input terminal EN_1D is connected to the input terminal of the first inverter. The adaptive mode can be turned on and off by controlling the second input terminal EN_1D_CTRL. When the adaptive mode is turned on, the input voltage is automatically detected. When the input voltage exceeds 1.8V, it automatically switches to the (1+D) boost mode. The boost mode can also be manually switched from the outside by controlling the third input terminal EN_1D. The output terminal of the first OR gate circuit is connected to the input terminal of the drive and dead time generation circuit 2.

[0044] refer to Figure 4 The zero-current detection circuit includes a rail-to-rail input amplifier, a first positive input terminal V+, a second negative input terminal V-, a fourth input terminal S2, a buffer, a second D flip-flop, a second inverter, and a second OR gate circuit. The first positive input terminal V+ and the second negative input terminal V- are connected to the two input terminals of the rail-to-rail input amplifier. The output terminal of the rail-to-rail input amplifier is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the CLK pin of the second D flip-flop. The D pin of the second D flip-flop is connected to the VDD pin of the second D flip-flop. The fourth input terminal S2 is connected to the input terminal of the second inverter and one input terminal of the OR gate circuit. The output terminal of the second inverter is connected to the RESET pin of the second D flip-flop. The inverted output terminal of the second D flip-flop is connected to the other input terminal of the second OR gate circuit. The output terminal of the second OR gate circuit is connected to the input terminal of the drive and dead-time generation circuit 2.

[0045] The present invention also includes an inductor L, a third capacitor C, a first resistor R1, a second resistor R2, and a third resistor R L One end of inductor L is connected to the third switch S3, the first capacitor C1, and the sixth switch S6. The other end of inductor L is connected to one end of the seventh switch S7 and the first signal input terminal of the zero-current detection circuit. The other end of the seventh switch S7 is connected to one end of the third capacitor C and the third resistor R. L One end of the capacitor C is connected to one end of the first resistor R1, and the other end of the third capacitor C and the third resistor R L The other end of the first resistor R1 and one end of the second resistor R2 are both grounded, and the other end of the first resistor R1 and the other end of the second resistor R2 are connected to the input terminal of the logic control circuit 3.

[0046] The drive and dead-time generation circuit 2 of this invention is used to generate control signals for the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7. In continuous conduction mode, the duty cycle of the control signal is determined by the PWM control loop. However, in discontinuous conduction mode, the duty cycle of the control signal is simultaneously regulated by the zero-current detection circuit.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A high-precision zero-current detection circuit for an improved KY converter with a wide input range, characterized in that, Including signal input terminal (V IN The circuit consists of a main power switch (1), a resistor divider network, a drive and dead zone generation circuit (2), and a logic control circuit (3). The logic control circuit (3) includes an adaptive mode switching circuit, an error amplifier, a comparator, a compensation network, and a zero current detection circuit. The main power switch (1) is connected to the input of the compensation network and the input of the error amplifier through the resistor voltage divider network. The zero current detection circuit is connected to the seventh switch (S7) in the main power switch (1). The output of the compensation network and the output of the error amplifier are connected to the input of the comparator. The output of the comparator and the output of the zero current detection circuit are connected to the input of the drive and dead zone generation circuit (2). The input terminal and signal input terminal (V) of the adaptive mode switching circuit IN The output of the adaptive mode switching circuit is connected to the input of the drive and dead zone generation circuit (2), and the output of the drive and dead zone generation circuit (2) is connected to the main power switch (1). The main power switching transistor (1) includes an inductor (L), a first switching transistor (S1), a second switching transistor (S2), a third switching transistor (S3), a fourth switching transistor (S4), a fifth switching transistor (S5), a sixth switching transistor (S6), a seventh switching transistor (S7), a first capacitor (C1), and a second capacitor (C2). Signal input terminal (V) IN The first switch (S1) is connected to one end of the second switch (S2) and one end of the third switch (S3). The other end of the second switch (S2) is connected to one end of the first switch (S1), one end of the fourth switch (S4), and one end of the second capacitor (C2). One end of the third switch (S3) is connected to one end of the inductor (L), one end of the first capacitor (C1), and one end of the sixth switch (S6). The other end of the fourth switch (S4) is connected to the other end of the first capacitor (C1) and one end of the fifth switch (S5). The other end of the fifth switch (S5) is connected to the other end of the second capacitor (C2) and the other end of the sixth switch (S6). One end of the seventh switch (S7) is connected to the other end of the inductor (L). The other end of the seventh switch (S7) is connected to the signal output terminal (V). OUT Connected to the signal output terminal (V) OUT It is connected to a resistor divider network; The first switch (S1), second switch (S2), third switch (S3), fourth switch (S4), fifth switch (S5), sixth switch (S6) and seventh switch (S7) are controlled by the drive and dead zone generation circuit (2) to achieve a boost ratio of up to (1+2D) times.

2. The high-precision zero-current detection circuit for a wide-input-range improved KY converter according to claim 1, characterized in that, The first switch (S1), the second switch (S2), the third switch (S3), the fourth switch (S4), the fifth switch (S5), the sixth switch (S6), the seventh switch (S7), the first capacitor (C1), and the second capacitor (C2) are all power MOSFETs.

3. The high-precision zero-current detection circuit for a wide-input-range improved KY converter according to claim 1, characterized in that, The first output terminal of the drive and dead zone generation circuit (2) is connected to the control terminal of the first switch (S1), the second output terminal of the drive and dead zone generation circuit (2) is connected to the control terminal of the second switch (S2), the third output terminal of the drive and dead zone generation circuit (2) is connected to the control terminal of the third switch (S3), the fourth output terminal of the drive and dead zone generation circuit (2) is connected to the control terminal of the fourth switch (S4), the fifth output terminal of the drive and dead zone generation circuit (2) is connected to the control terminal of the fifth switch (S5), the sixth output terminal of the drive and dead zone generation circuit (2) is connected to the control terminal of the sixth switch (S6), and the seventh output terminal of the drive and dead zone generation circuit (2) is connected to the control terminal of the seventh switch (S7).

4. The high-precision zero-current detection circuit for a wide-input-range improved KY converter according to claim 1, characterized in that, For the boost ratio of (1+D), the three stages are: Phase 1: The second switch (S2), the fourth switch (S4), the sixth switch (S6) and the seventh switch (S7) are turned on, the first switch (S1), the third switch (S3) and the fifth switch (S5) are turned off, and the inductor (L) is charged by the input voltage and the flying capacitor, wherein the flying capacitor includes the first capacitor (C1) and the second capacitor (C2). Phase 2: The first switch (S1), the third switch (S3), the fourth switch (S4), the sixth switch (S6) and the seventh switch (S7) are turned on, the second switch (S2) and the fifth switch (S5) are turned off, the flying capacitor is charged by the input voltage, and the inductor (L) is discharged. Phase 3: The first switch (S1), the second switch (S2), the third switch (S3), the fourth switch (S4), the fifth switch (S5), the sixth switch (S6), and the seventh switch (S7) are turned off, and the improved KY converter operates in discontinuous conduction mode, completely eliminating reverse current.

5. The high-precision zero-current detection circuit for a wide-input-range improved KY converter according to claim 1, characterized in that, For the (1+2D) boost ratio, the three stages are: Phase 1: The second switch (S2), the fifth switch (S5) and the seventh switch (S7) are turned on, the first switch (S1), the third switch (S3), the fourth switch (S4) and the sixth switch (S6) are turned off, and the inductor (L) is charged by the input voltage and the flying capacitor. Phase 2: The first switch (S1), the third switch (S3), the fourth switch (S4), the sixth switch (S6) and the seventh switch (S7) are turned on, the second switch (S2) and the fifth switch (S5) are turned off, the flying capacitor is charged by the input voltage, and the inductor (L) is discharged. Phase 3: The first switch (S1), the second switch (S2), the third switch (S3), the fourth switch (S4), the fifth switch (S5), the sixth switch (S6), and the seventh switch (S7) are turned off, and the improved KY converter operates in discontinuous conduction mode, completely eliminating reverse current.

6. The high-precision zero-current detection circuit for a wide-input-range improved KY converter according to claim 1, characterized in that, The resistor divider network includes a third capacitor (C), a first resistor (R1), a second resistor (R2), and a third resistor (R... L In this circuit, one end of the inductor (L) is connected to the third switch (S3), the first capacitor (C1), and the sixth switch (S6). The seventh switch (S7) is connected to one end of the third capacitor (C) and the third resistor (R). L One end of the capacitor (C) is connected to one end of the first resistor (R1), and the other end of the third capacitor (C) is connected to one end of the third resistor (R). L The other end of the first resistor (R1) and one end of the second resistor (R2) are grounded, and the other end of the first resistor (R1) and the other end of the second resistor (R2) are connected to the input terminal of the logic control circuit (3).

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