Instruction testing and debugging method and multi-core digital signal processor thereof

Abstract

The embodiment of the present application relates to the technical field of digital signal processor, in particular to a kind of instruction test and debugging method and its multicore digital signal processor.The method realizes the single-step test and cross-debugging of the instruction of multicore digital signal processor.Any kernel can be set as test kernel, and the test program built-in in the memory is loaded through the test kernel to carry out the detailed test of the whole phase of instruction, the error state of instruction execution can be quickly located, the test coverage is improved, and the test cost and test time are reduced;Single instruction whole phase debugging instruction state can be directly obtained, the debugging of single instruction is realized, and multiple instructions can also form a program for debugging, to improve the debugging coverage.The method greatly improves the test and debugging capability of the kernel instruction of multicore digital signal processor, reduces the difficulty of subsequent test program development, improves the test coverage, and is beneficial to the analysis and judgment of instruction in the use process of multicore digital signal processor.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the technical field of digital signal processor, in particular to a kind of instruction test and debugging method and its multicore digital signal processor. BACKGROUND

[0002] With the continuous development of economy, the demand of self-controllable chip in our country is also more and more big, especially the demand of high-performance multicore chip applicable to industry and car enterprise is increasing day by day.

[0003] With the increasing demand of domestic self-research and development of domestic chip, there is great requirement for the application occasion and chip performance of designed multicore digital signal processor chip. Therefore, it is necessary to continuously increase instructions and expand the instruction set of chip.

[0004] The existing technology is mainly to test the program of chip, and the development test of core instruction set and the adaptation test of new instruction set are very few, especially in the field of digital signal processor chip, therefore, how to better verify or confirm whether the digital signal processor chip can perfectly run the new instruction set or the existing instruction set is a problem to be solved at present. SUMMARY

[0005] The following is a summary of the subject matter described in detail in this document. This summary is not intended to limit the scope of protection of the claims.

[0006] The main purpose of the embodiment of the present disclosure is to propose a kind of instruction test and debugging method and its multicore digital signal processor, can greatly improve the test and debugging capability of multicore digital signal processor core instruction, reduce the difficulty of subsequent test program development, improve test coverage, be favorable to the analysis and judgment of instruction in the use process of multicore digital signal processor.

[0007] To achieve the above-mentioned purpose, the first aspect of the embodiment of the present disclosure proposes an instruction test and debugging method for digital signal processor with multiple cores, the instruction test and debugging method comprises:

[0008] When receiving test enable signal, enter test mode and execute first flow; when entering the test mode, receive debugging enable signal, enter the debugging mode and execute second flow;

[0009] The first flow comprises: calling the to-be-tested instruction from the local memory through a bus, and starting at least one of the plurality of cores as a test core to make the test core run the to-be-tested instruction through a pipeline built in the test core to obtain a first running state of the to-be-tested instruction at different stages of the pipeline; comparing the first running state with a second running state of the to-be-tested instruction at different stages obtained through prior testing to obtain a test result of the to-be-tested instruction by the test core.

[0010] The second flow comprises: calling a plurality of to-be-debugged instructions from the local memory through a bus, and starting at least one of the plurality of cores as a debug core to make the debug core run the plurality of to-be-debugged instructions to obtain a debug result of the plurality of to-be-debugged instructions.

[0011] The first aspect of the embodiment of the application provides an instruction testing and debugging method, which realizes single-step testing and cross debugging of instructions of a multi-core digital signal processor. In a testing mode, any core can be set as a test core to load a test program built in a memory through the test core to perform detailed testing of instructions at all stages, so that an error state of the instructions during execution can be quickly located, testing coverage is improved, and the test program of a test machine does not need to be written during testing, and the test program does not need to be loaded through external connection, thereby reducing testing cost and testing time; in a debugging mode, a single instruction can be directly obtained to obtain a debugging instruction state at all stages, debugging of a single instruction is realized, and a plurality of instructions can also be debugged to form a program, thereby improving debugging coverage. The method greatly improves the testing and debugging capability of the instructions of the multi-core digital signal processor, reduces the difficulty of subsequent development of a test program, improves testing coverage, and is beneficial to analysis and judgment of the instructions of the multi-core digital signal processor during use.

[0012] In some embodiments, the comparing the first running state with a second running state of the to-be-tested instruction at different stages comprises:

[0013] According to an instruction flag bit of the to-be-tested instruction, the second running state of the to-be-tested instruction at different stages is found from an instruction lookup table in the local memory;

[0014] The second running state and the first running state are respectively input into a comparator;

[0015] The second running state and the first running state are compared through the comparator.

[0016] In some embodiments, when one of the to-be-tested instructions is tested by one of the test cores, the one of the test cores runs the to-be-tested instruction through the built-in pipeline to obtain first running states of the to-be-tested instruction at different stages of the pipeline, and stores the first running states at different stages in local registers; and another one of the test cores extracts the first running states from the registers, and compares the first running states with the second running states.

[0017] In some embodiments, when a plurality of the to-be-tested instructions are tested by a plurality of the test cores, each of the test cores runs a corresponding one of the to-be-tested instructions to obtain first running states of the corresponding one of the to-be-tested instructions at different stages of the pipeline and store the first running states in local registers; and any one of the test cores extracts the first running states of each of the to-be-tested instructions from the registers, and compares each of the first running states with a corresponding one of the second running states.

[0018] In some embodiments, when the number of the to-be-debugged instructions is a plurality of instructions, the debug core runs the to-be-debugged instructions to obtain debug results of the to-be-debugged instructions, including:

[0019] forming a to-be-debugged program from the plurality of to-be-debugged instructions, and storing the to-be-debugged program in the local memory;

[0020] calling the to-be-debugged program from the local memory through the bus and running the to-be-debugged program to obtain debug results of the to-be-debugged program at different stages of the pipeline.

[0021] In some embodiments, the debug results are obtained by:

[0022] inputting first running states of the to-be-debugged instructions at different stages of the pipeline into boundary scan registers, and outputting the first running states as debug results through a built-in boundary scan chain.

[0023] In some embodiments, upon receiving the test enabling signal, the instruction testing and debugging method further includes:

[0024] receiving a test mode entry password instruction;

[0025] entering the test mode when the password instruction verification is successful.

[0026] In some embodiments, the second process further includes:

[0027] connecting a test machine;

[0028] The test machine loads the to-be-debugged instruction from the local memory and runs to obtain a debugging result of the to-be-debugged instruction.

[0029] The second aspect of the embodiments of the present application provides a multi-core digital signal processor, which is used to execute the instruction testing and debugging method of the first aspect.

[0030] In some embodiments, the plurality of cores includes a plurality of fixed-point cores and a plurality of floating-point cores.

[0031] It can be understood that the beneficial effects of the second aspect compared with the related art are the same as the beneficial effects of the first aspect compared with the related art, which can be referred to the related description in the first aspect and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or related description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 is a flowchart of an instruction testing and debugging method provided by an embodiment of the present application;

[0034] Figure 2 is a flowchart of password verification provided by an embodiment of the present application;

[0035] Figure 3 is a comparative flowchart of testing instruction running state provided by an embodiment of the present application;

[0036] Figure 4 is a schematic diagram of instruction flag bit and instruction data bit provided by an embodiment of the present application;

[0037] Figure 5 is a flowchart of running a plurality of debugging instructions provided by an embodiment of the present application;

[0038] Figure 6 is a debugging flowchart of debugging instruction by a test machine provided by an embodiment of the present application;

[0039] Figure 7 is a structural schematic diagram of CPU+FPU pipeline instruction execution state of a digital signal processor provided by an embodiment of the present application;

[0040] Figure 8is a kernel test mode structure schematic diagram provided by an embodiment of the present application;

[0041] Figure 9 is a flowchart of a test and debugging method of a multi-core digital signal processor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0042] For the purpose, technical solutions and advantages of the present application to be more clear and explicit, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0043] It should be noted that although the functional modules are divided in the device schematic diagram, and the logical sequence is shown in the flowchart, in some cases, the steps shown or described can be executed in a manner different from the module division in the device or the sequence in the flowchart. The terms "first", "second", etc. in the specification and claims and the above-described drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0045] The existing technology is mostly to test the program of the chip, and the development test of the kernel instruction set and the adaptation test of the new instruction set are rarely done, especially in the field of digital signal processor chip. Therefore, how to better verify or confirm whether the digital signal processor chip can perfectly run the new instruction set or the existing instruction set is a problem to be solved at the present stage.

[0046] In the field, in order to continuously improve the use range of the digital signal processor, it is necessary to continuously increase the new instruction set, and then realize the new function. These new instruction sets and the original instruction set need to be tested and debugged quickly during the test and debugging of the digital signal processor, especially when designing the multi-core kernel test. Therefore, the present application provides an instruction test and debugging method for reducing the test time of the chip and reducing the test cost of the chip.

[0047] Please refer to Figure 1 An embodiment of the present application provides an instruction test and debugging method for a multi-core digital signal processor, which comprises the following steps S100 and S200:

[0048] Step S100: When the test enable signal is received, enter the test mode and execute the first process; after entering the test mode, receive the debug enable signal, enter the debug mode and execute the second process.

[0049] In some embodiments of this application, the digital signal processor of this embodiment has multiple cores, such as several fixed-point cores or several floating-point cores.

[0050] After power-on and exiting the power-on reset mode, the digital signal processor (DSP) can input a test enable signal through its GPIO (General-purpose input / output) pins, causing the DSP to execute the first procedure in step S200 (referred to here as test mode). When the DSP is in test mode, a debug enable signal can be input through its GPIO pins, causing the DSP to execute the second procedure in step S200 (referred to here as debug mode). This application refers to the first and second procedures as the instruction adaptation process of this application.

[0051] like Figure 2 As shown, in some embodiments of this application, when receiving a test enable signal, the method further includes the following steps S301 and S302:

[0052] Step S301: Receive the password command to enter test mode.

[0053] Step S302: After the password command is successfully verified, enter the test mode.

[0054] Simultaneously with sending a test enable signal to the digital signal processor (DSP), a password command is input based on a pin to enter the test mode. Only after the password command is successfully verified will the DSP enter the first process. The purpose of setting a password here is to prevent unauthorized users from processing the DSP. Furthermore, this method is primarily for factory testing and debugging of the DSP; issuing the password prevents unauthorized testing and debugging.

[0055] Step S200, the first process includes: calling test instructions from local memory via the bus, and starting at least one kernel from multiple kernels as a test kernel, so that the test kernel runs the test instructions through its built-in pipeline, obtaining the first running state of the test instructions at different stages of the pipeline; comparing the first running state with the second running state of the pre-tested test instructions at different stages, to obtain the test result of the test kernel on the test instructions. The second process includes: calling several instructions to be debugged from local memory via the bus, and starting at least one kernel from multiple kernels as a debug kernel, so that the debug kernel runs the several instructions to be debugged, obtaining the debugging result of the several instructions to be debugged.

[0056] The first flow is introduced as follows: after entering the test mode, the digital signal processor starts the test kernel. Here, one or more kernels can be used as the test kernel. Then the test kernel calls the to-be-tested instruction from the built-in memory of the digital signal processor through the bus and runs it. The to-be-tested instruction is an instruction pre-input into the memory of the digital signal processor, which can be a single instruction or multiple instructions. The test kernel runs the to-be-tested instruction through the built-in pipeline, and the first running state of the to-be-tested instruction at different stages of the pipeline is obtained. The first running state includes the running state of the instruction at each stage (acquisition, decoding, and execution, etc.), in which the instruction is decomposed into 32-bit binary data at different stages. The digital signal processor also calls a second running state (standard result) of the to-be-tested instruction pre-tested from the memory, and compares the first running state with the second running state to obtain the error state of the instruction running, so as to quickly locate the specific circuit structure of the kernel executing the instruction, and quickly perform instruction analysis and confirmation.

[0057] As shown in Figure 3 In some embodiments of the present application, the first running state and the second running state are compared, including steps S401 to S403:

[0058] Step S401, according to the instruction flag bit of the to-be-tested instruction, the second running state of the to-be-tested instruction at different stages is found from the instruction lookup table in the local memory.

[0059] Step S402, the second running state and the first running state are respectively input into the comparator.

[0060] Step S403, the second running state and the first running state are compared by the comparator.

[0061] As shown in Figure 4 An instruction lookup table is set in the memory, which records the instruction flag bit and the instruction data bit of the to-be-tested instruction. The second running state of the instruction in the running process can be found from the instruction lookup table through the flag bit (its state is represented by the data bit). Then the second running state and the first running state are respectively input into the comparator, and the comparator is used to quickly compare whether the values at the acquisition, decoding, and execution stages are correct.

[0062] In some embodiments of the present application, when testing a to-be-tested instruction by multiple test kernels, one of the test kernels runs the to-be-tested instruction through the built-in pipeline to obtain first running states of the to-be-tested instruction at different stages of the pipeline and stores the first running states at different stages in local registers, and another of the test kernels extracts the first running states from the registers and compares the first running states with second running states.

[0063] In some embodiments of the present application, when testing multiple to-be-tested instructions by multiple test kernels, each of the test kernels runs a corresponding to-be-tested instruction to obtain first running states of the corresponding to-be-tested instruction at different stages of the pipeline and stores the first running states in local registers; and any one of the test kernels extracts the first running states of each of the to-be-tested instructions from the registers and compares each of the first running states with a corresponding second running state.

[0064] When two identical kernels test the same to-be-tested instruction, the data obtained by executing the same instruction should be completely consistent because the kernel structures are completely identical. Therefore, one of the kernels can be used to perform full-stage testing of the to-be-tested instruction, and the other kernel only needs to compare the execution data of the to-be-tested instruction.

[0065] When two identical kernels test corresponding to-be-tested instructions respectively, the instructions are cross-verified, and the data obtained by fetching, decoding and executing the two to-be-tested instructions are written into the built-in registers of the kernels, and then the test kernels quickly find and compare the data, which can reduce a large amount of testing time.

[0066] The second process is described below:

[0067] The digital signal processor calls a plurality of to-be-debugged instructions from a memory. The to-be-debugged instructions are newly added instructions and are stored in the memory in advance. The digital signal processor starts at least one of the multiple kernels as a debugging kernel, calls the to-be-debugged instructions through a bus, and runs the instructions through the debugging kernel to obtain a debugging result of the instructions.

[0068] Referring to Figure 5 When the number of the to-be-debugged instructions is multiple, the debugging kernel runs the to-be-debugged instructions to obtain a debugging result of the to-be-debugged instructions, including steps S501 to S502:

[0069] In step S501, the multiple to-be-debugged instructions are formed into a to-be-debugged program, and the to-be-debugged program is stored in a local memory.

[0070] In step S502, the to-be-debugged program is called from the local memory through a bus and is run to obtain a debugging result of the to-be-debugged program at different stages of the pipeline.

[0071] Reference Figure 6 In one embodiment of this application, the second process further includes the following steps S601 and S602:

[0072] Step S601: Connect the test machine.

[0073] Step S602: Load the instruction to be debugged from the local memory using the test machine and run it to obtain the debugging result of the instruction to be debugged.

[0074] Connect the multi-core digital signal processor to the test machine, and perform instruction testing based on the test machine.

[0075] This method enables single-step testing and cross-debugging of instructions in multi-core digital signal processors (DSPs). In test mode, any kernel can be designated as the test kernel. By loading the built-in test program into memory, detailed testing of all stages of the instruction is performed, quickly locating error states during instruction execution and improving test coverage. Furthermore, it eliminates the need for writing test programs for test equipment and external loading, reducing testing costs and time. In debug mode, the entire stage of a single instruction can be directly obtained for debugging, enabling debugging of individual instructions. Multiple instructions can also be combined into a program for debugging, further improving debug coverage. This method significantly enhances the testing and debugging capabilities of multi-core DSP kernel instructions, reduces the difficulty of subsequent test program development, increases test coverage, and facilitates instruction analysis and judgment during the use of multi-core DSPs.

[0076] For ease of understanding, the following provides a testing and debugging method for multi-core digital signal processors. The multi-core digital signal processor used in this method is a multi-core digital signal processor designed by Hunan Jinxin, and its structure is as follows: Figure 7 The digital signal processor (DSP) features two fixed-point cores and two floating-point cores, all designed based on the Haver bus architecture. The cores support 16-bit and 32-bit instruction modes, executing the DSP's 32-bit instruction set. It acquires data and instructions via a 32-bit data bus, a 32-bit address bus, and a 32-bit instruction bus. Under normal operating conditions, the instruction execution process involves the core's built-in pipeline acquiring data, fetching instructions, decoding, executing, and storing them. The core only executes the instruction set instructions during the execution phase. If a problem occurs in the instruction set, only the execution phase error can be observed, making it impossible to quickly identify the error stage for rapid instruction set analysis and testing. Figure 9 As shown, this method includes the following steps:

[0077] Step S201, when the multi-core digital signal processor is powered on and exits the power-on reset mode, input the test enable signal and a set of serial 32-bit test mode entering password instructions to two GPIO pins of the multi-core digital signal processor. At the same time, after the multi-core digital signal processor acquires the test enable signal within a 128 clock cycle window, the multi-core digital signal processor enters the test mode and executes step S202; when the multi-core digital signal processor is in the test mode, input the debug enable signal to the GPIO pin of the multi-core digital signal processor, and the multi-core digital signal processor enters the debug mode and executes step S203.

[0078] Step S202, the multi-core digital signal processor starts the test kernel and the instruction to be tested, tests the instruction to be tested through the test kernel, obtains the first running state of the whole stage, inputs the first running state into the comparator, inputs the second running state obtained by pre-testing the instruction to be tested once into the comparator, compares the exclusive or relationship between the first running state and the second running state through the comparator, and obtains the test result.

[0079] Reference Figure 8 The test kernel is at least one of two floating point kernels and two fixed point kernels, the test kernel loads and calls the instruction to be tested through the data bus quickly, and executes to obtain the first running state of the instruction in the acquisition, decoding and execution stages, and stores the state in a local register (test dedicated).

[0080] The test kernel can quickly identify the type of the instruction based on a lookup table through the instruction flag code, quickly adapt the second running state of the instruction in the acquisition, decoding and execution stages, extract the first running state from the register; input the first running state and the second running state into the comparator for exclusive or comparison, analyze the execution state of the instruction, and quickly locate the error state of the instruction execution by comparing the execution states of different stages of the instruction (the instruction is decomposed into 32-bit binary data in different stages), thereby quickly locating the specific circuit structure of the kernel executing the instruction, and quickly analyzing and confirming the instruction set.

[0081] The test mode of the present application supports simultaneous instruction set running test of two floating point kernels and two fixed point kernels, different kernels store the data of different stages of the executed instruction into the register (test dedicated), the test kernel determines the type of the instruction through the test executed instruction and the instruction flag bit, and quickly compares and tests the execution state of the instruction of different kernels through the instruction execution data in the register.

[0082] Step S203, without starting the test kernel, connecting the multi-core digital signal processor to the tester for debugging, the tester running to load one or more instructions to be debugged, the execution result of the instructions being output to the boundary scan register, the instruction debugging result being read through the boundary scan result, and the instruction debugging condition being judged. Alternatively, at least one kernel can be used as a debugging kernel, one or more instructions to be debuged being loaded through the data bus, the execution result of the instructions being output to the register (debugging special), and the debugging result of the instructions being obtained.

[0083] The method realizes single-step testing and cross-debugging of instructions of the multi-core digital signal processor. In the test mode, any kernel can be set as a test kernel, a test program built in the memory is loaded by the test kernel to perform detailed testing of the instructions in all stages, the error state during execution of the instructions can be quickly located, the test coverage is improved, the tester program does not need to be written during testing, and the test program does not need to be loaded through external connection, thereby reducing the test cost and test time. In the debugging mode, the debugging instruction state of a single instruction in all stages can be directly obtained, debugging of a single instruction is realized, and debugging of a plurality of instructions to form a program is also realized, thereby improving the debugging coverage. The method greatly improves the testing and debugging capability of the kernel instructions of the multi-core digital signal processor, reduces the difficulty of subsequent test program development, improves the test coverage, and is beneficial to analysis and judgment of the instructions of the multi-core digital signal processor during use.

[0084] The above is a specific description of the preferred implementation of the embodiments of the application, but the embodiments of the application are not limited to the above implementation, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the embodiments of the application, and these equivalent modifications or replacements are all included in the scope defined by the claims of the embodiments of the application.

Claims

1. A method of instruction testing and debugging, characterized by, The instruction test and debugging method for a multi-core digital signal processor comprises: When a test enable signal is received, a test mode is entered and a first flow is executed; when entering the test mode, a debugging enable signal is received, a debugging mode is entered and a second flow is executed; The first flow comprises: calling a to-be-tested instruction from a local memory through a bus, and starting at least one core in a plurality of cores as a test core, so that the test core runs the to-be-tested instruction through a pipeline built in the test core to obtain a first running state of the to-be-tested instruction at different stages of the pipeline; comparing the first running state with a second running state of the to-be-tested instruction at different stages which is tested in advance to obtain a test result of the test core on the to-be-tested instruction, specifically: according to an instruction flag bit of the to-be-tested instruction, searching for the second running state of the to-be-tested instruction at different stages from an instruction lookup table in the local memory; The second running state and the first running state are input into a comparator respectively; The second running state and the first running state are compared through the comparator by performing an exclusive or operation on instruction data bits; When a plurality of test cores test one to-be-tested instruction, one of the test cores runs the to-be-tested instruction through the built-in pipeline to obtain the first running state of the to-be-tested instruction at different stages of the pipeline, and stores the first running state at different stages in a local register; another one of the test cores extracts the first running state from the register and compares the first running state with the second running state; When a plurality of test cores test a plurality of to-be-tested instructions, each test core runs a corresponding to-be-tested instruction to obtain the first running state of the corresponding to-be-tested instruction at different stages of the pipeline and store the first running state in a local register; any one of the test cores extracts the first running state of each to-be-tested instruction from the register and compares each first running state with a corresponding second running state; The second flow comprises: calling a plurality of to-be-debugged instructions from the local memory through a bus, and starting at least one core in a plurality of cores as a debugging core, so that the debugging core runs the plurality of to-be-debugged instructions to obtain a debugging result of the plurality of to-be-debugged instructions.

2. The instruction testing and debugging method of claim 1, wherein, When the number of the plurality of to-be-debugged instructions is more than one, the debugging core runs the plurality of to-be-debugged instructions to obtain the debugging result of the plurality of to-be-debugged instructions, comprising: forming a to-be-debugged program by using the plurality of to-be-debugged instructions, and storing the to-be-debugged program in the local memory; calling the to-be-debugged program from the local memory through the bus and running the to-be-debugged program to obtain a debugging result of the to-be-debugged program at different stages of the pipeline.

3. The method of instruction testing and debugging of claim 2, wherein, The debugging result is obtained by the following way: The first running state of the to-be-debugged instruction at different stages of the pipeline is input to a boundary scan register, and the first running state is output as a debugging result through a built-in boundary scan chain.

4. The instruction testing and debugging method of claim 1, wherein, When the test enabling signal is received, the instruction testing and debugging method further comprises: receiving a test mode entering password instruction; When the password instruction is successfully verified, the test mode is entered.

5. The method of instruction testing and debugging of claim 1, wherein, The second process further comprises: connecting a test machine; loading the to-be-debugged instruction from the local memory and running the to-be-debugged instruction through the test machine to obtain a debugging result of the to-be-debugged instruction.

6. A multi-core digital signal processor, comprising: The multi-core digital signal processor is configured to execute the instruction testing and debugging method according to any one of claims 1 to 5.

7. The multi-core digital signal processor of claim 6, wherein, The plurality of cores comprise a plurality of fixed-point cores and a plurality of floating-point cores.

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