Circuit fault analysis model training method and circuit fault analysis method

Abstract

The application relates to a circuit fault analysis model training method and a circuit fault analysis method. The training method comprises obtaining a circuit fault analysis model to be trained and training data of a circuit fault, the training data comprising sample data and sample labels; the sample data is input into the circuit fault analysis model to be trained, the circuit fault analysis model is used for feature highlighting processing on the sample data, and fault features are obtained; the circuit fault analysis model is used for time sequence feature extraction on the fault features, feature data obtained through the time sequence feature extraction is classified and predicted; a similarity comparison is performed on a classification prediction result and the sample labels; model parameters of the circuit fault analysis model to be trained are updated until a similarity comparison result is not greater than a preset error, and a trained circuit fault analysis model is obtained. The method improves the applicability of the circuit fault analysis model and also improves the accuracy and reliability of a circuit model fault analysis result.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a training method, apparatus, computer equipment, storage medium, and computer program product for a circuit fault analysis model; it also relates to a circuit fault analysis method, apparatus, computer equipment, storage medium, and computer program product. Background Technology

[0002] Electronic circuits refer to circuits composed of electronic devices and related radio components. They include circuits for amplification, oscillation, rectification, detection, modulation, frequency conversion, waveform conversion, and various control circuits; they are widely used in various electronic devices. For example, in the industrial field, industrial operating systems are becoming increasingly large-scale and complex, and electronic circuit systems are the core modules of these systems. Similarly, in the military field, electronic circuits are a core component of modern weaponry, having become essential components in missiles, torpedoes, and various bombs. From aerospace and defense to sectors closely related to people's daily lives such as medicine, transportation, and communications, the integrity and security of the entire system are inextricably linked to electronic circuits; therefore, the reliability and security of electronic circuit systems are of paramount importance.

[0003] Traditional methods for electronic circuit fault analysis often employ time-frequency domain feature analysis, such as Fourier transform, empirical mode decomposition, wavelet analysis, and Hilbert-Huang transform. These methods only perform simple digital feature analysis and calculation of analog output voltage or current quantities. Alternatively, machine vision technology can be used to analyze equipment or component faults with visible defects or anomalies. However, the accuracy of identifying and judging faults in power circuits with weak or complex features or inconspicuous fault phenomena is relatively low, leading to lower reliability of electronic circuit fault analysis results. Summary of the Invention

[0004] Therefore, it is necessary to provide a training method for a circuit fault analysis model that can support high-reliability fault analysis and a circuit fault analysis method with higher reliability, as well as an apparatus, computer device, computer-readable storage medium and computer program product that can implement the corresponding method, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a method for training a circuit fault analysis model. The method includes:

[0006] Obtain the circuit fault analysis model to be trained and the training data of the circuit fault, wherein the training data includes sample data and sample labels;

[0007] The sample data is input into the circuit fault analysis model to be trained, and the circuit fault analysis model performs feature highlighting processing on the sample data to obtain fault features.

[0008] The fault characteristics are extracted using a circuit fault analysis model, and the extracted feature data are then classified and predicted.

[0009] The classification prediction results are compared with the sample labels for similarity.

[0010] Update the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than the preset error, and obtain the trained circuit fault analysis model.

[0011] In one embodiment, updating the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than a preset error, thereby obtaining the trained circuit fault analysis model, includes:

[0012] If the similarity comparison result is greater than the preset error, the model parameters of the circuit fault analysis model are updated by the whale optimization algorithm, and the circuit fault analysis model with updated model parameters is used again as the circuit fault analysis model to be trained, and the step of inputting the sample data into the circuit fault analysis model to be trained is returned.

[0013] If the similarity comparison result is not greater than the preset error, then the trained circuit fault analysis model is obtained.

[0014] In one embodiment, the model parameters of the circuit fault analysis model are updated using the whale optimization algorithm, including:

[0015] Obtain the number of channels in the convolutional layer, the size of the convolutional kernel, the parameters of the pooling layer, and the parameters of the long short-term memory layer in the circuit fault analysis model;

[0016] Based on the number of channels in the convolutional layer, the size of the convolutional kernel, the parameters of the pooling layer, and the parameters of the long short-term memory layer, a whale population for the whale optimization algorithm is constructed.

[0017] A reference individual was generated from the aforementioned whale population;

[0018] The position of the individual whale is updated using the spiral walking model of an individual whale in the whale optimization algorithm;

[0019] The optimal individual is selected based on the distance between the updated whale individual and the reference individual.

[0020] The circuit fault analysis model is updated based on the model parameters corresponding to the optimal individual.

[0021] In one embodiment, updating the position of the individual whale using the spiral walking model of an individual whale in the whale optimization algorithm includes:

[0022] Obtain the preset spiral control parameters in the spiral walking model;

[0023] The position of individual whales is updated using the spiral control parameters.

[0024] In one embodiment, updating the position of the individual whale using the spiral walking model of an individual whale in the whale optimization algorithm includes:

[0025] The encirclement step length of the spiral walking model is determined based on the individual distance between the whale and the reference individual.

[0026] Individual whales are screened based on the encirclement step size, and their positions are updated.

[0027] In one embodiment, the step of inputting the sample data into the circuit fault analysis model to be trained, and performing feature highlighting processing on the sample data to obtain fault features, includes:

[0028] Feature extraction is performed on the sample data to obtain the initial features of the circuit fault;

[0029] The initial features are normalized to obtain the weight matrix;

[0030] The fault features are obtained by multiplying the weight tensor in the weight matrix with the initial features corresponding to the weight tensor.

[0031] In one embodiment, the step of multiplying the weight tensor in the weight matrix with the initial feature corresponding to the weight tensor to obtain the fault features includes:

[0032] Obtain the weight tensor, the preset unit tensor, and the preset pruning parameters from the weight matrix;

[0033] The weight tensor is reversed using the unit tensor to obtain the reverse tensor;

[0034] The inverse tensor and the weight tensor are used as the initial feature inputs to the activation function in the circuit fault analysis model;

[0035] The activation function's computation results are pruned using the pruning parameters to obtain fault characteristics.

[0036] Secondly, this application also provides a circuit fault analysis method. The method includes:

[0037] Acquire the operating data generated during circuit operation, as well as the circuit fault analysis model;

[0038] The operating data is input into the circuit fault analysis model for fault analysis, and the circuit fault analysis results are output.

[0039] The circuit fault analysis model is obtained by training any one of the circuit fault analysis model training methods in the first aspect.

[0040] Thirdly, this application also provides a training device for a circuit fault analysis model. The device includes:

[0041] The data acquisition module acquires the circuit fault analysis model to be trained and the training data of the circuit fault, wherein the training data includes sample data and sample labels.

[0042] The feature highlighting module inputs the sample data into the circuit fault analysis model to be trained, and performs feature highlighting processing on the sample data through the circuit fault analysis model to obtain fault features;

[0043] The timing processing module extracts timing features from the fault features using a circuit fault analysis model, and then classifies and predicts the feature data obtained from the timing feature extraction.

[0044] The error analysis module compares the classification prediction results with the sample labels for similarity.

[0045] The model optimization module updates the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than a preset error, thereby obtaining the trained circuit fault analysis model.

[0046] Fourthly, this application also provides a circuit fault analysis device. The device includes:

[0047] The model acquisition module acquires the runtime data generated during circuit operation, as well as the circuit fault analysis model.

[0048] The fault analysis module inputs the operating data into the circuit fault analysis model to perform fault analysis and outputs the circuit fault analysis results.

[0049] The circuit fault analysis model is obtained by training any of the circuit fault analysis model training methods in the first aspect.

[0050] Fifthly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0051] Obtain the circuit fault analysis model to be trained and the training data of the circuit fault, wherein the training data includes sample data and sample labels;

[0052] The sample data is input into the circuit fault analysis model to be trained, and the circuit fault analysis model performs feature highlighting processing on the sample data to obtain fault features.

[0053] The fault characteristics are extracted using a circuit fault analysis model, and the extracted feature data are then classified and predicted.

[0054] The classification prediction results are compared with the sample labels for similarity.

[0055] Update the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than the preset error, and obtain the trained circuit fault analysis model.

[0056] Sixthly, this application also provides a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0057] Acquire the operating data generated during circuit operation, as well as the circuit fault analysis model;

[0058] The operating data is input into the circuit fault analysis model for fault analysis, and the circuit fault analysis results are output.

[0059] The circuit fault analysis model is obtained by training any of the circuit fault analysis model training methods in the first aspect.

[0060] Seventhly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the aforementioned training method for the circuit fault analysis model or the circuit fault analysis method.

[0061] Eighthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the aforementioned training method for the circuit fault analysis model or the circuit fault analysis method.

[0062] This application provides a training method, apparatus, computer device, storage medium, and program product for a circuit fault analysis model. The training method highlights fault features in circuit fault sample data, enabling the circuit fault analysis model to better identify these features and achieve accurate circuit fault analysis. Furthermore, the circuit fault analysis model extracts temporal features from the highlighted fault features and then performs fault classification prediction. This temporal feature extraction adapts to different sample data distributions, improving the applicability of the circuit fault analysis model and enhancing the accuracy and reliability of fault analysis results in scenarios with weak, complex features or unclear fault phenomena.

[0063] In addition, this application also provides a circuit fault analysis method, apparatus, computer equipment, storage medium, and program product. Since the circuit fault analysis model used in the circuit fault analysis method is obtained using the aforementioned circuit fault analysis model training method, the method can more accurately analyze and diagnose faults existing in the circuit, improving the reliability of the circuit fault analysis results. Attached Figure Description

[0064] Figure 1 This is a diagram illustrating the application environment of a training method for a circuit fault analysis model in one embodiment.

[0065] Figure 2 This is a flowchart illustrating the training method for a circuit fault analysis model in one embodiment;

[0066] Figure 3 This is a block diagram of the reverse attention network structure in one embodiment;

[0067] Figure 4 This is a block diagram of a long short-term memory network structure in one embodiment;

[0068] Figure 5 This is a flowchart of the sub-steps for optimizing model parameters using the whale optimization algorithm in one embodiment;

[0069] Figure 6 This is a flowchart illustrating the training method for a circuit fault analysis model in another embodiment;

[0070] Figure 7 This is a flowchart illustrating a circuit fault analysis method in one embodiment;

[0071] Figure 8 This is a flowchart illustrating the process of obtaining circuit fault analysis results in one embodiment;

[0072] Figure 9 This is a structural block diagram of a training device for a circuit fault analysis model in one embodiment;

[0073] Figure 10 This is a structural block diagram of a circuit fault analysis device in one embodiment;

[0074] Figure 11 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0076] Before describing specific embodiments, the abbreviations and key terms used in this specification are defined and described as follows:

[0077] Whale optimization algorithm (WOA): The Whale optimization algorithm is a swarm intelligence optimization algorithm proposed by imitating the hunting methods of humpback whales.

[0078] Reverse attention mechanism (RAM) is an improved attention mechanism inspired by how the human eye processes information. It highlights important features and suppresses secondary features to highlight fault features.

[0079] Long Short-Term Memory (LSTM) networks are a type of recurrent neural network specifically designed to address the long-term dependency problem inherent in general RNNs (Recurrent Neural Networks). All RNNs have a chain-like structure of repeating neural network modules. In a standard RNN, this repeating structure has only a very simple structure, such as a single tanh layer.

[0080] In critical fields such as aerospace, defense, medical, and transportation, the integrity and security of integrated systems are inextricably linked to electronic circuits. Therefore, the reliability and security of electronic circuit systems are paramount. Traditional technical solutions have proposed circuit fault diagnosis methods based on one-dimensional convolutional neural networks and corresponding network model design methods. These methods use multi-dimensional current data of the circuit as the output of the convolutional neural network, and the network model highlights fault features in the current data, enabling the diagnostic model to better identify fault characteristics and achieve accurate circuit fault diagnosis. However, the feature highlighting methods proposed in traditional solutions require large-scale data support, and the training of the diagnostic model also requires large-scale data support. This makes it difficult to guarantee the diagnostic accuracy of the fault diagnosis model under complex fault modes, imbalanced samples, small samples, or other complex conditions.

[0081] The training method for the circuit fault analysis model provided in this application embodiment can be applied to, for example... Figure 1In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104 or placed in the cloud or on another network server. In response to the model training command sent from terminal 102 to server 104, server 104 first retrieves training data on circuit faults in batches from its data storage system. This training data is obtained after detailed recording and necessary data cleaning of fault conditions during the circuit's lifecycle. The training data includes sample data and sample labels, which can be formed by simultaneously marking fault types during the recording and storage of fault conditions. Server 104 can retrieve the circuit fault analysis model to be trained stored in the data storage system, or it can obtain the model through a temporary setup. Server 104 inputs the sample data from the training data into the circuit fault analysis model to be trained, highlighting important feature information in the sample data through the model's back attention mechanism to obtain the fault features after feature highlighting. Furthermore, server 104 extracts temporal features of fault characteristics through the Long Short-Term Memory (LSTM) network in the circuit fault analysis model. Then, it classifies and predicts fault types using fully connected layers in the circuit fault analysis model, and compares the predicted circuit fault types with the sample labels in the training data for similarity. Server 104 determines whether the similarity comparison result is within acceptable test error; if it determines that the similarity comparison result is greater than the acceptable test error, it optimizes the model parameters of the circuit fault analysis model using the whale optimization algorithm, obtaining a parameter-optimized circuit fault analysis model. The parameter-optimized circuit fault analysis model can be stored in server 104's data storage system for subsequent retrieval. In addition, in this implementation environment, server 104 can also respond to fault analysis commands from terminal 102 to perform fault analysis and diagnosis of the circuit. Server 104 can directly call the trained circuit fault analysis model from the data storage system and input the circuit operation data uploaded in real time by terminal 102 into the circuit fault analysis model, perform fault analysis through the circuit fault analysis model, and output the circuit fault analysis results. The terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, and smart in-vehicle systems. Portable wearable devices can include smartwatches, smart bracelets, and head-mounted devices. The server 104 can be implemented using a standalone server or a server cluster consisting of multiple servers.

[0082] In one embodiment, such as Figure 2As shown, a training method for a circuit fault analysis model is provided, which can be applied to... Figure 1 Taking server 104 as an example, the following steps are included:

[0083] Step 202: Obtain the circuit fault analysis model to be trained and the training data of the circuit fault. The training data includes sample data and sample labels.

[0084] The circuit fault analysis model to be trained can be a model obtained by calling a pre-stored model in the storage space and performing initialization processing, or it can be a model obtained by temporary construction. The training data in this embodiment is data obtained after detailed recording and necessary data cleaning of fault conditions during the circuit's lifecycle. This training data includes sample data and sample labels, which can be obtained by simultaneously marking fault types during the recording and storage of fault conditions.

[0085] For example, in this embodiment, an initial fault diagnosis model is constructed by combining a one-dimensional convolutional neural network (1DCNN), RAM blocks, and an LSTM network; the model mainly includes several RAM blocks, LSTM layers, global average pooling layers, and fully connected layers. Figure 3 As shown, the RAM block includes input / output layers, convolutional layers, batch normalization layers, pooling layers, softmax layers, inverse layers, and pruning layers. The pooling layers are connected to both the softmax and inverse layers to perform inverse product operations on the features. The feature signals output from the RAM block are input into the LSTM layer for temporal feature processing; finally, fault classification prediction is performed by global average pooling layers and fully connected layers.

[0086] Step 204: Input the sample data into the circuit fault analysis model to be trained, and use the circuit fault analysis model to perform feature highlighting processing on the sample data to obtain fault features.

[0087] Feature highlighting refers to the process of emphasizing important features and suppressing secondary features through a reverse attention mechanism, thereby highlighting fault features. Fault features are data content contained in the sample data of the training data that can describe the attributes and categories of faults, and this data content can be in vector or tensor format, etc.

[0088] For example, in an embodiment, the sample data of the training data is input into the reverse attention mechanism RAM block in the circuit fault analysis model to be trained. First, it is processed by the activation function through the convolutional layer, and the result of the calculation is transformed to obtain the corresponding weight. The obtained weight value is then multiplied with the input sample data to obtain the fault features, thereby achieving the purpose of highlighting the important features in the sample data.

[0089] Step 206: Extract time-series features from the fault characteristics using the circuit fault analysis model, and then classify and predict the feature data obtained from the time-series feature extraction.

[0090] Among these, temporal features are the characteristic information of circuit fault sample data in the time dimension. In this embodiment, the extraction process of temporal features is implemented through a Long Short-Term Memory (LSTM) network. Since the input sample data during model training usually does not have a linear relationship, the LTM network can achieve nonlinear modeling through the nonlinear transformation of the neural network, thereby better extracting temporal features. In this embodiment, the purpose of classification prediction is to classify the fault types or fault attributes represented by different sample data, thereby enabling fault identification and confirmation.

[0091] For example, since the LSTM structure can overcome the vanishing and exploding gradient problems in models, the embodiment uses an LSTM structure to extract temporal features. The LSTM structure introduces gating mechanisms to add or remove cell states. Figure 4 As shown, the output of the σ layer in the LSTM structure is a value between 0 and 1, representing the percentage of information that the σ layer can pass through; 0 indicates that none of the information can pass through, and 1 indicates that all of it can pass through. Specifically, the LSTM controls the cell state through three gate structures, called the forget gate, the input gate, and the output gate. The forget gate f t By checking h t-1 and x t The information is used to output a vector between 0 and 1, where the 0-1 values ​​represent the cell state C. t-1 The degree to which information is retained or discarded. 0 indicates no retention, and 1 indicates retention of all information. The specific calculation formula for temporal feature extraction in the LSTM structure is as follows:

[0092] f t =σ(w f [h t-1 x t ]+b f )

[0093] i t =σ(w i [h t-1 x t ]+bi )

[0094]

[0095] c t =f t c t-1 +i t c t

[0096] o t =σ(w o [h t-1 x t ]+b o )

[0097] h t =o t *tanh(c t )

[0098] Where, x t Let represent the input at time t, ω represent the weight matrix, and b represent the bias matrix. Let c represent the candidate vector at time t. t h represents the update value at time t. t h t-1 This represents all outputs of the model at time points t and t-1. Input gate i t Decision h t-1 and x t The information is updated, and then h is used. t-1 and x t New candidate cell information C is obtained through a Tanh layer. t A portion of the information in the old cells is transmitted through the forget gate f. t Select "Forgot", then enter the option to add candidate cell information (C). t Part of it receives new cellular information C t Output gate o t It controls how much memory information will be used in the next stage of updates.

[0099] After extracting temporal features using an LSTM structure, the temporal features are subjected to global average pooling, and the pooling result is input into a fully connected layer, which then performs fault classification.

[0100] Step 208: Compare the classification prediction results with the sample labels for similarity.

[0101] Similarity comparison is the process of calculating the similarity distance between circuit fault types or attribute information of circuit faults in the classification prediction results.

[0102] For example, in this embodiment, the circuit fault analysis model performs fault classification prediction based on the input sample data, and the obtained fault type is compared with the similarity of the corresponding sample label of the training data obtained in step 202. For example, in this embodiment, the Euclidean distance between the classification prediction result and the sample label can be calculated, and the distance between the two can be described by Euclidean.

[0103] Step 210: Update the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than the preset error, and obtain the trained circuit fault analysis model.

[0104] The preset error refers to the acceptable test error that is set in advance before model training.

[0105] For example, in this embodiment, the circuit fault type predicted by the circuit fault analysis model based on sample data is calculated using the Euclidean distance formula. After calculating the similarity value (distance) with the sample labels in the original training data, this similarity value is compared with the acceptable test error set before model training. For example, the acceptable test error is 0.15, meaning that the similarity value between the classification prediction result of the circuit fault analysis model and the sample label needs to be greater than 0.85 for the model to be considered to have been trained to the optimal parameters. When the error of the calculated similarity value is greater than 0.15, that is, the similarity value is less than 0.85, the model parameters need to be iteratively optimized. The circuit fault analysis model with optimized parameters is continuously updated based on the initial training data to update the classification prediction result and the similarity value with the sample label. This continues until the similarity value is no greater than the acceptable test error, at which point the optimal model parameters are considered to have been obtained, and the circuit fault analysis model is updated based on the optimal model parameters to complete the model training process. For optimizing model parameters, in this embodiment, the model parameters that need optimization can be extracted, and their corresponding objective functions can be constructed. The optimal model parameters are obtained by finding the optimal solution to the objective function. In this embodiment, the process of finding the optimal solution to the objective function of the model parameters can be performed using logistic regression and population iterative algorithms.

[0106] The training method of the aforementioned circuit fault analysis model highlights the fault features in the circuit fault sample data, enabling the circuit fault analysis model to better identify fault features and achieve the goal of accurate circuit fault analysis. Furthermore, the circuit fault analysis model extracts time-series features from the highlighted fault features and then performs fault classification prediction. Through time-series feature extraction, it can adapt to different sample data distributions, improving the applicability of the fault analysis model and enhancing the accuracy and reliability of the model's fault analysis results in scenarios with weak, complex features or unclear fault phenomena.

[0107] Based on DCNN, RAM, and LSTM, a basic fault diagnosis model is constructed. The training method in this embodiment can also use WOA to adaptively select the parameters of the aforementioned diagnostic model, choosing the most suitable model parameters for fault diagnosis of the circuit. In one embodiment, such as... Figure 5 As shown, the process of updating the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than the preset error, thus obtaining the trained circuit fault analysis model, may include:

[0108] Step 212: If the similarity comparison result is greater than the preset error, the model parameters of the circuit fault analysis model are updated using the whale optimization algorithm. The circuit fault analysis model with updated model parameters is then used as the circuit fault analysis model to be trained again. The process returns to the step of inputting sample data into the circuit fault analysis model to be trained.

[0109] Among them, the whale optimization algorithm is a swarm intelligence optimization algorithm proposed by imitating the hunting methods of humpback whales. Its mathematical model mainly includes three parts: wandering to search for prey, shrinking to surround prey, and spiraling to hunt prey.

[0110] For example, in the process of optimizing the circuit fault analysis model using the Whale Optimization Algorithm (WOA) in the embodiment, firstly, an initial population in WOA is constructed based on the model parameters of the fault analysis model at the current stage, that is, the model parameters are represented as the position information of individual whales. Then, based on the global search of WOA, an individual is randomly selected from the initial population as a reference individual, that is, the whale individual in the best position, and new individuals are continuously generated to update the initial population. The process can simulate the spiral predation behavior of whales during the hunting process. At the algorithm level, the aforementioned spiral predation behavior is expressed by two mathematical models: one is a shrinking encirclement, which is to move the whale individual in the current position closer to the whale individual in the current best position; the other is a spiral position update, which, according to the preset long parameters in WOA, the model whale individual moves closer to the whale individual in the current best position in a spiral manner. After updating the positions of individual whales to obtain a new whale pod, based on the idea of ​​whales contracting and surrounding their prey, any given whale might not approach the whale in the optimal position, but instead randomly selects a whale from the current pod to approach. This concept of contracting and surrounding for prey, while potentially causing individual whales to deviate from their target prey, enhances the overall search capabilities of the whale pod.

[0111] Step 214: If the similarity comparison result is not greater than the preset error, the trained circuit fault analysis model is obtained.

[0112] For example, in this embodiment, after obtaining the current optimal whale individual through WOA, the corresponding optimized model parameters are obtained by converting the location information of the current optimal whale individual. Based on these optimized model parameters, the circuit fault analysis model is updated, and a new prediction analysis is performed based on the initially acquired training data. The updated classification prediction result is also compared with the sample labels in the training data for similarity. When the similarity comparison result is less than or equal to the acceptable test error, the process of iteratively updating the model parameters through WOA is stopped, and the currently obtained model parameters are taken as the optimal model parameters. The circuit fault analysis model loaded based on the final model parameters is the trained model. If the current similarity comparison result is still greater than the acceptable test error, iterative updates to the model parameters through WOA are required.

[0113] First, a basic fault diagnosis model is constructed using 1DCNN, RAM, and LSTM. Then, WOA is used to adaptively select the parameters of the above diagnostic model, choosing the most suitable model parameters for circuit fault diagnosis, which enables high-precision and robust identification and judgment of circuit faults.

[0114] In one embodiment, the process of updating the model parameters of the circuit fault analysis model using the whale optimization algorithm in the training method may include the following steps:

[0115] Step 1: Obtain the number of convolutional layer channels, convolutional kernel size, pooling layer parameters, and long short-term memory layer parameters in the circuit fault analysis model.

[0116] Step 2: Based on the number of channels in the convolutional layer, the size of the convolutional kernel, the parameters of the pooling layer, and the parameters of the long short-term memory layer, a whale population for the whale optimization algorithm is constructed.

[0117] Step 3: Generate reference individuals from the whale population.

[0118] Step four: Update the position of individual whales using the spiral walking model of individual whales in the whale optimization algorithm.

[0119] Step 5: Based on the distance between the updated whale individual and the reference individual, select the optimal individual.

[0120] Step 6: Update the parameters of the circuit fault analysis model based on the model parameters corresponding to the optimal individual.

[0121] For example, in this embodiment, the purpose of WOA is to optimize the number of channels in the convolutional layers, the kernel size, the pooling layer parameters, and the LSTM layer parameters in the overall convolutional neural network. Through iterative training, it seeks the optimal combination of channel parameters to achieve the best performance of the diagnostic model. Therefore, in the process of updating the model parameters in this embodiment, an initial population needs to be constructed first. After obtaining the initial population, during the model parameter update process in WOA, the search layer of the population is controlled by a pre-set control parameter A; that is, when |A|>1, WOA performs a global search and randomly selects a whale individual as the optimal reference individual. The other individuals in the population are generated in the manner described by the following calculation formula:

[0122]

[0123] A = 2ar - a

[0124] C = 2r

[0125]

[0126]

[0127] Where t is the current iteration number; t max The maximum number of iterations is r; r is a random number between [0, 1]. For randomly selected search individuals; X t denoted as an individual in the t-th generation population; D represents the encirclement step size; A represents the distance between the generated individual and the reference individual.

[0128] Next, the process of whales spiraling to hunt prey is simulated, iteratively updating the positional information of individual whales in the population. This updating involves both shrinking encirclement and spiral position updates. The stage of finding the optimal whale individual is similar to the shrinking encirclement process; however, in the shrinking encirclement stage, whales no longer randomly select individuals for position updates, but instead select the currently optimal individual, implementing an encirclement strategy to achieve the optimal solution for the population. The formula for calculating the position update of prey during shrinking encirclement is as follows:

[0129]

[0130]

[0131] in, To find the position of the optimal whale individual when searching up to the t-th generation of the population, D bestThe encirclement step size for the optimal individual whale. This simulates the behavior of shrinking the encirclement of prey by surrounding the optimal individual whale in the population. After obtaining the optimal individual whale and its corresponding location information, the model parameters of the optimized circuit fault analysis model are derived based on this location information.

[0132] In one embodiment, the process of updating the position of an individual whale using the spiral walking model of an individual whale in the whale optimization algorithm during training may include the following steps:

[0133] Step 1: Obtain the preset spiral control parameters in the spiral walking model.

[0134] Step two: Update the position of individual whales by controlling the spiral parameters.

[0135] For example, in this embodiment, when updating the position of individual whales in a whale population, the whales can move closer to the whale with the best current position in a spiral manner. The specific walking model is as follows:

[0136]

[0137] Where b is a constant that controls the shape of the spiral; l is a random variable in the range [0, 1].

[0138] In one embodiment, the training method, which updates the position of an individual whale using the spiral walking model of an individual whale in the whale optimization algorithm, may further include the following steps:

[0139] Step 1: Determine the encirclement step length of the spiral walking model based on the individual distance between the whale and the reference individual.

[0140] Step 2: Filter individual whales based on the encirclement step length, and update the positions of the filtered whales.

[0141] For example, in this embodiment, WOA simulates the process of whale shrinking and encircling, and its mathematical model is consistent with the mathematical model for obtaining the optimal individual whale. The difference lies in the range of values ​​for parameter A. Since shrinking and encircling means bringing the individual whale at the current position closer to the individual whale at the current optimal position, the range of values ​​for A is adjusted to [-1, 1], while other formula contents remain unchanged.

[0142] Since the whale's hunting behavior and spiral contraction occur simultaneously, assuming both have a 50% probability, the mathematical model for spiral predation in this embodiment is as follows:

[0143]

[0144] In one embodiment, the training method involves inputting sample data into the circuit fault analysis model to be trained, and performing feature highlighting processing on the sample data to obtain fault features. This process includes the following steps:

[0145] Step 1: Extract features from the sample data to obtain the initial features of the circuit fault.

[0146] Step 2: Normalize the initial features to obtain the weight matrix.

[0147] Step 3: Multiply the weight tensor in the weight matrix with the initial feature corresponding to the weight tensor to obtain the fault features.

[0148] When observing things, humans typically focus on information of high importance first, ignoring less important information. This reduces the size of the target area requiring attention and improves the efficiency of processing information in that area. Therefore, an attention mechanism can be introduced in this embodiment to highlight features in the sample data. For example, the attention mechanism mimics how humans process information, proactively increasing attention to important information and indirectly reducing attention to other information. The attention mechanism compresses all feature information into the range [0, 1] using the Softmax function to form a weight matrix. Then, the weight tensor is multiplied by the original feature information tensor to highlight important features within the feature tensor.

[0149] However, attention mechanisms can only highlight important features in sample data, without processing secondary features. When the circuit fault analysis model extracts features, secondary features may still have a large weight, affecting model performance. Therefore, to maximize the attention given to important features, a reverse attention amplification mechanism based on attention is proposed, which highlights important features while suppressing secondary features. In one embodiment, the process of multiplying the weight tensor in the weight matrix with the initial features corresponding to the weight tensor to obtain fault features during the training step may include the following steps:

[0150] Step 1: Obtain the weight tensor, the preset unit tensor, and the preset pruning parameters from the weight matrix.

[0151] Step two: Reverse the weight tensor using the unit tensor to obtain the reverse tensor.

[0152] Step 3: Input the initial features corresponding to the inverse tensor and the weight tensor into the activation function of the circuit fault analysis model.

[0153] Step four: Prune the activation function's computation results using pruning parameters to obtain fault characteristics.

[0154] For example, in this embodiment, the input feature tensor is first roughly extracted using convolution operations. Then, the feature tensor is transformed into a weighted tensor using the Softmax function. Next, the weighted tensor is reversed using a unit tensor, which suppresses the originally important features. Then, an optimizable pruning parameter is set to reduce the original prominent features to negative values, and then the ReLU activation function is used to make them directly become 0. At this point, ideally, the original important features become 0, and the original minor features become a small positive number. Then, 1 is subtracted from the currently retained feature tensor, and the original important features are further highlighted. A hyperparameter is then added to further amplify the current feature matrix.

[0155] Refer to the instruction manual. Figure 6 Taking the WOA-RAM-LSTM model architecture as an example, the training process of the circuit fault analysis model in the embodiment is described in complete and detailed manner as follows:

[0156] This embodiment constructs a diagnostic model using 1DCNN, RAM, and LSTM, and utilizes WOA to select model parameters. First, based on the network architecture of 1DCNN, RAM, and LSTM, a circuit fault analysis model to be trained is constructed. The original fault signal, after pre-cleaning and necessary preprocessing, is obtained. When the original fault signal is input into the circuit fault analysis model, the RAM block in the model highlights important features and suppresses secondary features. This operation improves the model's feature extraction capability, ultimately enhancing its diagnostic performance and noise resistance. Second, the highlighted feature signal is input into the LSTM for temporal feature extraction. Finally, a fully connected layer performs fault classification. Regarding the optimization process of the circuit fault analysis model, this embodiment uses WOA to select diagnostic model parameters, optimizing the overall model structure as much as possible, thereby improving the model's diagnostic performance.

[0157] In one embodiment, this application also provides a circuit fault analysis method. For example... Figure 7 As shown, this method is applied to Figure 1 Taking server 104 as an example, the following steps are included:

[0158] Step 702: Obtain the running data generated during circuit operation and the circuit fault analysis model.

[0159] Step 704: Input the running data into the circuit fault analysis model to perform fault analysis, and output the circuit fault analysis results.

[0160] The circuit fault analysis model is obtained through the aforementioned training method for the circuit fault analysis model.

[0161] For example, in this embodiment, operational data from the electronic circuit can be collected in real time, and after cleaning, organizing, and formatting the data, it can be uploaded to a server. Figure 8 As shown, the server is equipped with a pre-trained circuit fault analysis model, and the received operating data is input into the circuit fault analysis model. The model predicts the possible faults in the current operating state of the electronic circuit, and the electronic circuit is maintained or repaired based on the prediction results.

[0162] Since the circuit fault analysis model used in the embodiment is obtained by the above-mentioned circuit fault analysis model training method, the method can more accurately analyze and diagnose the faults existing in the circuit, thus improving the reliability of the circuit fault analysis results.

[0163] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0164] Based on the same inventive concept, this application also provides a training apparatus for a circuit fault analysis model to implement the training method for the circuit fault analysis model described above. For example... Figure 9 As shown, the training device 900 for the circuit fault analysis model includes: a data acquisition module 901, a feature highlighting module 902, a timing processing module 903, an error analysis module 904, and a model optimization module 905, wherein:

[0165] The data acquisition module 901 acquires the circuit fault analysis model to be trained and the training data of the circuit fault. The training data includes sample data and sample labels.

[0166] The feature highlighting module 902 inputs sample data into the circuit fault analysis model to be trained, and performs feature highlighting processing on the sample data through the circuit fault analysis model to obtain fault features;

[0167] The timing processing module 903 extracts timing features from fault characteristics through a circuit fault analysis model and classifies and predicts the feature data obtained from the timing feature extraction.

[0168] Error analysis module 904 compares the classification prediction results with the sample labels for similarity.

[0169] The model optimization module 905 updates the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than the preset error, thus obtaining the trained circuit fault analysis model.

[0170] Specifically, in this embodiment, the data acquisition module 901 first acquires training data of circuit faults in batches from its data storage system, and retrieves the circuit fault analysis model to be trained stored in the data storage system, or can obtain the circuit fault analysis model to be trained through temporary construction. The feature highlighting module 902 inputs sample data from the training data into the circuit fault analysis model to be trained, and highlights important feature information in the sample data through the reverse attention mechanism in the model to obtain the fault features after feature highlighting. The time series processing module 903 extracts time series features of the fault features through the long short-term memory network in the circuit fault analysis model. The error analysis module 904 classifies and predicts the fault type, and compares the similarity of the circuit fault type obtained by classification and prediction with the sample labels in the training data. The model optimization module 905 determines whether the similarity comparison result is within the acceptable test error; after determining that the similarity comparison result is greater than the acceptable test error, it uses the whale optimization algorithm to optimize the model parameters of the circuit fault analysis model to obtain the parameter-optimized circuit fault analysis model.

[0171] In one embodiment, if the similarity comparison result is greater than a preset error, the model optimization module 905 can update the model parameters of the circuit fault analysis model through the whale optimization algorithm, and use the circuit fault analysis model with updated model parameters as the circuit fault analysis model to be trained again, and return to input the sample data to the feature highlighting module 902; if the similarity comparison result is not greater than the preset error, the trained circuit fault analysis model is obtained.

[0172] In one embodiment, the model optimization module 905 can obtain the number of convolutional layer channels, convolutional kernel size, pooling layer parameters, and long short-term memory layer parameters in the circuit fault analysis model; construct a whale population for the whale optimization algorithm based on the number of convolutional layer channels, convolutional kernel size, pooling layer parameters, and long short-term memory layer parameters; generate reference individuals from the whale population; update the positions of the whale individuals using the spiral walking model of the whale individuals in the whale optimization algorithm; select the optimal individual based on the distance between the updated whale individual and the reference individual; and update the parameters of the circuit fault analysis model based on the model parameters corresponding to the optimal individual.

[0173] In one embodiment, the model optimization module 905 can obtain preset spiral control parameters in the spiral walking model; and update the position of the individual whale using the spiral control parameters.

[0174] In one embodiment, the model optimization module 905 can determine the encirclement step size of the spiral walking model based on the individual distance between the individual whale and the reference individual; filter the individual whales based on the encirclement step size; and update the position of the individual whales obtained after filtering.

[0175] In one embodiment, the feature highlighting module 902 can extract features from the sample data to obtain the initial features of the circuit fault; normalize the initial features to obtain the weight matrix; and multiply the weight tensors in the weight matrix with the initial features corresponding to the weight tensors to obtain the fault features.

[0176] In one embodiment, the feature highlighting module 902 obtains the weight tensor, the preset unit tensor, and the preset pruning parameters in the weight matrix; it reverses the weight tensor using the unit tensor to obtain the reverse tensor; it inputs the initial features corresponding to the reverse tensor and the weight tensor into the activation function in the circuit fault analysis model; and it prunes the result of the activation function using the pruning parameters to obtain the fault features.

[0177] Each module in the training device for the aforementioned circuit fault analysis model can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0178] Based on the same inventive concept, embodiments of this application also provide a circuit fault analysis apparatus for implementing the circuit fault analysis method described above. For example... Figure 10 As shown, the circuit fault analysis device 110 includes a model acquisition module 111 and a fault analysis module 112.

[0179] The model acquisition module 111 acquires the running data generated during circuit operation and the circuit fault analysis model.

[0180] The fault analysis module 112 takes the running data into the circuit fault analysis model, performs fault analysis, and outputs the circuit fault analysis results.

[0181] The circuit fault analysis model is trained using the training method of any of the aforementioned circuit fault analysis models, which will not be elaborated here.

[0182] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 11 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores circuit fault data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a training method for a circuit fault analysis model.

[0183] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0184] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0185] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0186] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0187] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0188] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0189] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A training method for a circuit fault analysis model, characterized in that, The method includes: Obtain the circuit fault analysis model to be trained and the training data of the circuit fault, wherein the training data includes sample data and sample labels; The sample data is input into the circuit fault analysis model to be trained, and the circuit fault analysis model performs feature highlighting processing on the sample data to obtain fault features. The feature highlighting processing is based on the reverse attention mechanism. The fault characteristics are extracted using a circuit fault analysis model, and the extracted feature data are then classified and predicted. The classification prediction results are compared with the sample labels for similarity. Update the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than the preset error, and obtain the trained circuit fault analysis model. The step of inputting the sample data into the circuit fault analysis model to be trained, and performing feature highlighting processing on the sample data to obtain fault features includes: Feature extraction is performed on the sample data to obtain the initial features of the circuit fault; The initial features are normalized to obtain the weight matrix; Obtain the weight tensor, the preset unit tensor, and the preset pruning parameters from the weight matrix; The weight tensor is reversed using the unit tensor to obtain the reverse tensor; The inverse tensor and the weight tensor are used as the initial feature inputs to the activation function in the circuit fault analysis model; The activation function's computation results are pruned using the pruning parameters to obtain fault characteristics.

2. The method according to claim 1, characterized in that, The process of updating the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than a preset error, thereby obtaining the trained circuit fault analysis model, includes: If the similarity comparison result is greater than the preset error, the model parameters of the circuit fault analysis model are updated by the whale optimization algorithm, and the circuit fault analysis model with updated model parameters is used again as the circuit fault analysis model to be trained, and the step of inputting the sample data into the circuit fault analysis model to be trained is returned. If the similarity comparison result is not greater than the preset error, then the trained circuit fault analysis model is obtained.

3. The method according to claim 2, characterized in that, Updating the model parameters of the circuit fault analysis model using the whale optimization algorithm includes: Obtain the number of channels in the convolutional layer, the size of the convolutional kernel, the parameters of the pooling layer, and the parameters of the long short-term memory layer in the circuit fault analysis model; Based on the number of channels in the convolutional layer, the size of the convolutional kernel, the parameters of the pooling layer, and the parameters of the long short-term memory layer, a whale population for the whale optimization algorithm is constructed. A reference individual was generated from the aforementioned whale population; The position of the individual whale is updated using the spiral walking model of an individual whale in the whale optimization algorithm; The optimal individual is selected based on the distance between the updated whale individual and the reference individual. The circuit fault analysis model is updated based on the model parameters corresponding to the optimal individual.

4. The method according to claim 3, characterized in that, The step of updating the position of the individual whale using the spiral walking model of an individual whale in the whale optimization algorithm includes: Obtain the preset spiral control parameters in the spiral walking model; The position of individual whales is updated using the spiral control parameters.

5. The method according to claim 3, characterized in that, The step of updating the position of an individual whale using the spiral walking model of an individual whale in the whale optimization algorithm includes: The encirclement step length of the spiral walking model is determined based on the individual distance between the whale and the reference individual. Individual whales are screened based on the encirclement step size, and their positions are updated.

6. A circuit fault analysis method, characterized in that, The method includes: Acquire the operating data generated during circuit operation, as well as the circuit fault analysis model; The operating data is input into the circuit fault analysis model for fault analysis, and the circuit fault analysis results are output. The circuit fault analysis model is trained using the training method for the circuit fault analysis model as described in any one of claims 1 to 5.

7. A training device for a circuit fault analysis model, characterized in that, The device includes: The data acquisition module acquires the circuit fault analysis model to be trained and the training data of the circuit fault, wherein the training data includes sample data and sample labels. The feature highlighting module inputs the sample data into the circuit fault analysis model to be trained, and performs feature highlighting processing on the sample data through the circuit fault analysis model to obtain fault features. The feature highlighting processing is based on the reverse attention mechanism. The timing processing module extracts timing features from the fault features using a circuit fault analysis model, and then classifies and predicts the feature data obtained from the timing feature extraction. The error analysis module compares the classification prediction results with the sample labels for similarity. The model optimization module updates the model parameters of the circuit fault analysis model to be trained until the similarity comparison result is no greater than the preset error, thereby obtaining the trained circuit fault analysis model. The feature highlighting module extracts features from the sample data to obtain initial features of the circuit fault; normalizes the initial features to obtain a weight matrix; obtains the weight tensor, a preset unit tensor, and preset pruning parameters from the weight matrix; reverses the weight tensor using the unit tensor to obtain a reverse tensor; inputs the initial features corresponding to the reverse tensor and the weight tensor into the activation function of the circuit fault analysis model; and prunes the result of the activation function using the pruning parameters to obtain the fault features.

8. The apparatus according to claim 7, characterized in that, If the similarity comparison result is greater than the preset error, the model optimization module updates the model parameters of the circuit fault analysis model through the whale optimization algorithm, and uses the circuit fault analysis model with updated model parameters as the circuit fault analysis model to be trained again, and returns to input the sample data into the feature highlighting module. If the similarity comparison result is not greater than the preset error, then the trained circuit fault analysis model is obtained.

9. A circuit fault analysis device, characterized in that, The device includes: The model acquisition module acquires the runtime data generated during circuit operation, as well as the circuit fault analysis model. The fault analysis module inputs the operating data into the circuit fault analysis model to perform fault analysis and outputs the circuit fault analysis results. The circuit fault analysis model is trained using the training method for the circuit fault analysis model as described in any one of claims 1 to 5.

Images