Wafer alignment control method and system

Abstract

The application provides a wafer alignment control method and system, and relates to the technical field of image data processing.The method comprises the following steps: collecting a video of a target wafer to be aligned through machine vision, performing key frame analysis on the video of the wafer to be aligned, performing feature extraction after obtaining N image key frames, determining feature information of the wafer to be aligned, determining M wafer alignment position information according to the feature information of the wafer to be aligned, traversing the M wafer alignment position information based on historical wafer alignment position information, obtaining deviation position information, performing data cleaning on the M wafer alignment position information according to the deviation position information, and controlling the alignment position of the target wafer.The application solves the technical problem that the alignment of machine vision is poor in the prior art, which leads to poor control of the wafer alignment position and inaccurate final wafer alignment position, realizes rational and accurate control of the wafer alignment position, and further improves the accuracy of the wafer alignment position.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image data processing, and particularly relates to a wafer alignment control method and system. BACKGROUND

[0002] Semiconductor elements are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor elements are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor material layers over a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] However, in the prior art, there is a technical problem that poor machine vision alignment leads to poor control of wafer alignment position, so that the final wafer alignment position is inaccurate. SUMMARY

[0004] The present application provides a wafer alignment control method and system, which is used to solve the technical problem that poor machine vision alignment leads to poor control of wafer alignment position, so that the final wafer alignment position is inaccurate.

[0005] In view of the above problems, the present application provides a wafer alignment control method and system.

[0006] In a first aspect, the present application provides a wafer alignment control method, which comprises: collecting video of a target wafer to be aligned through machine vision, to obtain a video of the wafer to be aligned; performing key frame analysis on the video of the wafer to be aligned, to obtain N image key frames, wherein N is a positive integer greater than 1; performing feature extraction based on the N image key frames, to determine feature information of the wafer to be aligned; determining M wafer alignment position information according to the feature information of the wafer to be aligned, wherein M is a positive integer greater than or equal to 2; traversing the M wafer alignment position information based on historical wafer alignment position information, to obtain deviation position information; performing data cleaning on the M wafer alignment position information according to the deviation position information; and controlling the alignment position of the target wafer.

[0007] In a second aspect, the application provides a wafer alignment control system, which comprises: a video acquisition module, configured to acquire a video of a target wafer to be aligned through machine vision, and obtain a wafer video to be aligned; a key frame analysis module, configured to analyze key frames of the wafer video to be aligned, and obtain N image key frames, wherein N is a positive integer greater than 1; a feature extraction module, configured to extract features based on the N image key frames, and determine wafer feature information to be aligned; a position determination module, configured to determine M wafer alignment position information according to the wafer feature information to be aligned, wherein M is a positive integer greater than or equal to 2; a traversal module, configured to traverse the M wafer alignment position information based on historical wafer alignment position information, and obtain deviation position information; and a control module, configured to control the alignment position of the target wafer by data cleaning of the M wafer alignment position information according to the deviation position information.

[0008] The one or more technical solutions provided in the application have at least the following technical effects or advantages:

[0009] The wafer alignment control method and system provided by the application are related to the technical field of image data processing, and solve the technical problem that the poor machine vision alignment in the prior art leads to poor control of the wafer alignment position and inaccurate final wafer alignment position, and achieve rational and accurate control of the wafer alignment position, thereby improving the accuracy of the wafer alignment position. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A wafer alignment control method flowchart is provided for the application;

[0011] Figure 2 A wafer alignment control system structure diagram is provided for the application.

[0012] Legend of the drawings: video acquisition module 1, key frame analysis module 2, feature extraction module 3, position determination module 4, traversal module 5, and control module 6. DETAILED DESCRIPTION

[0013] The application provides a wafer alignment control method and system to solve the technical problem that the poor machine vision alignment in the prior art leads to poor control of the wafer alignment position and inaccurate final wafer alignment position.

[0014] Embodiment one

[0015] As shown in Figure 1 The application provides a wafer alignment control method, which comprises:

[0016] Step S100: video acquisition of a target wafer to be aligned by machine vision, to obtain a video of the wafer to be aligned;

[0017] Specifically, the wafer alignment control method provided by the embodiment of the application is applied to a wafer alignment control system. In order to better control the target wafer in the alignment position, first, the video acquisition of the target wafer in the non-alignment position is performed by machine vision. Machine vision refers to the use of machines to replace the human eye to measure and judge. That is, the image acquisition device converts the target wafer in the non-alignment position into an image signal, which is transmitted to a dedicated image processing system to obtain the shape information of the target wafer in the non-alignment position. According to the pixel distribution, brightness, color and other information, the digital signal is converted, so as to complete the video of the wafer to be aligned, which serves as an important reference for the subsequent control of the alignment position of the target wafer.

[0018] Step S200: key frame analysis of the video of the wafer to be aligned, to obtain N image key frames, wherein N is a positive integer greater than 1;

[0019] Specifically, based on the obtained video of the wafer to be aligned, the video of the wafer to be aligned is segmented by using the lens boundary detection method of the image acquisition device to obtain a plurality of video frames. The key frames in which the target wafer exists in the video of the wafer to be aligned are extracted from the plurality of video frames obtained after segmentation. The extracted key frames are integrated to obtain N image key frames, and N is a positive integer greater than 1. Thus, the control of the alignment position of the target wafer is ensured.

[0020] Step S300: feature extraction based on the N image key frames, to determine the feature information of the wafer to be aligned;

[0021] Specifically, the I-frame image is extracted from the N image key frames, and the I-frame image is segmented according to the preset block standard. The discrete cosine transform coefficients of the segmented I-frame image block are calculated, and the discrete cosine transform coefficients include direct current coefficients and alternating current coefficients. That is, the feature value of the I-frame image in each image key frame is calculated according to the direct current coefficients and alternating current coefficients using the feature value calculation formula. Thus, the feature information of the wafer to be aligned is determined according to the size of the I-frame image feature value. The larger the I-frame image feature value is, the more likely the current image key frame is to become the feature information, which lays a foundation for the subsequent control of the alignment position of the target wafer.

[0022] Step S400: determination of M wafer alignment position information according to the feature information of the wafer to be aligned, wherein M is a positive integer greater than or equal to 2;

[0023] Specifically, on the basis of the I-frame image feature values contained in the wafer feature information to be aligned, all the images in the N image key frames are divided into equal grids, and the divided equal grid image information is iteratively identified based on a convolution kernel, that is, by sequentially accessing the image grid nodes in the grid image information and identifying the wafer structure within the image, M wafer alignment positions are determined, and the M wafer alignment positions include wafer alignment positions and suspected wafer alignment positions, and M is a positive integer greater than or equal to 2, so as to serve as reference data for later control of the alignment position of the target wafer.

[0024] Step S500: Based on the historical wafer alignment position information, the M wafer alignment position information is iterated to obtain deviation position information.

[0025] Specifically, the wafer alignment position information obtained by aligning the wafer in the past time period is taken as a standard position, each wafer alignment position node contained in the M wafer alignment position information obtained above is sequentially accessed, and the accessed node position information is matched and compared with the standard position, one position that coincides with or is closest to the standard position is selected as a temporary optimal wafer alignment position, and the remaining M-1 wafer alignment position information is recorded as deviation position information for output, thereby improving the accuracy of later control of the alignment position of the target wafer.

[0026] Step S600: According to the deviation position information, the M wafer alignment position information is data cleaned to control the alignment position of the target wafer.

[0027] Specifically, the M-1 wafer alignment position information contained in the deviation position information is taken as target data, thereby iterating the M wafer alignment position information, data cleaning is performed on the iteration result that meets the target data in the M wafer alignment position information, the data cleaning refers to deleting the wafer alignment position information that meets the target data in the M wafer alignment position information, then a data matrix of the wafer alignment position is constructed according to the data cleaning result, and finally the constructed matrix is set as the alignment position of the target wafer, thereby completing the control of the alignment position of the target wafer and improving the accuracy of the wafer alignment position.

[0028] Further, the step S200 of the present application further comprises:

[0029] Step S210: performing video segmentation on the wafer video to be aligned by using a lens boundary detection method to obtain segmented video information.

[0030] Step S220: extracting key frames based on the segmented video information to obtain N image key frames.

[0031] Specifically, in order to more accurately control the alignment position of the wafer, first, a lens boundary detection method is used to segment the video of the wafer to be aligned by machine vision, wherein the input of the lens boundary detection method is the video of the wafer to be aligned. Further, each frame of the video of the wafer to be aligned is compressed to a uniform small size of 48x27x3, and every 100 frames are taken as a segment. Further, the start frame defining the lens in the segmented video information obtained above is taken as a key frame, and key frame extraction is dynamically performed on the segmented video information. The extraction of the key frame should not be based on the length of the current lens, but should be based on the change intensity of the current lens, that is, the more intense the change of the current lens, the more key frames should be extracted. Even if the current lens is not long, on the contrary, even if a long lens, if the picture basically does not change, fewer key frames should be extracted. If the picture of the current lens is all black, no key frame is extracted. For example, if M frames are started, the maximum frame in the next 8 frames is found. If the interval of the maximum frame is less than M, the M frame is retained. Otherwise, the next step is performed. If there is a frame greater than M, it is named P. The average value of the interval between M and P is calculated, and it is judged whether P is greater than the multiple of the average value. If not, M is retained. Otherwise, P is the new M frame, and the next judgment is continued. From the new key frame, each subsequent frame is compared with it until the last frame. After the comparison, it is judged whether the number of key frames obtained actually satisfies the relationship. If not, the key frames are recombined. The iteration is continued until the number of key frames reaches the requirement, and the algorithm ends. All the key frames obtained after iteration are recorded as N image key frames, which achieve the technical effect of providing an important basis for realizing the control of the alignment position of the target wafer in the later stage.

[0032] Further, step S300 of the present application further comprises:

[0033] Step S310: extracting an I frame image;

[0034] Step S320: segmenting the I frame image according to a preset segmentation standard to determine a target I frame image block;

[0035] Step S330: calculating discrete cosine transform coefficients based on the target I frame image block, wherein the discrete cosine transform coefficients include a direct current coefficient and an alternating current coefficient;

[0036] Step S340: calculating an I frame image eigenvalue according to the direct current coefficient and the alternating current coefficient by using an eigenvalue calculation formula;

[0037] Step S350: adding the I frame image eigenvalue to the feature information of the wafer to be aligned.

[0038] Specifically, first, I-frame images in N image key frames are extracted, and the extracted I-frame images are further segmented according to a preset segmentation standard, wherein the obtained preset segmentation standard is preset by a related technical person according to a pixel block in the I-frame image, and a target I-frame image block is determined, so as to divide the discrete cosine change coefficient into a first discrete cosine change coefficient and a second discrete cosine change coefficient.

[0039] wherein a first direct current coefficient and a first alternating current coefficient in the first discrete cosine change coefficient are extracted, and the first feature value is calculated according to the first direct current coefficient and the first alternating current coefficient, wherein the calculation formula is as follows:

[0040]

[0041] T n refers to the first feature value, DC n (x', y') refers to the first direct current coefficient, AC n (x', y') refers to the first alternating current coefficient, n refers to the first I-frame image, (x', y') refers to an (x', y')th sub-block of the first I-frame image, a refers to an influence factor of the first direct current coefficient on the first feature value, and b refers to an influence factor of the first alternating current coefficient on the first feature value.

[0042] Further, a second direct current coefficient and a second alternating current coefficient in the second discrete cosine change coefficient are extracted;

[0043] According to the second direct current coefficient and the second alternating current coefficient, a second feature value is calculated, wherein the calculation formula is as follows:

[0044]

[0045] T n+1 refers to the second feature value, DC n+1 (x'', y'') refers to the second direct current coefficient, AC n+1 (x'', y'') refers to the second alternating current coefficient, n+1 refers to the second I-frame image, (x'', y'') refers to an (x'', y'')th sub-block of the second I-frame image, c refers to an influence factor of the second direct current coefficient on the second feature value, and d refers to an influence factor of the second alternating current coefficient on the second feature value.

[0046] Finally, the feature values of adjacent I-frame images are calculated, that is, the feature value of the I-frame image is the white rectangular pixel and minus the black rectangular pixel, which reflects the gray scale change of the image. The I-frame image feature value is obtained, and then the I-frame image feature value is added to the to-be-aligned wafer feature information to improve the to-be-aligned wafer feature information, so as to ensure the optimal control of the alignment position of the target wafer in the later stage.

[0047] Further, the step S400 of the application further includes:

[0048] Step S410: based on the I-frame image feature value in the wafer alignment feature information, grid division is performed on the images in the N image key frames to obtain divided image information;

[0049] Step S420: based on the convolution kernel, the divided image information is iteratively identified to obtain grid identification information;

[0050] Step S430: according to the grid identification information, the wafer alignment position is determined.

[0051] Specifically, according to the size of the I-frame image feature value in the wafer alignment feature information, the images in the N image key frames are divided into equal grids, and the image with a large feature value corresponds to a small divided grid, and the image with a small feature value corresponds to a large divided grid, so as to achieve fine processing of the image with a high feature value, thereby obtaining the divided image information, and then iteratively identifying and screening the image information captured by the divided image information. In the process of image recognition of the image collection set, it can be realized by comparing the convolution kernel features. For example, based on the obtained divided image information, the first region in the image equal grid is set as the starting point, i.e. the obtained first region is marked as the zero point region, and then the iteration starts from the first region, the information obtained in each region is matched with the wafer alignment position feature in the big data, thereby obtaining the grid identification information. Further, according to the grid image block matched with the wafer alignment position in the grid identification information, the wafer alignment position is determined, and the alignment position of the target wafer is accurately controlled based on the determined wafer alignment position.

[0052] Further, the step S600 of the application further includes:

[0053] Step S610: obtaining a plurality of deviation position information;

[0054] Step S620: according to the plurality of deviation position information, iteratively deleting the M wafer alignment position information to obtain a wafer alignment position information cleaning result;

[0055] Step S630: according to the M wafer alignment position information cleaning result, constructing a wafer alignment position matrix;

[0056] Step S640: based on the wafer alignment position matrix, setting the alignment position of the target wafer.

[0057] Specifically, the deviation position information obtained by traversing the M wafer alignment position information based on the historical wafer alignment position information is taken as the traversal target information, so as to traverse the M wafer alignment position information, and the traversal result meeting the target data is subjected to data cleaning in the M wafer alignment position information. The data cleaning refers to deleting the wafer alignment position information meeting the target data in the M wafer alignment position information, and obtaining the M wafer alignment position information cleaning result

[0058] Therefore, on the basis of the M wafer alignment position information cleaning result, a wafer alignment position matrix is established through a function, such as y=sin(x), and the response relationship of the elements in the wafer alignment position matrix to the wafer alignment position is a one-to-one relationship. That is, when the transmission module has a position in the wafer alignment position matrix, there is only one wafer alignment position. After matching the wafer alignment position matrix according to the M wafer alignment position information cleaning result, there is only one wafer alignment position. Finally, the wafer alignment position output by the wafer alignment position matrix is set as the alignment position of the target wafer, so as to ensure the efficiency when the alignment position of the target wafer is controlled.

[0059] Further, the step S700 of the present application further includes:

[0060] Step S710: position alignment supervision is performed on the alignment position of the target wafer, and an alignment supervision result is obtained.

[0061] Step S720: position alignment accuracy evaluation is performed on the alignment supervision result and the alignment position of the target wafer, and a position alignment accuracy evaluation result is obtained.

[0062] Step S730: real-time position adjustment is performed on the wafer alignment position according to the position alignment accuracy evaluation result.

[0063] Specifically, after the data cleaning of the M wafer alignment position information and the control of the alignment position of the target wafer according to the deviation position information, position alignment supervision is performed on the alignment position of the current target wafer, that is, it is further judged whether the alignment position of the current target wafer is completed. The judgment result is recorded as the alignment supervision result. Meanwhile, position alignment accuracy evaluation is performed on the alignment supervision result and the alignment position of the target wafer. If the alignment position of the current target wafer is not completed, the position alignment accuracy evaluation of the alignment position of the target wafer is unqualified. If the alignment position of the current target wafer is completed, the position alignment accuracy evaluation of the alignment position of the target wafer is qualified. If the position alignment accuracy evaluation result is unqualified, real-time adjustment control is performed on the position of the current target wafer alignment position, so as to ensure the efficiency of the control of the alignment position of the target wafer.

[0064] Embodiment Two

[0065] Based on the same inventive concept as the wafer alignment control method in the foregoing embodiment, as shown in the following, the present application provides a wafer alignment control system, which comprises: Figure 2

[0066] a video acquisition module 1 configured to acquire a video of a target wafer to be aligned by machine vision, and obtain a wafer video to be aligned;

[0067] a key frame analysis module 2 configured to analyze key frames of the wafer video to be aligned, and obtain N image key frames, wherein N is a positive integer greater than 1;

[0068] a feature extraction module 3 configured to extract features based on the N image key frames, and determine wafer feature information to be aligned;

[0069] a position determination module 4 configured to determine M wafer alignment position information according to the wafer feature information to be aligned, wherein M is a positive integer greater than or equal to 2;

[0070] a traversal module 5 configured to traverse the M wafer alignment position information based on historical wafer alignment position information, and obtain deviation position information;

[0071] a control module 6 configured to control alignment positions of the target wafer by data cleaning the M wafer alignment position information according to the deviation position information.

[0072] Further, the system further comprises:

[0073] a video segmentation module configured to segment the wafer video to be aligned by a lens boundary detection method, and obtain segmentation video information;

[0074] a key frame extraction module configured to extract key frames based on the segmentation video information, and obtain N image key frames.

[0075] Further, the system further comprises:

[0076] an extraction module configured to extract I-frame images;

[0077] a segmentation module configured to segment the I-frame images according to a preset segmentation standard, and determine target I-frame image blocks;

[0078] ​The first calculation module is configured to calculate discrete cosine transform coefficients based on the target I-frame image block, wherein the discrete cosine transform coefficients include a direct current coefficient and an alternating current coefficient;

[0079] The second calculation module is configured to calculate an I-frame image feature value according to the direct current coefficient and the alternating current coefficient by using a feature value calculation formula.

[0080] The adding module is configured to add the I-frame image feature value to the wafer feature information to be aligned.

[0081] Further, the system further comprises:

[0082] The grid division module is configured to divide the N image key frames into grids based on the I-frame image feature value in the wafer feature information to be aligned, and obtain divided image information.

[0083] The traversal identification module is configured to perform traversal identification on the divided image information based on a convolution kernel, and obtain grid identification information.

[0084] The wafer alignment position determination module is configured to determine a wafer alignment position according to the grid identification information.

[0085] Further, the system further comprises:

[0086] The position information acquisition module is configured to acquire a plurality of offset position information.

[0087] The deletion module is configured to delete the M wafer alignment position information according to the plurality of offset position information, and obtain a M wafer alignment position information cleaning result.

[0088] The matrix construction module is configured to construct a wafer alignment position matrix according to the M wafer alignment position information cleaning result.

[0089] The position setting module is configured to set the alignment position of the target wafer based on the wafer alignment position matrix.

[0090] Further, the system further comprises:

[0091] The position alignment supervision module is configured to perform position alignment supervision on the alignment position of the target wafer, and obtain an alignment supervision result.

[0092] an evaluation module configured to perform position alignment accuracy evaluation on the alignment position of the target wafer according to the alignment supervision result, and obtain a position alignment accuracy evaluation result;

[0093] an adjustment module configured to perform real-time position adjustment on the wafer alignment position according to the position alignment accuracy evaluation result.

[0094] The foregoing detailed description of the wafer alignment control method has enabled those skilled in the art to clearly understand the wafer alignment control system in the embodiments. As the device disclosed in the embodiments corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part.

[0095] The foregoing description of the disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer alignment control method, characterized by, The method comprises the following steps: video acquisition of a target wafer to be aligned by machine vision to obtain a video of the wafer to be aligned; key frame analysis of the video of the wafer to be aligned to obtain N image key frames, wherein N is a positive integer greater than 1; feature extraction based on the N image key frames to determine wafer to be aligned feature information; determination of M wafer alignment position information according to the wafer to be aligned feature information, wherein M is a positive integer greater than or equal to 2; obtaining deviation position information by traversing the M wafer alignment position information based on historical wafer alignment position information; data cleaning of the M wafer alignment position information according to the deviation position information to control the alignment position of the target wafer.

2. The method of claim 1, wherein, The N image key frames are obtained by the following steps: video segmentation of the video of the wafer to be aligned by using a lens boundary detection method to obtain segmentation video information; key frame extraction based on the segmentation video information to obtain N image key frames.

3. The method of claim 1, wherein, The wafer to be aligned feature information is determined by the following steps: extracting an I-frame image; segmenting the I-frame image according to a preset block standard to determine a target I-frame image block; calculating discrete cosine transform coefficients based on the target I-frame image block, wherein the discrete cosine transform coefficients include direct current coefficients and alternating current coefficients; calculating I-frame image feature values according to the direct current coefficients and the alternating current coefficients by using a feature value calculation formula; adding the I-frame image feature values to the wafer to be aligned feature information.

4. The method of claim 3, wherein, The wafer alignment position information is determined by the following steps: grid division of an image in the N image key frames based on the I-frame image feature values in the wafer to be aligned feature information to obtain divided image information; traversal recognition of the divided image information based on a convolution kernel to obtain grid recognition information; determination of wafer alignment positions according to the grid recognition information.

5. The method of claim 1, wherein, The data cleaning of the M wafer alignment position information according to the deviation position information comprises the following steps: obtaining multiple deviation position information; deleting the M wafer alignment position information according to the multiple deviation position information to obtain M wafer alignment position information cleaning results; constructing a wafer alignment position matrix according to the M wafer alignment position information cleaning results; setting the wafer alignment position matrix as the alignment position of the target wafer.

6. The method of claim 1, wherein, The method further comprises the following steps: position alignment supervision of the alignment position of the target wafer to obtain an alignment supervision result; position alignment precision evaluation of the alignment supervision result and the alignment position of the target wafer to obtain a position alignment precision evaluation result; real-time position adjustment of the wafer alignment position by the position alignment precision evaluation result.

7. A wafer alignment control system, characterized by, The method comprises the following steps: a video acquisition module for video acquisition of a target wafer to be aligned by machine vision to obtain a video of the wafer to be aligned; a key frame analysis module for key frame analysis of the video of the wafer to be aligned to obtain N image key frames, wherein N is a positive integer greater than 1; The feature extraction module is configured to perform feature extraction based on the N image key frames to determine wafer-to-be-aligned feature information; The position determination module is configured to determine M wafer alignment position information according to the wafer-to-be-aligned feature information, where M is a positive integer greater than or equal to 2; The traversal module is configured to traverse the M wafer alignment position information based on historical wafer alignment position information to obtain deviation position information; The control module is configured to perform data cleaning on the M wafer alignment position information according to the deviation position information to control the alignment position of the target wafer.

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