A sampling method for reducing the minimum on-time allowable by the system

Abstract

The application discloses a sampling mode for reducing the minimum on-time allowed by a system, comprising the following steps: step 1, determining the control mode of a BUCK circuit; and step 2, controlling the BUCK circuit based on the delay sampling of a SW voltage, wherein SW is the connection point of an upper tube and a lower tube in the BUCK circuit. The BUCK circuit is controlled based on the delay sampling of the SW voltage, so that the minimum on-time allowed by the system is reduced.

Description

Technical Field

[0001] This invention belongs to the field of converter control technology and relates to a sampling method for reducing the minimum allowable on-time of a system. Background Technology

[0002] With the increasing demand for power, voltage converters have developed rapidly and are widely used in power supplies for various electronic devices, daily lighting, and household appliances.

[0003] The converter operates in two modes based on its output state: constant voltage output mode and constant current output mode. Taking a BUCK circuit as an example... Figure 2 This is the basic topology of a BUCK circuit. A common problem is that when the BUCK circuit output switches from a light load to a heavy load, the inductor current cannot increase in time, resulting in an average inductor current that is less than the current required by the load. This leads to a large drop in output voltage and a long recovery time. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application provides a sampling method for reducing the minimum allowable on-time of a system.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A sampling method for reducing the minimum allowable on-time of a system, the method comprising the following steps: Step 1: Determine the BUCK circuit control mode; Step 2: Control the BUCK circuit based on the delayed sampling of the SW voltage; SW is the connection point between the upper and lower transistors in the BUCK circuit.

[0006] The present invention further includes the following preferred embodiments: Preferably, the BUCK circuit includes a voltage source Vin, an upper transistor S1, a lower transistor S2, an inductor L, a capacitor Cout, and a resistor Rout; The positive terminal of the voltage source Vin is connected to the upper transistor S1, and the negative terminal is connected to the lower transistor S2 and grounded. The inductor L and capacitor Cout form a low-pass filter, which is connected in parallel with resistor Rout across the lower transistor S2.

[0007] Preferably, in step 1, the control modes of the BUCK circuit include voltage control mode and current control mode.

[0008] Preferably, the BUCK circuit maintains the output voltage VO at the rated voltage by switching the upper transistor S1 and the lower transistor S2 on and off. Furthermore, it adopts a continuous conduction mode, and when the circuit is working stably, the output voltage VO = D * Vin; Where D = TON / T, and TON is the on-time of the upper tube within a switching cycle T.

[0009] Preferably, in step 1, the control mode of the BUCK circuit is determined to be the peak current control mode to control the on / off state of the upper transistor S1. In this mode, the peak value of the inductor current IL, IPEAK, is determined by the output voltage EAO of the error amplifier EA.

[0010] Preferably, the error amplifier EA detects the error between the output voltage divider FB and the reference voltage FB_REF. After the error is amplified, the output voltage EAO is obtained. EAO positively affects the reference current IREF of IL, thereby affecting the peak value IPEAK of IL, which is used by the BUCK circuit to stabilize the output voltage.

[0011] Preferably, step 2 specifically includes: Step 2.1: Set the delay time DELAY according to the actual system conditions. After the upper tube is turned on, delay DELAY, and then sample the SW voltage through SW_SENSE detection to make SW_SENSE=SW. Step 2.2: Use a comparator to determine whether SW_SENSE is lower than the set FB_REF, and thus determine whether IL has risen to IREF; Step 2.3: After IL rises to IREF, a RESET pulse is generated to turn off the upper tube.

[0012] Preferably, in step 2.1, DELAY includes the time for the VGS of the upper tube S1 to build up to the Miller platform and the SW rise time.

[0013] Preferably, the DELAY setting is as follows:

[0014] In the formula, The time it takes for the VGS of the upper tube S1 to establish up to the Miller platform; C HS_GATE It is the gate-source capacitance of the upper transistor S1; The gate-source voltage is the moment when the current IDS flowing through the upper transistor equals the inductor current IL. It is the current that charges the gate source during the turn-on process of the upper transistor driven by the gate-source voltage of the upper transistor; It is the maximum rise time of SW; It is the parasitic capacitance from point SW to ground.

[0015] Preferably, in step 2.3, the comparator compares SW_SENSE and FB_REF and outputs a high level, which is used as a RESET pulse to turn off the upper transistor.

[0016] The beneficial effects achieved by this application are: This invention reduces the minimum allowable on-time of the system (i.e., the BUCK circuit) by controlling the BUCK circuit based on delayed sampling of the SW voltage. Attached Figure Description

[0017] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is the basic topology diagram of the BUCK circuit; Figure 3 CCM working sequence Figure 4 This is the schematic diagram of peak current control mode. Figure 5 It is the upper transistor turn-off logic diagram. Figure 6 It detects the upper transistor turn-off logic generated by SW. Figure 7 The time-blocking LEB is used to block out the erroneous flip logic immediately after the upper transistor is turned on; Figure 8 The logic that disables the erroneous flip-over immediately after the upper transistor is turned on after adding a long LEB Delay is applied. Figure 9 This is the improved HS_COMP of this invention; Figure 10 This is a schematic diagram of the BUCK circuit control based on delayed sampling of the SW voltage in this invention. Figure 11 This is the ideal case for the upper tube Miller platform; Figure 12 This is a schematic diagram of the delayed sampling operation principle of the present invention. Detailed Implementation

[0018] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0019] like Figure 1 As shown, the present invention provides a sampling method for reducing the minimum allowable on-time of a system, comprising the following steps: Step 1: Determine the BUCK circuit control mode; like Figure 2 As shown, the BUCK circuit includes a voltage source Vin, an upper transistor S1, a lower transistor S2, an inductor L, a capacitor Cout, and a resistor Rout; The positive terminal of the voltage source Vin is connected to the upper transistor S1, and the negative terminal is connected to the lower transistor S2 and grounded. The inductor L and capacitor Cout form a low-pass filter, which is connected in parallel with resistor Rout across the lower transistor S2.

[0020] In practice, Figure 2 The BUCK circuit maintains the output voltage VO at the rated voltage by switching the upper transistor S1 and the lower transistor S2 on and off. It adopts continuous conduction mode (CCM), and the corresponding operating timing is as follows: Figure 3 As shown in the diagram. Here, IL is the inductor current, HS is the upper transistor turn-on signal, LS is the lower transistor turn-on signal, TON is the upper transistor turn-on time within a switching cycle T, and TOFF is the upper transistor turn-off time within a switching cycle T. The proportion of TON to the entire cycle T is D. When the system is operating stably, the output voltage VO = D * Vin.

[0021] Figure 2 The condition under which a transistor in a circuit changes from on to off is determined by the converter's control method. Based on the control method, circuits are divided into voltage control mode circuits and current control mode circuits.

[0022] In practice, the peak current control mode is used to control the switching on and off of the upper transistor S1. In this mode, the peak value of the inductor current IL, IPEAK, is determined by the output voltage EAO of the error amplifier EA inside the chip.

[0023] After the upper transistor is turned off, the lower transistor is turned on. The chip internally times the lower transistor's on-time. After the timer expires, the lower transistor turns off, generating a SET signal to trigger the upper transistor to turn on again. See [link / details]. Figure 10 .

[0024] The error amplifier is a normal amplifier, but it's often called an error amplifier because it's used to integrate the errors of FB and SSREF. Its connection to the BUCK circuit is shown in [link to BUCK circuit diagram]. Figure 10 .

[0025] Specifically, the error amplifier EA detects the error between the output voltage divider FB and the reference voltage FB_REF established inside the chip. After the error is amplified, the output voltage EAO is obtained. EAO positively affects the reference current IREF of IL, thereby affecting the peak value IPEAK of IL, which is used by the BUCK circuit to stabilize the output voltage.

[0026] The error amplifier EA detects the error between the output voltage divider FB and the reference voltage FB_REF. After the error is amplified, the output voltage EAO is obtained. EAO positively affects the reference current IREF of IL, thereby affecting the peak value IPEAK of IL, which is used by the BUCK circuit to stabilize the output voltage.

[0027] SW can reflect IL information. IL is sampled by sampling SW. The larger the IL, the smaller the SW, and the lower the SW_SENSE. When it is lower than FB_REF, the upper transistor is triggered to turn off, and the IL at this time is the maximum value IPEAK. This sampling method is the basic sampling method. The highlight of this invention is that the sampling start time is delayed. Instead of sampling SW as soon as the upper transistor is turned on, sampling is delayed for a while.

[0028] Figure 4 The connection relationship between the three circuits and the BUCK circuit is shown in the figure. Figure 10 .

[0029] Specifically: When the output switches from a light load (e.g., IL=0A) to a heavy load (e.g., IL=5A), the output voltage VO decreases, FB decreases, the value of FB_REF (FB) increases, EAO increases, and IPEAK increases, thereby increasing the average output inductor current. The closed-loop feedback ultimately restores the previously decreased VO to its rated value. Conversely, the negative feedback of this closed loop eventually stabilizes the output voltage at its rated value. The principle is as follows: Figure 4 As shown.

[0030] Based on the above analysis, it can be seen that for the upper transistor turn-off logic, after detecting that IL rises to IREF, a RESET pulse is generated to turn off the upper transistor, such as... Figure 5 As shown. By Figure 5 It is evident that the inductor current detection circuit is particularly important in controlling the turn-off of the upper transistor.

[0031] In conventional methods, SW decreases as the inductor current increases. Therefore, SW_SENSE can be used to detect whether the SW voltage is below a certain value FB_REF to determine whether IL has reached IREF. Figure 6 As shown.

[0032] In practical operation, due to the presence of parasitic inductance and capacitance, SW oscillates at a high frequency when the upper transistor is first turned on, causing the comparator outputs of SW_SENSE and FB_REF to flip incorrectly. Therefore, a shielding time LEB is needed to shield against the incorrect flipping immediately after the upper transistor is turned on. Figure 7 As shown.

[0033] The comparator's topping has a delay. Therefore, when the upper transistor is first turned on, if the comparator accidentally toggles high, even if SW_SENSE returns to a value higher than FB_REF, the comparator output COMPOUT cannot immediately toggle low due to the comparator's topping delay. As a result, the time when COMPOUT is erroneously high may even be longer than the high-frequency oscillation time of SW, which means that LEB needs to be long enough to completely mask the erroneous COMPOUT.

[0034] Even when the parasitic oscillation of SW is negligible, at the instant the upper transistor turns on, SW_SENSE equals SW. However, because SW was a negative voltage in the previous state and the lower transistor has a large parasitic capacitance, SW needs time to rise and cannot immediately exceed FB_REF. During the initial period of the upper transistor's turn-on, SW_SENSE is less than FB_REF, resulting in a false COMPOUT flip. Furthermore, due to the delay, it will remain at an incorrect high level for a period of time before recovering. Therefore, to eliminate this misjudgment, a long LEB Delay must be added, thus minimizing the upper transistor's conduction time T. ONMIN It is restricted from being shorter. For example... Figure 8 As shown.

[0035] When the switching period is fixed, T ONMIN The minimum duty cycle that prevents the system from outputting Vin*T, which is essential for its normal operation. ONMIN The low voltage of / T limits the operating conditions of the system.

[0036] The present invention is further improved, specifically: Step 2: Control the BUCK circuit based on the delayed sampling of the SW voltage; SW is the connection point between the upper and lower transistors in the BUCK circuit.

[0037] Step 2 specifically includes: Step 2.1: Set the delay time DELAY according to the actual system conditions. After the upper tube is turned on, delay DELAY, and then sample the SW voltage through SW_SENSE detection to make SW_SENSE=SW. SW_SENSE is a voltage measurement device connected to the SW node, see Figure 10 .

[0038] DELAY settings:

[0039] In the formula, The time it takes for the VGS of the upper tube S1 to establish up to the Miller platform; C HS_GATE It is the gate-source capacitance of the upper transistor S1; The gate-source voltage is the moment when the current IDS flowing through the upper transistor equals the inductor current IL. It is the current that charges the gate source during the turn-on process of the upper transistor driven by the gate-source voltage of the upper transistor; It is the maximum rise time of SW; It is the parasitic capacitance from point SW to ground.

[0040] The purpose of setting the sampling delay is to wait until SW rises above FB_REF after the upper MOSFET HS is turned on, and then HCS goes high before sampling SW begins. SW_SENSE=SW, see [link / details]. Figure 10 The current sampling feedback circuit.

[0041] Therefore, DELAY must include the time for the upper transistor S1 VGS to build up to the Miller plateau and the rise time of SW. According to the switching principle, ideally, when the switch's VGS rises to the Miller plateau, the current IDS flowing through the switch should just have risen to IL. Therefore... This represents the time it takes for the upper tube S1 VGS to establish itself on the Miller platform.

[0042] This is the maximum rise time of SW. In reality, IDS will be greater than IL. After VGS1 reaches the Miller platform, it will also increase to charge SW. Therefore, the charging current of CSW will be greater than IL. Here, in order to have a margin of flow, we ensure that SW is higher than FB_REF after DELAY, so we take the charging current of CSW as IL.

[0043] Ideally, the upper tube Miller platform, such as Figure 11 As shown, T1 corresponds to T2 corresponds to .

[0044] The improvement of this invention is the addition of sampling delay, the specific operation of which is as follows: Figure 12 As shown.

[0045] Step 2.2: Use a comparator to determine whether SW_SENSE is lower than the set FB_REF, and thus determine whether IL has risen to IREF; Each IREF corresponds to an FB_REF. SW_SENSE directly reflects SW. The higher the IL, the lower SW = VIN - IL * Rdson_S1, and the lower SW_SENSE. When SW_SENSE is lower than FB_REF, the transistor is turned off, which means that at this time the IL corresponding to SW_SENSE is higher than the IREF corresponding to FB_REF.

[0046] Step 2.3: After IL rises to IREF, a RESET pulse is generated to turn off the upper tube.

[0047] The comparator outputs of SW_SENSE and FB_REF are high. Using this high level to perform an ONESHOT operation results in a RESET. The same applies to ON PULSE.

[0048] The logic for lower-level pipe activation and upper-level pipe activation is the opposite, see... Figure 10 .

[0049] For example, after the upper tube is turned on, the sampling SW is delayed by an appropriate time, such as 25ns, according to the actual system conditions, so that SW_SENSE=SW, to avoid SW_SENSE being pulled down by the previous state of SW and the high-frequency large-amplitude oscillation of SW when the upper tube is turned on.

[0050] Thus, before IL is higher than IREF, SW_SENSE will always be higher than FB_REF throughout the entire upper tube turn-on process, preventing the comparator output COMPOUT from being incorrectly toggled.

[0051] Even though high-frequency oscillations still exist on SW, the oscillation amplitude is low after delayed sampling, insufficient to cause COMPOUT to flip incorrectly. For example... Figure 9 As shown.

[0052] After the improvement, the LEB time can be reduced to slightly more than DELAY, such as 30 ns, thus T ONMIN Reduced. The system can operate stably at a smaller duty cycle.

[0053] In summary, this invention reduces the minimum allowable on-time of the system by using BUCK circuit control based on delayed sampling of the SW voltage. This method is applicable to any converter, as long as circuit control is performed using a sampling method that delays the SW voltage to sample the inductor current, thereby reducing the minimum allowable on-time of the system. The sampling methods for other converters are similar to BUCK and will not be elaborated further; protection can be claimed for the inductor current sampling method of any converter.

[0054] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A sampling method for reducing the minimum allowable on-time of a system, characterized in that: The method includes the following steps: Step 1: Determine the BUCK circuit control mode; Step 2: BUCK circuit control based on delayed sampling of the SW voltage, specifically including: Step 2.1: Set the delay time DELAY according to the actual system conditions. After the upper tube is turned on, delay DELAY, and then sample the SW voltage through SW_SENSE detection to make SW_SENSE=SW. Step 2.2: Use a comparator to determine whether SW_SENSE is lower than the set FB_REF, and thus determine whether IL has risen to IREF; Step 2.3: After IL rises to IREF, a RESET pulse is generated to turn off the upper transistor; SW is the connection point between the upper and lower transistors in the BUCK circuit.

2. The sampling method for reducing the minimum allowable on-time of a system according to claim 1, characterized in that: The BUCK circuit includes a voltage source Vin, an upper transistor S1, a lower transistor S2, an inductor L, a capacitor Cout, and a resistor Rout. The positive terminal of the voltage source Vin is connected to the upper transistor S1, and the negative terminal is connected to the lower transistor S2 and grounded. The inductor L and capacitor Cout form a low-pass filter, which is connected in parallel with resistor Rout across the lower transistor S2.

3. The sampling method for reducing the minimum allowable on-time of a system according to claim 2, characterized in that: The BUCK circuit maintains the output voltage VO at the rated voltage by switching the upper transistor S1 and the lower transistor S2 on and off. Furthermore, it adopts a continuous conduction mode, and when the circuit is working stably, the output voltage VO = D * Vin; Where D = TON / T, and TON is the on-time of the upper tube within a switching cycle T.

4. The sampling method for reducing the minimum allowable on-time of a system according to claim 1, characterized in that: In step 1, the control modes of the BUCK circuit include voltage control mode and current control mode.

5. The sampling method for reducing the minimum allowable on-time of a system according to claim 1, characterized in that: In step 1, the control mode of the BUCK circuit is determined to be the peak current control mode to control the on and off of the upper transistor S1. In this mode, the peak value of the inductor current IL, IPEAK, is determined by the output voltage EAO of the error amplifier EA.

6. The sampling method for reducing the minimum allowable on-time of a system according to claim 5, characterized in that: The error amplifier EA detects the error between the output voltage divider FB and the reference voltage FB_REF. After the error is amplified, the output voltage EAO is obtained. EAO positively affects the reference current IREF of IL, thereby affecting the peak value IPEAK of IL, which is used by the BUCK circuit to stabilize the output voltage.

7. The sampling method for reducing the minimum allowable on-time of a system according to claim 1, characterized in that: In step 2.1, DELAY includes the time for the VGS of the upper tube S1 to establish up to the Miller platform and the SW rise time.

8. The sampling method for reducing the minimum allowable on-time of a system according to claim 1, characterized in that: The DELAY setting method is as follows: In the formula, The time it takes for the VGS of the upper tube S1 to establish up to the Miller platform; C HS_GATE It is the gate-source capacitance of the upper transistor S1; The gate-source voltage is the moment when the current IDS flowing through the upper transistor equals the inductor current IL. It is the current that charges the gate source during the turn-on process of the upper transistor driven by the gate-source voltage of the upper transistor; It is the maximum rise time of SW; It is the parasitic capacitance from point SW to ground.

9. A sampling method for reducing the minimum allowable on-time of a system according to claim 1, characterized in that: In step 2.3, the comparator compares SW_SENSE and FB_REF and outputs a high level, which is used as a RESET pulse to turn off the upper transistor.

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