Light detection device and light detection system

Abstract

The light detection section of the present disclosure includes: a plurality of light receiving units each having a light receiving element and generating a first pulse signal including a pulse corresponding to a light receiving result of the light receiving element; an adding unit that selects at least one first pulse signal among a plurality of first pulse signals generated by the plurality of light receiving units, and generates a second pulse signal by performing an adding process based on the selected at least one first pulse signal; a distribution unit that performs a distribution process of distributing the second pulse signal in a time division manner based on a clock signal into a plurality of third pulse signals; a plurality of counters provided corresponding to the third pulse signals, and performing a counting process based on the corresponding third pulse signals; and a control unit that sets a number of signals of at least one pulse signal to be subjected to the adding process based on counting values of the plurality of counters.

Description

Technical Field

[0001] This disclosure relates to optical detection equipment and optical detection systems for detecting light. Background Technology

[0002] Time-of-Flight (TOF) methods are frequently used to measure distances to a target object. In this TOF method, light is emitted, and the reflected light from the target object is detected. The distance to the target object is then measured by measuring the time difference between the timing of the emitted light and the timing of the detected reflected light. For example, Patent Document 1 discloses a light detection device that controls the sensitivity of a light receiver based on a pulse rate, which represents the number of pulse signals output from the light receiver per unit time.

[0003] List of citations

[0004] Patent documents

[0005] PTL 1: Japanese Unexamined Patent Application Publication No. 2018-182051 Summary of the Invention

[0006] The photoelectric detection device is expected to have high detection accuracy, and further improvements in detection accuracy are anticipated.

[0007] The aim is to provide an optical detection device and optical detection system that can improve detection accuracy.

[0008] A photoelectric detection apparatus according to an embodiment of the present disclosure includes a plurality of light receiving units, an adder, a distributor, a plurality of counters, and a control unit. Each of the plurality of light receiving units includes a light receiving element and is configured to generate a first pulse signal comprising a pulse corresponding to the result of light reception by the light receiving element. The adder is configured to generate a second pulse signal by selecting one or more first pulse signals from the plurality of first pulse signals generated by the plurality of light receiving units and performing addition processing based on the selected one or more first pulse signals. The distributor is configured to perform distribution processing to divide the second pulse signal into a plurality of third pulse signals in a time-division manner based on a clock signal. The plurality of counters are set to correspond to the plurality of third pulse signals and are configured to perform counting processing based on the corresponding third pulse signal. The control unit is configured to set the number of signals of the one or more pulse signals to undergo addition processing based on the corresponding count values ​​of the plurality of counters.

[0009] A light detection system according to an embodiment of the present disclosure includes a light emitting unit and a light detection unit. The light emitting unit is configured to emit light. The light detection unit is configured to detect light reflected from a detected object by the light emitted from the light emitting unit. The light detection unit includes a plurality of light receiving units, an adder, a distributor, a plurality of counters, and a control unit. Each of the plurality of light receiving units includes a light receiving element and is configured to generate a first pulse signal including pulses corresponding to the result of light reception by the light receiving element. The adder is configured to generate a second pulse signal by selecting one or more first pulse signals from the plurality of first pulse signals generated by the plurality of light receiving units and performing addition processing based on the selected one or more first pulse signals. The distributor is configured to perform distribution processing to distribute the second pulse signal into a plurality of third pulse signals in a time-division manner based on a clock signal. The plurality of counters are set to correspond to the plurality of third pulse signals and are configured to each perform counting processing based on the corresponding third pulse signal. The control unit is configured to set the number of signals of the one or more pulse signals to undergo addition processing based on the respective count values ​​of the plurality of counters.

[0010] In the optical detection apparatus and optical detection system according to embodiments of the present disclosure, a first pulse signal comprising a pulse corresponding to the result of optical reception by an optical receiving element is generated in a plurality of optical receiving units. Then, a second pulse signal is generated by selecting one or more first pulse signals from a plurality of first pulse signals generated by the plurality of optical receiving units and performing addition processing based on the selected one or more first pulse signals. This second pulse signal is then divided into a plurality of third pulse signals in a time-division manner based on a clock signal. A count value is generated by performing counting processing based on each of the plurality of third pulse signals. Then, the number of signals of the one or more pulse signals to undergo addition processing is set based on these count values. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a configuration example of a light detection system according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A block diagram of a configuration example of the light detection unit shown.

[0013] Figure 3 It means Figure 2 The circuit diagram shows an example of the structure of the photodetector.

[0014] Figure 4A It is shown in Figure 3 The circuit diagram shown is a construction example of the optical receiver.

[0015] Figure 4B It is shown Figure 3The circuit diagram shows another configuration example of the optical receiver shown.

[0016] Figure 5 It is shown Figure 3 The diagram shows a configuration example of the addition unit.

[0017] Figure 6A It is shown Figure 3 A block diagram showing an example configuration of the light intensity determination unit.

[0018] Figure 6B It is shown Figure 3 A block diagram of another configuration example of the light intensity determination unit shown in the figure.

[0019] Figure 6C It is shown Figure 3 A block diagram of another configuration example of the light intensity determination unit shown.

[0020] Figure 7 It means Figure 3 A block diagram illustrating an example of operation of the light detection unit in imaging mode.

[0021] Figure 8 It means Figure 3 The timing waveform diagram shows an example of the operation of the photodetector in imaging mode.

[0022] Figure 9 It is shown Figure 3 A block diagram illustrating an operational example of the ranging mode of the light detection unit.

[0023] Figure 10 It means Figure 3 The timing waveform diagram shows an example of operation of the optical detection unit in ranging mode.

[0024] Figure 11 This is an explanatory diagram illustrating an example of the operation of a light detection array in ranging mode.

[0025] Figure 12 This is a block diagram showing an example of the configuration of the light intensity determination unit according to a modified example.

[0026] Figure 13 This is a block diagram showing an example of the operation of the addition part according to a modified example.

[0027] Figure 14 This is an explanatory diagram showing an implementation example of the light detection unit according to another variation.

[0028] Figure 15A This is a circuit diagram showing an example of the configuration of the light receiver according to another variation.

[0029] Figure 15BThis is a circuit diagram showing another configuration example of the optical receiver according to another variation.

[0030] Figure 16 This is a block diagram illustrating a structural example of a light detection system according to another variation.

[0031] Figure 17 It is shown Figure 16 A block diagram of a configuration example of the light detection unit shown.

[0032] Figure 18 It means Figure 17 The circuit diagram shows an example of the structure of the optical detection unit.

[0033] Figure 19 It means Figure 18 The timing waveform diagram shows an example of the operation of the optical detection unit.

[0034] Figure 20 This is a circuit diagram showing an example of the configuration of the light receiver according to another variation.

[0035] Figure 21 This is a circuit diagram showing an example of the configuration of the adder section according to another variation.

[0036] Figure 22A A circuit diagram illustrating a configuration example of the light receiver according to another variation.

[0037] Figure 22B This is a circuit diagram showing a configuration example of the optical receiver according to another variation.

[0038] Figure 23 This is a circuit diagram illustrating an operational example of a light detection unit according to another variation.

[0039] Figure 24 This is a circuit diagram illustrating another operational example of a light detection unit according to another variation.

[0040] Figure 25 This is a circuit diagram illustrating another operational example of a light detection unit according to another variation.

[0041] Figure 26 This is a circuit diagram illustrating another operational example of a light detection unit according to another variation.

[0042] Figure 27 This is a circuit diagram showing an example of the configuration of the light receiver according to another variation.

[0043] Figure 28 It is shown Figure 27 The timing waveform diagram of an operational example of the optical receiver shown in the figure.

[0044] Figure 29 This is a circuit diagram showing an example of the configuration of the light receiver according to another variation.

[0045] Figure 30 It is shown in Figure 29 The timing waveform diagram shows an operational example of the imaging mode of the light receiver shown.

[0046] Figure 31 It is shown in Figure 29 The circuit diagram shows an example of operation of the light receiver in the imaging mode.

[0047] Figure 32 It is shown in Figure 29 The timing waveform diagram shows an operational example of the ranging mode of the optical receiver shown.

[0048] Figure 33 It shows Figure 29 The circuit diagram shows an example of operation of the optical receiver in the ranging mode.

[0049] Figure 34 This is a circuit diagram showing an example of the configuration of the light receiver according to another variation.

[0050] Figure 35 This is a circuit diagram showing an example of the configuration of the light receiver according to another variation.

[0051] Figure 36 This is a circuit diagram showing an example of the configuration of the light receiver according to another variation.

[0052] Figure 37 It is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0053] Figure 38 This diagram illustrates an example of the installation location of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0054] In the following description, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0055] 1. Example

[0056] 2. Examples of applications to moving bodies

[0057] <1. Implementation Method>

[0058] [Configuration Example]

[0059] Figure 1An example configuration of a light detection system (light detection system 1) according to an embodiment is shown. The light detection system 1 is configured to operate as an image sensor and as a ToF sensor. The light detection system 1 includes a light emitting unit 11, an optical system 12, a light detection unit 20, and a control unit 14.

[0060] The light emitting unit 11 is configured to emit light pulses L0 toward the detection object OBJ based on instructions from the control unit 14. The light emitting unit 11 emits light pulses L0 by performing an alternating operation of emitting light and not emitting light, based on instructions from the control unit 14. The light emitting unit 11 includes a light source, for example, that emits infrared light. This light source includes, for example, a laser light source, an LED (light-emitting diode), etc.

[0061] The optical system 12 includes a lens that forms an image on the light receiving surface S of the light detection unit 20.

[0062] The light detection unit 20 is configured to detect light based on instructions from the control unit 14. The light detection unit 20 then outputs image data based on the detection results as data DT.

[0063] The control unit 14 is configured to provide control signals to the light emitting unit 11 and the light detection unit 20 and control the operation of the light emitting unit 11 and the light detection unit 20, thereby controlling the operation of the light detection system 1. The control unit 14 includes a mode setting unit 15. The mode setting unit 15 is configured to set the operation mode M of the light detection system 1. The light detection system 1 can operate in imaging mode MA and ranging mode MB. Imaging mode MA is a mode in which an image of an object is captured based on light L10 from the object. The ranging mode MB is a mode in which a light pulse L0 is emitted and a reflected light pulse L1 reflected by the object OBJ is detected, thereby measuring the time difference between the timing of the emission of the light pulse L0 and the timing of the detection of the reflected light pulse L1. The mode setting unit 15 sets one of the imaging mode MA and the ranging mode MB to the operation mode M. In addition, the control unit 14 controls the operation of the light detection system 1 according to the set operation mode M.

[0064] Figure 2 An example configuration of the light detection unit 20 is shown. The light detection unit 20 includes a light detection array 21, a signal generation unit 22, a readout control unit 23, a signal processing unit 24, and a light detection control unit 25.

[0065] The photoelectric detection array 21 includes multiple photoelectric detection units U arranged in a matrix. Each photoelectric detection unit U is configured to detect light and count the number of detections.

[0066] Figure 3An example configuration of the light detection unit U is shown. The light detection unit U has multiple light receivers 31 (four light receivers 31A to 31D in this example), an adder 32, multiple selectors 33 (four selectors 33A to 33D in this example), multiple switches 34 (four switches 34A to 34D in this example), multiple counters 35 (four counters 35A to 35D in this example), and a light intensity determination unit 36.

[0067] Each of the plurality of optical receivers 31 is configured to detect light, thereby generating a pulse signal PLSA comprising a pulse corresponding to the detected light. Optical receiver 31A generates pulse signal PLS (pulse signal PLSA) by detecting light. Optical receiver 31B generates pulse signal PLS (pulse signal PLSB) by detecting light. Optical receiver 31C generates pulse signal PLS (pulse signal PLSC) by detecting light. Optical receiver 31D generates pulse signal PLS (pulse signal PLSD) by detecting light. Optical receiver 31A is described below as an example. It should be noted that this also applies to optical receivers 31B to 31D.

[0068] Figure 4A An example configuration of the light receiver 31A is shown. In this example, the light receiver 31A includes a photodiode PD, a resistor R1, and an inverter IV1.

[0069] A photodiode (PD) is a photoelectric conversion element that converts light into electrical charge. A PD has an anode supplied with a power supply voltage VSS and a cathode coupled to node N1. For example, avalanche photodiodes (APDs) and single-photon avalanche diodes (SPADs) can be used as PDs.

[0070] One end of resistor R1 is supplied with the power supply voltage VDD, and the other end is coupled to node N1.

[0071] Inverter IV1 is configured to output a low level when the voltage at node N1 is higher than the logic threshold and to output a high level when the voltage at node N1 is lower than the logic threshold, thereby generating the pulse signal PLSA.

[0072] Using this configuration, in the light receiver 31A, the photodiode PD induces avalanche amplification by detecting light, which lowers the voltage at node N1. Then, when the voltage at node N1 falls below the logic threshold of inverter IV1, the pulse signal PLSA changes from low to high. Current then flows into node N1 through resistor R1, causing the voltage at node N1 to rise. Then, when the voltage at node N1 rises above the logic threshold of inverter IV1, the pulse signal PLSA changes from high to low. Therefore, the light receiver 31A generates a pulse signal PLSA that includes a pulse corresponding to the detected light.

[0073] Figure 4B Another configuration example of the light receiver 31A is shown. In this example, the light receiver 31A includes a photodiode PD, a transistor MP1, an inverter IV1, and a control circuit CKT1.

[0074] Transistor MP1 is a P-type MOS (metal-oxide-semiconductor) transistor, and has a gate coupled to the output terminal of the control circuit CKT1, a source supplied with a power supply voltage VDD, and a drain coupled to node N1.

[0075] The control circuit CKT1 is configured to control the operation of transistor MP1 based on the pulse signal PLSA. Specifically, after the pulse signal PLSA changes from low to high, the control circuit CKT1 lowers the voltage at the gate of transistor MP1, and after the pulse signal PLSA changes from high to low, it raises the voltage at the gate of transistor MP1.

[0076] Using this configuration, in the light receiver 31A, the photodiode PD detects light, thereby reducing the voltage at node N1. Then, when the voltage at node N1 becomes lower than the logic threshold of inverter IV1, the pulse signal PLSA changes from low to high. After this change in pulse signal PLSA, the control circuit CKT1 changes the voltage at the gate of transistor MP1 to low. Therefore, transistor MP1 is turned on, allowing current to flow through transistor MP1 into node N1, which increases the voltage at node N1. Then, when the voltage at node N1 becomes higher than the logic threshold of inverter IV1, the pulse signal PLSA changes from high to low. After this change in pulse signal PLSA, the control circuit CKT1 changes the voltage at the gate of transistor MP1 to high. This turns off transistor MP1. Therefore, the light receiver 31A generates a pulse signal PLSA that includes a pulse corresponding to the detected light.

[0077] Addition section 32 ( Figure 3The light intensity determination unit 36 ​​is configured to generate pulse signal PLS1 by performing addition processing based on pulse signals PLSA, PLSB, PLSC and PLSD and control signal CTL generated by the light intensity determination unit 36.

[0078] Figure 5 An example configuration of the adder unit 32 is shown. The adder unit 32 includes switches SWA, SWB, SWC and SWD, a logic OR circuit OR1 and an adder control unit CKT2.

[0079] The switch SWA is configured to turn the pulse signal PLSA on or off to the OR circuit OR1 based on a control signal supplied from the adder control unit CKT2. Specifically, when the switch SWA is on, it provides the pulse signal PLSA to the OR circuit OR1; when the switch SWA is off, it provides a low-level signal to the OR circuit OR1. The switch SWA includes, for example, an AND circuit or an OR circuit.

[0080] Similarly, switch SWB is configured to turn pulse signal PLSB on or off to OR circuit OR1 based on a control signal supplied from adder control unit CKT2. Switch SWC is configured to turn pulse signal PLSC on or off to OR circuit OR1 based on a control signal supplied from adder control unit CKT2. Switch SWD is configured to turn pulse signal PLSD on or off to OR circuit OR1 based on a control signal supplied from adder control unit CKT2.

[0081] The OR circuit OR1 is configured to generate the pulse signal PLS1 by performing a logical OR operation on the four signals supplied from switches SWA to SWD.

[0082] The addition control unit CKT2 sets the number NUM of the pulse signals PLS (pulse signals PLSA to PLSD) to be added based on the control signal CTL, and provides the control signal to each of the switches SWA to SWD based on the setting result.

[0083] Using this configuration, for example, when the control signal CTL indicates high light intensity, the addition control unit CKT2 sets the signal quantity NUM of the pulse signal PLS to be added to "1", and, for example, turns on switch SWA and turns off switches SWB to SWD. Therefore, the addition unit 32 generates a pulse signal PLS1 that becomes high during periods when the pulse signal PLSA is high and low during other periods. In other words, the addition unit 32 generates a pulse signal PLS1 with a waveform similar to that of the pulse signal PLSA.

[0084] Furthermore, for example, when the control signal CTL indicates low light intensity, the addition control unit CKT2 sets the signal quantity NUM of the pulse signal PLS to be added to "4" and turns on the switch SWA to SWD. Therefore, the addition unit 32 generates a pulse signal PLS1 that becomes high during the periods when the pulse signal PLSA is high, during the periods when the pulse signal PLSB is high, during the periods when the pulse signal PLSC is high, and during the periods when the pulse signal PLSD is high, and becomes low during other periods.

[0085] Selector 33A ( Figure 3 The selector is configured to select one of pulse signals PLSA and PLS1 based on the mode control signal SMODE, and output the selected pulse signal as pulse signal PLSA1. In this example, when the operating mode M is imaging mode MA, the mode control signal SMODE is at a low level "0", and when the operating mode M is ranging mode MB, the mode control signal SMODE is at a high level "1". Therefore, when the operating mode M is imaging mode MA, selector 33A selects pulse signal PLSA and outputs pulse signal PLSA as pulse signal PLSA1. Furthermore, when the operating mode M is ranging mode MB, selector 33A selects pulse signal PLS1 and outputs pulse signal PLS1 as pulse signal PLSA1.

[0086] Similarly, selector 33B is configured to select one of pulse signals PLSB and PLS1 based on the mode control signal SMODE, and output the selected pulse signal as pulse signal PLSB1. Selector 33C is configured to select one of pulse signals PLSC and PLS1 based on the mode control signal SMODE, and output the selected pulse signal as pulse signal PLSC1. Selector 33D is configured to select one of pulse signals PLSD and PLS1 based on the mode control signal SMODE, and output the selected pulse signal as pulse signal PLSD1.

[0087] Switch 34A is configured to turn the supply of pulse signal PLSA1 to counter 35A on or off based on clock signal CLKA. Specifically, when clock signal CLKA is high, switch 34A supplies pulse signal PLSA1 to counter 35A, and when clock signal CLKA is low, switch 34A supplies a low-level signal to counter 35A. Switch 34A includes, for example, an AND circuit or an OR circuit.

[0088] Similarly, switch 34B is configured to turn on or off the supply of pulse signal PLSB1 to counter 35B based on clock signal CLKB. Switch 34C is configured to turn on or off the supply of pulse signal PLSC1 to counter 35C based on clock signal CLKC. Switch 34D is configured to turn on or off the supply of pulse signal PLSD1 to counter 35D based on clock signal CLKD.

[0089] When the operating mode M is the imaging mode MA, the clock signals CLKA to CLKD supplied to switches 34A to 34D rise and fall at the same timing. Therefore, during the periods when clock signals CLKA to CLKD are high, switches 34A to 34D supply pulse signals PLSA1 to PLSD1 to counters 35A to 35D as is. Furthermore, when the operating mode M is the ranging mode MB, the clock signals CLKA to CLKD supplied to switches 34A to 34D are four-phase clock signals. In ranging mode MB, pulse signals PLSA1 to PLSD1 are each pulse signal PLS1 generated by adder 32. Therefore, switches 34A to 34D divide this pulse signal PLS1 into four pulse signals in a time-division manner based on the clock signals CLKA to CLKD.

[0090] Counter 35A is configured to increment the count value CNTA by performing counting processing based on the rising edge of a pulse signal supplied from switch 34A. Similarly, counter 35B is configured to increment the count value CNTB by performing counting processing based on the rising edge of a pulse signal supplied from switch 34B. Counter 35C is configured to increment the count value CNTC by performing counting processing based on the rising edge of a pulse signal supplied from switch 34C. Counter 35D is configured to increment the count value CNTD by performing counting processing based on the rising edge of a pulse signal supplied from switch 34D.

[0091] The light intensity determination unit 36 ​​is configured to determine the light intensity based on the count values ​​CNTA to CNTD of counters 35A to 35D. Specifically, when the operation mode M is imaging mode MA, the light intensity determination unit 36 ​​determines whether the light intensity is high based on the count values ​​CNTA to CNTD. The light intensity determination unit 36 ​​then provides the result of such determination to the adder unit 32 using the control signal CTL when the operation mode M changes from imaging mode MA to ranging mode MB.

[0092] Figure 6AAn example configuration of the light intensity determination unit 36 ​​is shown. In this example, the light intensity determination unit 36 ​​includes an adder ADD1 and a comparator CP1. The adder ADD1 is configured to calculate the total value of count values ​​CNT1 to CNT4. The comparator CP1 is configured to generate a control signal by comparing the total value obtained by the adder ADD1 with a predetermined threshold REF. In this example, the light intensity determination unit 36 ​​determines that the light intensity is high when the total value of count values ​​CNT1 to CNT4 is greater than the threshold REF, and determines that the light intensity is low when the total value of count values ​​CNT1 to CNT4 is less than the threshold REF.

[0093] Figure 6B Another configuration example of the light intensity determination unit 36 ​​is shown. In this example, the light intensity determination unit 36 ​​includes latches LTA to LTD and / or circuit OR2. Latch LTA is configured to set the output signal high based on the most significant bit (MSB) value in the bit data of the count value CNTA changing from "1" to "0". Similarly, latch LTB is configured to set the output signal high based on the most significant bit value in the bit data of the count value CNTB changing from "1" to "0". Latch LTC is configured to set the output signal high based on the most significant bit value in the bit data of the count value CNTC changing from "1" to "0". Latch LTD is configured to set the output signal high based on the most significant bit value in the bit data of the count value CNTD changing from "1" to "0". The OR circuit OR2 is configured to generate a control signal CTL by performing a logical OR operation on the signals provided from latches LTA to LTD. In this example, the light intensity determination unit 36 ​​determines that the light intensity is high when at least one of the count values ​​CNT1 to CNT4 has been counted once, and determines that the light intensity is low when none of the count values ​​CNT1 to CNT4 have been counted once.

[0094] Figure 6C Another configuration example of the light intensity determination unit 36 ​​is shown. In this example, the light intensity determination unit 36 ​​includes latches LTA to LTD and a logic AND circuit AND1. The AND circuit AND1 is configured to generate a control signal CTL by performing a logic AND operation on the signals provided from the latches LTA to LTD. In this example, the light intensity determination unit 36 ​​determines that the light intensity is high if all count values ​​CNT1 to CNT4 have been counted once, and determines that the light intensity is low if any count value from CNT1 to CNT4 has not been counted once.

[0095] Signal generation unit 22( Figure 2The unit is configured to generate clock signals CLKA to CLKD and mode control signal SMODE based on instructions from the optical detection control unit 25, and supply the clock signals CLKA to CLKD and mode control signal SMODE to multiple optical detection units U in the optical detection array 21.

[0096] The readout control unit 23 is configured to control the operation of supplying the count values ​​CNTA to CNTD generated in each of the plurality of optical detection units U in the optical detection array 21 to the signal processing unit 24 based on instructions from the optical detection control unit 25. For example, the readout control unit 23 controls the operation of the plurality of optical detection units U to sequentially select a row of optical detection units U and cause the selected optical detection unit U to provide the count values ​​CNTA to CNTD to the signal processing unit 24.

[0097] The signal processing unit 24 is configured to perform predetermined signal processing based on instructions from the light detection control unit 25. Specifically, when the operation mode M is imaging mode MA, the signal processing unit 24 generates image data of the captured image by performing predetermined image processing based on count values ​​CNTA to CNTD provided from each of the plurality of light detection units U in the light detection array 21. Furthermore, when the operation mode M is ranging mode MB, the signal processing unit 24 generates image data of the distance image by measuring the time from the emission of a light pulse L0 from the light emitting unit 11 to the detection of a reflected light pulse L1 by the light detection unit U, based on the count values ​​CNTA to CNTD provided from each of the plurality of light detection units U in the light detection array 21. Then, the signal processing unit 24 outputs the generated image data as data DT.

[0098] The light detection control unit 25 is configured to be based on the light from the control unit 14 ( Figure 1 The instructions provide control signals to the signal generation unit 22, the readout control unit 23, and the signal processing unit 24, and control the operation of the signal generation unit 22, the readout control unit 23, and the signal processing unit 24, thereby controlling the operation of the photodetector unit 20.

[0099] Here, the light receiving unit 31 corresponds to a specific example of the "light receiving unit" in this disclosure. The photodiode PD corresponds to a specific example of the "light receiving element" in this disclosure. The pulse signal PLS corresponds to a specific example of the "first pulse signal" in this disclosure. The switches SWA to SWD and / or the circuit OR1 correspond to a specific example of the "adder" in this disclosure. The pulse signal PLS1 corresponds to a specific example of the "second pulse signal" in this disclosure. The switches 34A to 34D correspond to a specific example of the "distribution unit" in this disclosure. The counter 35 corresponds to a specific example of the "counter" in this disclosure. The light intensity determination unit 36 ​​and the addition control unit CKT2 correspond to a specific example of the "control unit" in this disclosure. The ranging mode MB corresponds to a specific example of the "first operating mode" in this disclosure. The imaging mode MA corresponds to a specific example of the "second operating mode" in this disclosure.

[0100] [Operation and Work]

[0101] Next, the operation and function of the light detection system 1 according to this embodiment will be described.

[0102] (Overview of the overall operation)

[0103] First, refer to Figure 1 and Figure 2 An overview describing the overall operation of the optical detection system 1.

[0104] When the operating mode M is the imaging mode MA, the optical system 12 forms an image on the light receiving surface S of the light detection unit 20. The light detection unit 20 detects light. The control unit 14 supplies a control signal to the light detection unit 20 and controls the operation of the light detection unit 20, thereby controlling the imaging operation of the light detection system 1.

[0105] When the operating mode M is the ranging mode MB, the light emitting unit 11 emits a light pulse L0 towards the detection object OBJ. The optical system 12 forms an image on the light receiving surface S of the light detection unit 20. The light detection unit 20 detects the reflected light pulse L1. The control unit 14 provides control signals to the light emitting unit 11 and the light detection unit 20, and controls the operation of the light emitting unit 11 and the light detection unit 20, thereby controlling the distance measurement operation of the light detection system 1.

[0106] In the light detection unit 20, the light detection units U of the light detection array 21 generate count values ​​CNTA to CNTD by detecting light. The signal generation unit 22 generates clock signals CLKA to CLKD and a mode control signal SMODE, and supplies the clock signals CLKA to CLKD and the mode control signal SMODE to the plurality of light detection units U. The readout control unit 23 controls the operation of supplying the count values ​​CNTA to CNTD generated by each of the plurality of light detection units U in the light detection array 21 to the signal processing unit 24. The signal processing unit 24 performs predetermined signal processing based on the count values ​​CNTA to CNTD provided from each of the plurality of light detection units U in the light detection array 21 to generate image data, and outputs the generated image data as data DT. The light detection control unit 25 controls the operation of the signal generation unit 22, the readout control unit 23, and the signal processing unit 24 by supplying control signals to the signal generation unit 22, the readout control unit 23, and the signal processing unit 24 based on the instructions from the control unit 14, thereby controlling the operation of the light detection unit 20.

[0107] (Detailed instructions)

[0108] Figure 7 An operational example of the light detection unit U is shown when the operating mode M is the imaging mode MA. Figure 7 The diagram illustrates selectors 33A to 33D and switches 34A to 34D, using switches to indicate their states. In imaging mode MA, selector 33A outputs pulse signal PLSA as pulse signal PLSA1. Selector 33B outputs pulse signal PLSB as pulse signal PLSB1. Selector 33C outputs pulse signal PLSC as pulse signal PLSC1. Selector 33D outputs pulse signal PLSD as pulse signal PLSD1. Switches 34A to 34D are then simultaneously turned on or off based on clock signals CLKA to CLKD. Figure 7 In the middle, switches 34A to 34D are turned on.

[0109] Figure 8 An example of the operation of the light detection unit 20 during imaging operation is shown. (A) shows the waveform of the mode control signal SMODE. (B) to (E) show the waveforms of the clock signals CLKA to CLKD, respectively. (F) shows the operation of the readout control unit 23.

[0110] When performing an imaging operation, the signal generation unit 22 changes the mode control signal SMODE to a low level. Figure 8 (A)). In each of the plurality of optical detection units U, the optical receiving units 31A to 31D generate pulse signals PLSA to PLSD respectively through the detection light. Therefore, as Figure 7As shown, selectors 33A to 33D output pulse signals PLSA to PLSD respectively as pulse signals PLSA1 to PLSD1. Signal generation unit 22 then generates clock signals CLKA to CLKD that simultaneously vary between high and low levels. Figure 8 (B) to (E)).

[0111] At time t11, the frame period F begins. At this time t11, the signal generation unit 22 changes the clock signals CLKA to CLKD from low to high level. Figure 8 (B) to (E)). Therefore, during the period from timing t11 to timing t12, switch 34A provides pulse signal PLSA1 to counter 35A, switch 34B provides pulse signal PLSB1 to counter 35B, switch 34C provides pulse signal PLSC1 to counter 35C, and switch 34D provides pulse signal PLSD1 to counter 35D.

[0112] Counter 35A then performs counting processing based on the rising edge of the pulse signal PLSA1 supplied from switch 34A to increment the count value CNTA. Similarly, counter 35B performs counting processing based on the rising edge of the pulse signal PLSB1 supplied from switch 34B to increment the count value CNTB. Counter 35C performs counting processing based on the rising edge of the pulse signal PLSC1 supplied from switch 34C to increment the count value CNTC. Counter 35D performs counting processing based on the rising edge of the pulse signal PLSD1 supplied from switch 34D to increment the count value CNTD.

[0113] Then, at time t12, the signal generation unit 22 changes the clock signals CLKA to CLKD from high level to low level. Figure 8 (B) to (E)). Therefore, switches 34A to 34D stop supplying pulse signals PLSA1 to PLSD1 to counters 35A to 35D.

[0114] Then, during the time period from timing t12 to timing t13, the readout control unit 23 executes readout control CR, thereby controlling the operation of the plurality of optical detection units U to supply the count values ​​CNTA to CNTD generated in each of the plurality of optical detection units U to the signal processing unit 24. Afterwards, the count values ​​CNTA to CNTD in counters 35A to 35D are reset. Then, at this timing t13, the frame period F ends.

[0115] The light detection unit 20 repeats this operation from timing t11 to timing t13. The signal processing unit 24 then performs predetermined image processing based on the count values ​​CNTA to CNTD provided from each of the plurality of light detection units U to generate data of the captured image, and outputs the generated data as data DT.

[0116] Figure 9 An operational example of the optical detection unit is shown when the operating mode M is the ranging mode MB. In the ranging mode MB, selector 33A outputs pulse signal PLS1 as pulse signal PLSA1, selector 33B outputs pulse signal PLS1 as pulse signal PLSB1, selector 33C outputs pulse signal PLS1 as pulse signal PLSC1, and selector 33D outputs pulse signal PLS1 as pulse signal PLSD1. Then, based on the clock signals CLKA to CLKD that constitute the four-phase clock signal, switches 34A to 34D are turned on or off in a time-division manner. Figure 9 In the middle, switch 34A is turned on, and switches 34B to 34D are turned off.

[0117] Figure 10 An example of the operation of the light detection unit 20 during ranging operations is shown. (A) shows the waveform of the mode control signal SMODE. (B) shows the waveform of the light emitted from the light emitting unit 11. (C) to (F) show the waveforms of the clock signals CLKA to CLKD, respectively. (G) shows the waveform of the control signal CTL (control signal CTL1) in a certain light detection unit U (light detection unit U1). (H) shows the signal quantity NUM (signal quantity NUM1) of the pulse signal PLS to be added by the adder 32 of the light detection unit U1. (I) shows the waveform of the control signal CTL (control signal CTL2) in another light detection unit U (light detection unit U2). (J) shows the signal quantity NUM (signal quantity NUM2) of the pulse signal PLS to be added by the adder 32 of the light detection unit U2. (K) shows the operation of the readout control unit 23.

[0118] In the case of performing a ranging operation, in order to prepare for the ranging operation, the signal generation unit 22 changes the mode control signal SMODE to a low level similar to that of the imaging operation. Figure 10 (A)). Therefore, it is similar to the imaging operation ( Figure 7 Selectors 33A to 33D output pulse signals PLSA to PLSD respectively as pulse signals PLSA1 to PLSD1.

[0119] Then, at time t21, the signal generation unit 22 changes the clock signals CLKA to CLKD from low level to high level. Figure 10 (C) to (F)). Therefore, during the time period from timing t21 to timing t22, switch 34A provides pulse signal PLSA1 to counter 35A, switch 34B provides pulse signal PLSB1 to counter 35B, switch 34C provides pulse signal PLSC1 to counter 35C, and switch 34D provides pulse signal PLSD1 to counter 35D.

[0120] During the time period from time t21 to time t22, the light emitting part 11 may emit light or may not emit light. Figure 10 (B)

[0121] Then, counter 35A performs counting processing based on the rising edge of the pulse signal PLSA1 supplied from switch 34A to increment the count value CNTA. Similarly, counter 35B performs counting processing based on the rising edge of the pulse signal PLSB1 supplied from switch 34B to increment the count value CNTB. Counter 35C performs counting processing based on the rising edge of the pulse signal PLSC1 supplied from switch 34C to increment the count value CNTC. Counter 35D performs counting processing based on the rising edge of the pulse signal PLSD1 supplied from switch 34D to increment the count value CNTD.

[0122] Then, at time t22, the signal generation unit 22 changes the clock signals CLKA to CLKD from high level to low level. Figure 10 (C) to (F)). Therefore, switches 34A to 34D stop supplying pulse signals PLSA1 to PLSD1 to counters 35A to 35D.

[0123] Then, after timing t22, the light intensity determination unit 36 ​​determines the light intensity based on the count values ​​CNTA to CNTD of counters 35A to 35D. Based on the result of this determination, the addition control unit CKT2 of the addition unit 32 sets the number NUM of the pulse signals PLS that will undergo addition processing of four pulse signals PLS (pulse signals PLSA to PLSD).

[0124] In this example, in the light detection unit U1, the light intensity determination unit 36 ​​determines that the obtained light intensity is high based on the count values ​​CNTA to CNTD of counters 35A to 35D, and changes the control signal CTL to a high level at time t23. Figure 10 (G)). The addition control unit CKT2 of the addition unit 32 sets the signal quantity NUM1 of the pulse signal PLS to be added to "1" based on the control signal CTL1. Figure 10 (H) Therefore, for example, when the addition control unit CKT2 turns on the switch SWA and turns off the switch SWB to SWD, the addition unit 32 generates a pulse signal PLS1 with a waveform similar to that of the pulse signal PLSA.

[0125] Furthermore, in the light detection unit U2, the light intensity determination unit 36 ​​determines that the obtained light intensity is low based on the count values ​​CNTA to CNTD of the counters 35A to 35D, and changes the control signal CTL2 to a low level at time t23. Figure 10(I)). The addition control unit CKT2 of the addition unit 32 sets the signal quantity NUM2 of the pulse signal PLS to be added to "4" based on the control signal CTL2. Figure 10 (J) Therefore, the addition control unit CKT2 turns on the switch SWA to SWD, and the addition unit 32 generates the pulse signal PLS1 based on the pulse signals PLSA to PLSD.

[0126] Figure 11 An example of an optical receiver 31 in multiple optical detection units U that generates a pulse signal PLS to be added is shown. In this example, the optical receivers 31 are arranged in 2 rows and 2 columns within the optical detection unit U. The shaded optical receivers 31 represent those that generate the pulse signal PLS to be added, while the unshaded optical receivers 31 generate the pulse signal PLS that does not undergo addition. In this example, in one optical detection unit U, one pulse signal PLS output from one of the four optical receivers 31 is added, and in another optical detection unit U, four pulse signals PLS output from the four optical receivers 31 are added. Thus, the number of signals NUM is set individually in each of the multiple optical detection units U.

[0127] Then, during the time period from time t23 to time t24, the readout control unit 23 executes readout control CR, thereby controlling the operation of the plurality of photodetectors U to supply the signal processing unit 24 with the count values ​​CNTA to CNTD generated by each of the plurality of photodetectors U. Figure 10 (K)). Thereafter, the count values ​​CNTA to CNTD in counters 35A to 35D are reset.

[0128] Then, at time t24, the signal generation unit 22 changes the mode control signal SMODE from low level to high level. Figure 10 (A) Therefore, selectors 33A to 33D output the pulse signals generated by the adder 32 as pulse signals PLSA1 to PLSD1, respectively.

[0129] Then, during the time period from time t25 to time t30 (detection period PDET), the optical detection system 1 repeatedly emits optical pulses L0 and repeatedly detects the reflected optical pulses L1 reflected by the detection object OBJ.

[0130] Specifically, during the time period from time t25 to time t26, the light emitting unit 11 emits light ( Figure 10(B) The signal generation unit 22 changes the clock signal CLKA to a high level during the time period from timing t25 to timing t26, changes the clock signal CLKB to a high level during the time period from timing t26 to timing t27, changes the clock signal CLKC to a high level during the time period from timing t27 to timing t28, and changes the clock signal CLKD to a high level during the time period from timing t28 to timing t29. Therefore, switch 34A provides pulse signal PLSA1 (pulse signal PLS1) to counter 35A during the time period from time t25 to time t26, switch 34B provides pulse signal PLSB1 (pulse signal PLS1) to counter 35B during the time period from time t26 to time t27, switch 34C provides pulse signal PLSC1 (pulse signal PLS1) to counter 35C during the time period from time t27 to time t28, and switch 34D provides pulse signal PLSD1 (pulse signal PLS1) to counter 35D during the time period from time t28 to time t29. Then, counter 35A performs counting processing based on the rising edge of pulse signal PLSA1 supplied from switch 34A during the time period from time t25 to time t26 to increment the count value CNTA. Counter 35B performs counting based on the rising edge of the pulse signal PLSB1 supplied from switch 34B during the time period from time t26 to time t27, incrementing the count value CNTB. Counter 35C performs counting based on the rising edge of the pulse signal PLSC1 supplied from switch 34C during the time period from time t27 to time t28, incrementing the count value CNTC. Counter 35D performs counting based on the rising edge of the pulse signal PLSD1 supplied from switch 34D during the time period from time t28 to time t29, incrementing the count value CNTD.

[0131] The optical detection unit U repeats the operation from timing t25 to timing t29. Therefore, counter 35A performs counting processing to generate the count value CNTA during multiple periods when the clock signal CLKA is high, counter 35B performs counting processing to generate the count value CNTB during multiple periods when the clock signal CLKB is high, counter 35C performs counting processing to generate the count value CNTC during multiple periods when the clock signal CLKC is high, and counter 35D performs counting processing to generate the count value CNTD during multiple periods when the clock signal CLKD is high.

[0132] Then, during the time period from time t30 to time t31, the readout control unit 23 executes readout control CR, thereby controlling the multiple photodetector units U to supply the signal processing unit 24 with the count values ​​CNTA to CNTD generated by each of the multiple photodetector units U. Figure 10(K)). Thereafter, the count values ​​CNTA to CNTD in counters 35A to 35D are reset.

[0133] The light detection system 1 repeats the operation from time t25 to time t31. The signal processing unit 24 generates distance image data based on the count values ​​CNTA to CNTD provided from each of the plurality of light detection units U by measuring the time from the emission of light pulse L0 by the light emitting unit 11 to the detection of reflected light pulse L1 by the light detection unit U, and outputs the generated data as data DT.

[0134] Therefore, in the optical detection system 1, an addition process is performed based on multiple pulse signals PLS (pulse signals PLSA to PLSD) generated by multiple optical receivers 31 to generate a pulse signal PLS1. Then, an allocation process is performed based on clock signals CLKA to CLKD to distribute the pulse signal PLS1 into multiple pulse signals in a time-division manner, and a counting process is performed based on each of the multiple pulse signals. Therefore, for example, by collecting pulses from multiple pulse signals PLS through the addition process to generate a single pulse signal PLS1 comprising multiple pulses, the number of pulses in the pulse signal PLS1 can be increased compared to the case without the addition process. Therefore, in the optical detection system 1, the detection accuracy during ranging operations can be improved.

[0135] Furthermore, in the optical detection system 1, one or more pulse signals PLS (pulse signals PLSA to PLSD) are selected from multiple pulse signals PLS based on the control signal CTL, and addition processing is performed based on the selected pulse signals PLS. Additionally, the number of signals for the one or more pulse signals is set based on the corresponding count values ​​of multiple counters. Therefore, for example, in the case of high light intensity, the possibility of decreased detection accuracy during distance measurement operations can be reduced. In other words, in the case of high light intensity, the four optical receivers 31A to 31D can generate pulse signals PLSA to PLSD that include pulses with slightly offset timings from each other. For example, if addition processing is performed consistently based on the four pulse signals PLSA to PLSD, there is a possibility that the pulses of such pulse signals PLSA to PLSD may be combined into a single pulse in the pulse signal PLS1 generated by the addition processing. In this case, the detection accuracy during distance measurement operations decreases. In contrast, in the optical detection system 1, for example, in the case of high light intensity, the number of pulse signals PLS that need to undergo addition processing can be reduced, and as a result, the possibility of synthesizing pulse signals PLSA to PLSD can be reduced. As a result, in optical detection system 1, the possibility of decreased detection accuracy during ranging operations can be reduced.

[0136] Furthermore, in the optical detection system 1, one or more pulse signals PLS (pulse signals PLSA to PLSD) are selected from multiple pulse signals PLS based on the control signal CTL, and addition processing is performed based on the one or more selected pulse signals PLS. Therefore, for example, in the case of high light intensity, the drop in power supply voltage can be suppressed. In other words, for example, when addition processing is performed consistently based on four pulse signals PLSA to PLSD in a state of high light intensity, multiple pulses may be generated in a short period of time in the pulse signal PLS1 generated by the addition processing. In many optical detection units U, when pulses are generated in a short period of time in the pulse signal PLS1, a large power supply current flows through in a short period of time, and the power supply voltage temporarily drops due to the so-called IR drop. In contrast, in the optical detection system 1, for example in the case of high light intensity, the number of pulse signals PLS that need to undergo addition processing can be reduced, and the possibility of generating multiple pulses in the pulse signal PLS1 in a short period of time can be reduced. This makes it possible to reduce the possibility of a temporary drop in power supply voltage. As a result, in the optical detection system 1, the possibility of, for example, malfunction can be reduced, and the possibility of a decrease in detection accuracy during ranging operations can be reduced.

[0137] [Effect]

[0138] As described above, in this embodiment, an addition process is performed based on multiple pulse signals generated by multiple optical receivers to generate a pulse signal. Then, an allocation process is performed to divide the pulse signal into multiple pulse signals in a time-division manner based on a clock signal, and a counting process is performed based on each of the multiple pulse signals. This allows for improved detection accuracy in distance measurement operations.

[0139] In this embodiment, one or more pulse signals are selected from multiple pulse signals based on a control signal, and an addition process is performed based on the selected pulse signals to generate a pulse signal. Furthermore, the number of pulse signals is set based on the corresponding count values ​​of multiple counters. This reduces the possibility of decreased detection accuracy during distance measurement operations.

[0140] In this embodiment, one or more pulse signals are selected from multiple pulse signals based on a control signal, and an addition process is performed based on the selected one or more pulse signals to generate a pulse signal. This reduces the possibility of a temporary drop in power supply voltage. Therefore, it reduces the possibility of a decrease in detection accuracy during distance measurement operations.

[0141] [Variation Example 1]

[0142] In the above embodiment, the light intensity determination unit 36 ​​determines whether the light intensity is high or low, and the addition control unit CKT2 of the addition unit 32 sets the signal number NUM of the pulse signal PLS (pulse signals PLSA to PLSD) to be added based on the result of this determination, but this is not limiting. The light detection unit U of this modified example will be described in detail below. The light detection unit U of this modified example is similar to that of the above embodiment ( Figure 3 Similarly, it has a light intensity determination unit 36B and an addition unit 32B.

[0143] Figure 12 An example configuration of the light intensity determination unit 36B is shown. The light intensity determination unit 36B includes an adder ADD1, a comparator CP1, and a threshold setting unit CKT3. In this example, the threshold setting unit CKT3 is configured to sequentially generate three thresholds REF1 to REF3. The comparator CP1 compares the total value obtained by the adder ADD1 with the three thresholds REF1 to REF3 sequentially.

[0144] Figure 13 An operational example of the adder unit 32B is shown. When the control signal CTL indicates that the total value of counts CNTA to CNTD is lower than the threshold REF1, the adder control unit CKT2B of the adder unit 32B sets the signal quantity NUM of the pulse signal PLS to be added to "4". Furthermore, when the control signal CTL indicates that the total value of counts CNTA to CNTD is higher than the threshold REF1 and lower than the threshold REF2, the adder control unit CKT2B sets the signal quantity NUM of the pulse signal PLS to be added to "3". Furthermore, when the control signal CTL indicates that the total value of counts CNTA to CNTD is higher than the threshold REF2 and lower than the threshold REF3, the adder control unit CKT2B sets the signal quantity NUM of the pulse signal PLS to be added to "2". Furthermore, when the control signal CTL indicates that the total value of counts CNTA to CNTD is higher than the threshold REF3, the adder control unit CKT2B sets the signal quantity NUM of the pulse signal PLS to be added to "1".

[0145] [Variation Example 2]

[0146] The photodetector 20 according to the above embodiment can be formed on one semiconductor substrate or on multiple semiconductor substrates. The following describes in detail the case where the photodetector 20 is formed on two semiconductor substrates as an example.

[0147] Figure 14An implementation example of the light detection unit 20 is shown. In this example, the light detection unit 20 is formed on two semiconductor substrates 101 and 102. Semiconductor substrate 101 is disposed on the light receiving surface S side of the light detection unit 20, and semiconductor substrate 102 is disposed on the side opposite to the light receiving surface S of the light detection unit 20. Semiconductor substrates 101 and 102 overlap each other. The wiring of semiconductor substrate 101 and the wiring of semiconductor substrate 102 are coupled to each other through wiring 103. For example, a metal bond such as Cu-Cu can be used for wiring 103. A photodetector unit U is disposed above the two semiconductor substrates 101 and 102.

[0148] Figure 15A An example configuration of the optical receiver 31A is shown. The optical receiver 31A has the same... Figure 4A The light receiver 31A shown has the same circuit configuration. In this example, the light receiver 31A is disposed above two semiconductor substrates 101 and 102. Specifically, a photodiode PD is disposed on semiconductor substrate 101, and a resistor R1 and an inverter IV1 are disposed on semiconductor substrate 102. The cathode of the photodiode PD is coupled to the other end of the resistor R1 and the input terminal of the inverter IV1 via wiring 103.

[0149] Figure 15B Another configuration example of the optical receiver 31A is shown. This optical receiver 31A has the same... Figure 4B The light receiver 31A shown has the same circuit configuration. In this example, the light receiver 31A is disposed on two semiconductor substrates 101 and 102. Specifically, a photodiode PD is disposed on semiconductor substrate 101, and a transistor MP1, an inverter IV1, and a control circuit CKT1 are disposed on semiconductor substrate 102. The photodiode PD has a cathode coupled to the drain of transistor MP1 and the input terminal of inverter IV1 via wiring 103.

[0150] The adder 32, selectors 33A to 33D, switches 34A to 34D, counters 35A to 35D, and light intensity determination unit 36 ​​in the light detection unit U are disposed, for example, on the semiconductor substrate 102.

[0151] [Variation Example 3]

[0152] In the above embodiments, both imaging and ranging operations are performed, but this is not limiting. Alternatively, for example, only the distance measurement operation may be performed. The optical detection system 1D of this modified example will now be described in detail.

[0153] Figure 16An example configuration of a light detection system 1D is shown. The light detection system 1D includes a light detection unit 20D and a control unit 14D. The light detection unit 20D is configured to detect light based on commands from the control unit 14D. The control unit 14D is configured to provide control signals to the light emitting unit 11 and the light detection unit 20D and control the operation of the light emitting unit 11 and the light detection unit 20D, thereby controlling the operation of the light detection system 1D.

[0154] Figure 17 An example configuration of the light detection unit 20D is shown. The light detection unit 20D includes a light detection array 21D, a signal generation unit 22D, a readout control unit 23, a signal processing unit 24D, and a light detection control unit 25.

[0155] The optical detection array 21D includes multiple optical detection units U arranged in a matrix.

[0156] Figure 18 An example configuration of the light detection unit U is shown. The light detection unit U has multiple light receiving units 31 (four light receiving units 31A to 31D in this example), an adder 32, multiple switches 34 (four switches 34A to 34D in this example), multiple counters 35 (four counters 35A to 35D in this example), and a light intensity determination unit 36.

[0157] The adder 32 generates a pulse signal PLS1 by performing addition processing based on pulse signals PLSA, PLSB, PLSC, and PLSD, and a control signal CTL generated by the light intensity determination unit 36. The adder 32 then provides the generated pulse signal PLS1 to switches 34A to 34D.

[0158] Switch 34A switches the pulse signal PLS1 to counter 35A on or off based on clock signal CLKA. Similarly, switch 34B switches the pulse signal PLS1 to counter 35B on or off based on clock signal CLKB. Switch 34C switches the pulse signal PLS1 to counter 35C on or off based on clock signal CLKC. Switch 34D switches the pulse signal PLS1 to counter 35D on or off based on clock signal CLKD. Switches 34A to 34D divide the pulse signal PLS1 into four pulse signals in a time-division manner based on clock signals CLKA to CLKD.

[0159] Signal generation unit 22D ( Figure 17 It is configured to generate clock signals CLKA to CLKD based on instructions from the optical detection control unit 25, and provide the clock signals CLKA to CLKD to multiple optical detection units U in the optical detection array 21D.

[0160] The signal processing unit 24D is configured to generate distance image data by measuring the time from the emission of a light pulse L0 from the light emitting unit 11 to the detection of a reflected light pulse L1 by the light detection unit U, based on count values ​​CNTA to CNTD provided from each of the plurality of light detection units U in the light detection array 21. Then, the signal processing unit 24D outputs the generated data as data DT.

[0161] Figure 19 An operational example of the light detection unit 20D is shown. (A) shows the waveform of the light emitted from the light emitting unit 11. (B) to (E) show the waveforms of the clock signals CLKA to CLKD, respectively. (F) shows the waveform of the control signal (control signal CTL1) in a certain light detection unit U (light detection unit U1). (G) shows the signal quantity NUM (signal quantity NUM1) of the pulse signal PLS to be added by the adder 32 of the light detection unit U1. (H) shows the waveform of the control signal CTL (control signal CTL2) in another light detection unit U (light detection unit U2). (I) shows the signal quantity NUM (signal quantity NUM2) of the pulse signal PLS to be added by the adder 32 of the light detection unit U2. (J) shows the operation of the readout control unit 23.

[0162] During the time period from time t41 to time t42 (detection period PDET), the above-described implementation method ( Figure 10 Similarly, the optical detection system 1D repeatedly emits optical pulses L0 and repeatedly detects the reflected optical pulses L1 reflected by the object being detected OBJ.

[0163] Then, after timing t42, the light intensity determination unit 36 ​​determines the light intensity based on the count values ​​CNTA to CNTD of counters 35A to 35D. The addition control unit CKT2 of the addition unit 32 sets the number NUM of pulse signals PLS that will undergo addition processing of four pulse signals PLS (pulse signals PLSA to PLSD) based on the result of this determination.

[0164] In this example, in the light detection unit U1, the light intensity determination unit 36 ​​determines that the obtained light intensity is high based on the count values ​​CNTA to CNTD of counters 35A to 35D, and changes the control signal CLT1 to a high level at time t43. Figure 19 (F)). The addition control unit CKT2 of the addition unit 32 sets the signal quantity NUM1 of the pulse signal PLS to be added to "1" based on the control signal CTL1. Figure 19 (G). Therefore, for example, when the addition control unit CKT2 turns on the switch SWA and turns off the switch SWB to SWD, the addition unit 32 generates a pulse signal PLS1 with a waveform similar to that of the pulse signal PLSA.

[0165] Furthermore, in the light detection unit U2, the light intensity determination unit 36 ​​determines that the obtained light intensity is low based on the count values ​​CNTA to CNTD of the counters 35A to 35D, and changes the control signal CTL2 to a low level at time t43. Figure 19 (H)). The addition control unit CKT2 of the addition unit 32 sets the signal quantity NUM2 of the pulse signal PLS to be added to "4" based on the control signal CTL2. Figure 19 (I)). Therefore, the addition control unit CKT2 turns on the switch SWA to SWD, and the addition unit 32 generates the pulse signal PLS1 based on the pulse signal PLSA to PLSD.

[0166] Then, during the time period from time t44 to time t45, the readout control unit 23 executes readout control CR, thereby controlling the operation of supplying the count values ​​CNTA to CNTD generated by each of the multiple photodetector units U to the signal processing unit 24. Afterwards, the count values ​​CNTA to CNTD in counters 35A to 35D are reset.

[0167] During the time period from time t45 to time t46 (detection period PDET), the optical detection system 1D repeatedly emits light pulses L0 and repeatedly detects the reflected light pulses L1 reflected by the object being detected OBJ.

[0168] Then, after timing t46, the light intensity determination unit 36 ​​determines the light intensity based on the count values ​​CNTA to CNTD of counters 35A to 35D. Then, based on the result of this determination, the addition control unit CKT2 of the addition unit 32 sets the number NUM of the pulse signals PLS that will undergo addition processing of four pulse signals PLS (pulse signals PLSA to PLSD).

[0169] In this example, in the light detection unit U1, the light intensity determination unit 36 ​​determines that the obtained light intensity is high based on the count values ​​CNTA to CNTD of counters 35A to 35D, and changes the control signal CTL to a high level at time t47. Figure 19 (F)). The addition control unit CKT2 of the addition unit 32 sets the signal quantity NUM1 of the pulse signal PLS to be added to "1" based on the control signal CTL1. Figure 19 (G). Therefore, for example, when the addition control unit CKT2 turns on the switch SWA and turns off the switch SWB to SWD, the addition unit 32 generates a pulse signal PLS1 with a waveform similar to that of the pulse signal PLSA.

[0170] Furthermore, in the light detection unit U2, the light intensity determination unit 36 ​​determines that the obtained light intensity is high based on the count values ​​CNTA to CNTD of the counters 35A to 35D, and changes the control signal CTL2 to a low level at time t47. Figure 19 (H)). The addition control unit CKT2 of the addition unit 32 sets the signal quantity NUM2 of the pulse signal PLS to be added to "1" based on the control signal CTL2. Figure 19 (I) Therefore, the addition control unit CKT2 turns on switch SWA and turns off switch SWB to SWD, and the addition unit 32 generates a pulse signal PLS1 with a waveform similar to that of the pulse signal PLSA.

[0171] Then, during the time period from timing t48 to timing t49, the readout control unit 23 executes readout control CR, thereby controlling the operation of supplying the count values ​​CNTA to CNTD generated by each of the multiple photodetector units U to the signal processing unit 24D. Afterwards, the count values ​​CNTA to CNTD in counters 35A to 35D are reset.

[0172] The signal processing unit 24D generates distance image data based on the count values ​​CNTA to CNTD provided from each of the multiple light detection units U by measuring the time from the emission of light pulse L0 from the light emitting unit 11 to the detection of reflected light pulse L1 by the light detection unit U, and outputs the generated data as data DT.

[0173] Even with such a configuration, detection accuracy in ranging operations can be improved. In this example, in the optical detection system 1D that only performs ranging operations, the signal quantity NUM is determined based on the count values ​​CNTA to CNTD during the ranging operation; however, in an optical detection system capable of performing both imaging and ranging operations, the signal quantity NUM can be determined based on the count values ​​CNTA to CNTD during the ranging operation.

[0174] In this example, in the light receiving sections 31A to 31D, for example, as Figure 4A As shown, an inverter IV1 is provided, but this is not limiting. For example, an inverter IV1 may not be provided. The light detection unit U in this variant example is... Figure 18 The structures shown are identical, including light receiving sections 41A to 41D and an adding section 42. For example... Figure 20 As shown, the light receiving unit 41A includes a photodiode PD and a resistor R1. The adding unit 42 includes switches SWA, SWB, SWC and SWD, a NAND circuit ND1, and an adding control unit CKT2, as shown. Figure 21 As shown in the diagram, the NAND circuit ND1 is configured to generate the pulse signal PLS1 by calculating the NAND of the four signals provided from switches SWA to SWD.

[0175] [Variation Example 4]

[0176] In the above embodiments, such as Figure 4A and Figure 4B As shown, each of the light receiving units 31A to 31D includes a photodiode PD, but this is not limiting. Instead, for example, as... Figure 22A and Figure 22B As shown, each of the light receiving units 31A to 31D may include a plurality of photodiodes PD (in this example, four photodiodes PD1 to PD4). The photodiodes PD1 to PD4 are coupled in parallel to each other, and each of the photodiodes PD1 to PD4 has an anode supplied with a power supply voltage VSS and a cathode coupled to node N1.

[0177] [Variation Example 5]

[0178] In the above embodiments, the configuration of counter 35 is fixed, but this is not limiting. Instead, for example, the configuration of counter 35 can be variable. The light detection unit U of this modified example will be described in detail below.

[0179] The light detection unit U has the same characteristics as the light detection unit U according to the above embodiment. Figure 3 The optical detection unit U in this modified example has a similar structure to the one in the original example. It also has multiple switches, and by changing these switches, various structures can be achieved. The equivalent circuit configurations achieved by changing the switches are described below.

[0180] Figure 23 An example of the equivalent circuit configuration in the imaging mode MA of the light detection unit U according to this modification is shown. Figure 23 The addition unit 32, selectors 33A to 33D, switches 34A to 34D, and light intensity determination unit 36 ​​are not shown. In this example, counter 35A includes a low-order counter 35A1 and a high-order counter 35A2. Counter 35B includes a low-order counter 35B1 and a high-order counter 35B2. Counter 35C includes a low-order counter 35C1 and a high-order counter 35C2. Counter 35D includes a low-order counter 35D1 and a high-order counter 35D2. For example, when counter 35A is an 8-bit counter, each of counters 35A1 and 35A2 is a 4-bit counter. As in the above embodiment, counter 35A performs counting based on pulse signal PLSA, counter 35B performs counting based on pulse signal PLSB, counter 35C performs counting based on pulse signal PLSC, and counter 35D performs counting based on pulse signal PLSD.

[0181] Figure 24An example of the equivalent circuit configuration of the optical detection unit U in ranging mode MB (ranging mode MB1) according to this modification is shown. Figure 24 Selectors 33A to 33D and light intensity determination unit 36 ​​are not shown. In this example, as in the embodiment described above, switches 34A to 34D divide the pulse signal PLS1 into four pulse signals in a time-division manner based on clock signals CLKA to CLKD that constitute the four-phase clock signal.

[0182] Figure 25 An example of an equivalent circuit configuration is shown under another ranging mode MB (ranging mode MB2) of the optical detection unit U according to this modification. Figure 25 Selectors 33A to 33D and light intensity determination unit 36 ​​are not shown in this example. Figure 23 and Figure 24 The four counters 35A, 35B, 35C, and 35D shown are reconfigured into eight counters 35A1, 35A2, 35B1, 35B2, 35C1, 35C2, 35D1, and 35D2. The light detection unit U includes switches 44A to 44H. Switch 44A is configured to turn the supply of pulse signal PLS1 to counter 35A1 on or off based on clock signal CLKA. Switch 44B is configured to turn the supply of pulse signal PLS1 to counter 35A2 on or off based on clock signal CLKB. Switch 44C is configured to turn the supply of pulse signal PLS1 to counter 35B1 on or off based on clock signal CLKC. Switch 44D is configured to turn the supply of pulse signal PLS1 to counter 35B2 on or off based on clock signal CLKD. Switch 44E is configured to turn the supply of pulse signal PLS1 to counter 35C1 on or off based on clock signal CLKE. Switch 44F is configured to turn the supply of pulse signal PLS1 to counter 35C2 on or off based on clock signal CLKF. Switch 44G is configured to turn the supply of pulse signal PLS1 to counter 35D1 on or off based on clock signal CLKG. Switch 44H is configured to turn the supply of pulse signal PLS1 to counter 35D2 on or off based on clock signal CLKH. In this example, switches 44A to 44H divide pulse signal PLS1 into eight pulse signals in a time-division manner based on clock signals CLKA to CLKH that constitute an eight-phase clock signal. Therefore, for example, the detection accuracy in distance measurement operations can be improved to ranging mode MB1 ( Figure 24 The detection accuracy is twice that of the previous method, or the range of measurable distances is expanded to the ranging mode MB1. Figure 24 Twice the distance range in ).

[0183] Figure 26An example of an equivalent circuit configuration in another ranging mode MB (ranging mode MB3) of the optical detection unit U according to this modification is shown. Figure 26 Selectors 33A to 33D and light intensity determination unit 36 ​​are not shown in this example. Figure 25 The eight counters 35A1, 35A2, 35B1, 35B2, 35C1, 35C2, 35D1, and 35D2 shown are reconfigured into two counters 35AB and 35CD. In counter 35AB, counters 35A1, 35A2, 35B1, and 35B2 are coupled in ascending order. In counter 35CD, counters 35C1, 35C2, 35D1, and 35D2 are coupled in ascending order. The optical detection unit U includes switches 54A and 54B. Switch 54A is configured to turn on or off the supply of pulse signal PLS1 to counter 35AB based on clock signal CLKA. Switch 54B is configured to turn on or off the supply of pulse signal PLS1 to counter 35CD based on clock signal CLKB. In this example, switches 54A and 54B divide the pulse signal PLS1 into two pulse signals in a time-division manner based on clock signals CLKA and CLKB, which constitute the two-phase clock signal. Therefore, for example, the counting range of each of counters 35AB and 35CD can be extended to ranging mode MB1. Figure 24 The count range in () is twice the value. Therefore, for example, it is possible to increase... Figure 10 The detection period PDET shown can reduce the number of readout control CR cycles.

[0184] Therefore, in this example, the optical detection unit U of this variant can operate in one imaging mode MA and three ranging modes MB1 to MB3. Thus, an appropriate ranging mode MB can be selected according to the application. It should be noted that in this example, three ranging modes MB1 to MB3 are provided, but this is not limiting. For example, one or two of these ranging modes MB can be omitted, or another ranging mode MB can be provided.

[0185] [Variation Example 6]

[0186] In the above embodiments, a method having Figure 4A and Figure 4B The circuit configuration shown includes optical receivers 31A to 31D, but this is not limiting. A modified example will be described in detail below.

[0187] Figure 27An example configuration of the light receiver 31A according to this modification is shown. The light receiver 31A includes a photodiode PD, transistors MP1 to MP3 and MN4, inverters IV2 and IV3, a delay circuit DEL, a NAND circuit ND2, and an inverter IV4. Transistors MP1 to MP3 are P-type MOS transistors, and transistor MN4 is an N-type MOS transistor.

[0188] Photodiode PD has an anode supplied with power supply voltage VSS and a cathode coupled to node N1. Transistor MP1 has a gate coupled to the output terminal of inverter IV4, a source supplied with power supply voltage VDD, and a drain coupled to node N1. Transistor MP2 has a gate coupled to the output terminal of NAND circuit ND2, a source supplied with power supply voltage VDD2, and a drain coupled to the source of transistor MP3. Transistor MP3 has a gate coupled to node N1, a source coupled to the drain of transistor MP2, and a drain coupled to node N2. Transistor MN4 has a gate coupled to the output terminal of NAND circuit ND2, a drain coupled to node N2, and a grounded source.

[0189] The input terminal of inverter IV2 is coupled to node N2, and its output terminal is coupled to the input terminal of inverter IV3 and the input terminal of delay circuit DEL. Inverter IV3 has an input terminal coupled to the output terminal of inverter IV2, and a selector 33A and an adder 32 coupled to the stage following the optical receiver 31A. Figure 32 ) output terminals.

[0190] The delay circuit DEL is configured to delay an input signal by a predetermined time and output a delayed signal. The delay circuit DEL has an input terminal coupled to the output terminal of inverter IV2 and an output terminal coupled to NAND circuit ND2. NAND circuit ND2 is configured to receive the output signal of delay circuit DEL and the NAND signal XRST. NAND circuit ND2 has a first input terminal coupled to the output terminal of delay circuit DEL, a second input terminal provided with the control signal XRST, and an output terminal coupled to the gates of transistors MP2 and MN4 and the input terminal of inverter IV4. Inverter IV4 has an input terminal to the output terminal of NAND circuit ND2 and an output terminal coupled to the gate of transistor MP1.

[0191] Here, transistor MP3 corresponds to a specific instance of "transistor" in this disclosure. Transistor MP2 corresponds to a specific instance of "first switch" in this disclosure. Transistor MN4 corresponds to a specific instance of "second switch" in this disclosure. Inverter IV2, delay circuit DEL, and NAND circuit ND2 correspond to specific instances of "control circuit" in this disclosure.

[0192] Figure 28 An operational example of the light receiving unit 31A is shown. (A) Waveform of incident light on photodiode PD. (B) Waveform of control signal XRST. (C) Waveform of voltage V1 at node N1. (D) Waveform of voltage V2 at node N2. (E) Waveform of voltage V3 at the output of inverter IV2. (F) Voltage V4 at the output of NAND circuit ND2. (G) Waveform of pulse signal PLSA.

[0193] At time t61, the control signal XRST is changed from high level to low level by the signal generation unit 22E of this modified example. Figure 28 (B)). Based on this change in the control signal XRST, the voltage V4 at the output terminal of the NAND circuit ND2 changes from low level to high level. Figure 28 Based on this change in voltage V4, the voltage at the gate of transistor MP1 changes from a high level to a low level, which will turn on transistor MP1 to set the voltage at node N1 to the supply voltage VDD. Figure 28 (C)). Furthermore, based on this change in voltage V4, transistor MP2 is turned off and transistor MN4 is turned on, which sets the voltage V2 at node N2 to a low level (C). Figure 28 (D)), and set the voltage V3 at the output terminal of inverter IV2 to a high level ( Figure 28 (E)).

[0194] Subsequently, the signal generation unit 22E changes the control signal XRST from low level to high level. Figure 28 (B)). Based on this change in the control signal XRST, the voltage V4 at the output terminal of the NAND circuit ND2 changes from a high level to a low level. Figure 28 (F)). Based on this change in voltage V4, the voltage at the gate of transistor MP1 changes from a low level to a high level, which turns off transistor MP1 and keeps the voltage at node N1 at the supply voltage VDD. Figure 28 (C)). Furthermore, based on this change in voltage V4, transistor MP2 turns on and transistor MN4 turns off, which maintains the voltage V2 at node N2 at a low level. Figure 28 (D)) and maintain the voltage V3 at the output terminal of inverter IV2 at a high level ( Figure 28 (E)).

[0195] At time t62, when photons enter the photodiode PD ( Figure 28(A)), avalanche amplification occurs, and the voltage V1 at node N1 begins to decrease from the supply voltage VDD. Figure 28 (C)). Then, based on this change in voltage V1, transistor MP3 changes from off to on, and the voltage V2 at node N2 changes from low to high. Figure 28 (D)). Based on this change in voltage V2, the voltage V3 at the output of inverter IV2 changes from high to low at timing t63. Figure 28 (E)). Based on this change in voltage V3, the voltage of the pulse signal PLSA changes from low level to high level. Figure 28 (G)).

[0196] The delay circuit DEL delays the signal indicated by voltage V3. Therefore, the voltage V4 at the output terminal of NAND circuit ND2 changes from low to high at timing t64. Figure 28 (F)). Based on this change in voltage V4, the voltage at the gate of transistor MP1 changes from a high level to a low level, which turns transistor MP1 from off to on, and the cathode voltage V1 of photodiode PD changes towards the power supply voltage VDD. Figure 28 (C)). Furthermore, based on this change in voltage V4, transistor MP2 changes from on to off, transistor MN4 changes from off to on, and the voltage V2 at node N2 changes from high to low. Figure 28 (D)). Based on this change in voltage V2, the voltage V3 at the output of inverter IV2 changes from low to high at timing t65. Figure 28 (E)). Based on this change in voltage V3, the voltage of the pulse signal PLSA changes from high level to low level. Figure 28 (G)). The delay circuit DEL delays the signal represented by voltage V3. Therefore, the voltage V4 at the output terminal of NAND circuit ND2 changes from high to low at timing t66. Figure 28 (F)).

[0197] Therefore, the light receiving unit 31A generates a pulse signal PLSA by detecting light. The pulse width Tpw of the pulse signal PLSA has a time width corresponding to the delay amount of the delay circuit DEL. Therefore, by adjusting the delay amount of the delay circuit DEL, the pulse width Tpw of the pulse signal PLSA can be set to an appropriate time width.

[0198] [Variation Example 7]

[0199] In the above embodiments, such as Figure 4A and Figure 4BAs shown, the cathode of the photodiode PD is directly coupled to the drain of the transistor MP1 and the input terminal of the inverter IV1, but this is not limiting. The following describes this variation in detail with reference to some examples.

[0200] Figure 29 An example configuration of the light receiving unit 31A according to this modification is shown. Figure 29 This illustrates the application of this variation to... Figure 4B The light receiver 31A shown is a photodiode PD, a transistor MP1, an inverter IV11, transistors MP11 and MP12, a resistor R11, an inverter IV1, and a control circuit CKT1. Transistors MP1, MP11, and MP12 are P-type MOS transistors.

[0201] The anode of the photodiode PD is supplied with a power supply voltage VSS, and its cathode is coupled to node N11. Inverter IV11 has an input terminal supplied with a mode control signal SMODE and an output terminal coupled to the gate of transistor MP12. Transistor MP11 has a gate supplied with the mode control signal SMODE, a source coupled to node N1, and a drain coupled to one end of resistor R11. Resistor R11 has one end coupled to the drain of transistor MP11 and the other end coupled to node N11. Transistor MP12 has a gate coupled to the output terminal of inverter IV11, a source coupled to node N1, and a drain coupled to node N11. It is desirable that the sum of the on-resistance of transistor MP12 and the resistance of resistor R11 is greater than the resistance between the anode and cathode of the photodiode PD.

[0202] With this configuration, when the operating mode M is imaging mode MA, transistor MP11 is turned on and transistor MP12 is turned off in the light receiving unit 31A. Therefore, the cathode of the photodiode PD is coupled to the drain of transistor MP1 and the input terminal of inverter IV1 via transistor MP11 and resistor R11. Furthermore, when the operating mode M is ranging mode MB, transistor MP12 is turned on and transistor MP11 is turned off. Therefore, the cathode of the photodiode PD is coupled to the drain of transistor MP1 and the input terminal of inverter IV1 via transistor MP12.

[0203] Here, transistor MP1 corresponds to a specific example of the "load element" in this disclosure. Transistors MP11 and MP12, and resistor R11, correspond to specific examples of the "variable resistance section" in this disclosure. Inverter IV1 corresponds to a specific example of the "generating section" in this disclosure.

[0204] Figure 30An operational example of the light receiver 31A in imaging mode MA is shown. (A) shows the waveform of the incident light on the photodiode PD. (B) shows the waveform of the voltage V1 at node N1. (C) shows the waveform of the voltage V11 at node N11. (D) shows the waveform of the pulse signal PLSA.

[0205] Figure 31 An example configuration of the light receiver 31A in imaging mode MA is shown. Figure 31 In the diagram, transistors MP11 and MP12 are both illustrated using switches to indicate their states. Furthermore, Figure 31 The capacitor CAP1, representing the parasitic capacitance value at node N1, and the capacitor CAP11, corresponding to the parasitic capacitance value at node N2, are shown. In imaging mode MA, as... Figure 31 As shown, transistor MP11 is turned on, and transistor MP12 is turned off.

[0206] At time t71, when photons enter the photodiode PD ( Figure 30 (A) Avalanche amplification occurs, and current flows from the cathode to the anode of the photodiode PD. In this case, current flows from capacitor CAP11 to photodiode PD, and current flows from capacitor CAP1 to photodiode PD through resistor R11, and the voltage V11 at node N1 and the voltage V1 at node N1 begin to decrease from the supply voltage VDD. Figure 30 (B) and (C)). Capacitor CAP11 is directly coupled to photodiode PD, and resistor R11 is coupled between capacitor CAP1 and photodiode PD; therefore, the voltage drop at node N1 is less than the voltage drop at node N11.

[0207] Then, at time t72, after the avalanche amplification ends, current flows from capacitor CAP1 to capacitor CAP11, and a redistribution of charge occurs on capacitors CAP1 and CAP11. Therefore, voltage V11 begins to increase, while voltage V1 continues to decrease. Figure 30 (B) and (C)).

[0208] At time t73, when voltage V1 falls below the logic threshold of inverter IV1, the pulse signal PLSA changes from low to high. Figure 30 (D)).

[0209] Then, at time t74, when the redistribution of charge on capacitors CAP1 and CAP11 ends, voltages V1 and V11 become the same as each other and remain at these voltages.

[0210] Subsequently, at time t75, the control circuit CKT1 changes the voltage at the gate of transistor MP1 from high to low. Therefore, transistor MP1 turns on, and voltages V1 and V11 change towards the power supply voltage VDD. Figure 30 (B) and (C)). The pulse signal PLSA changes from high level to low level according to this change in voltage V1. Figure 30 (D)).

[0211] Therefore, in imaging mode MA, the voltage V1 does not change significantly, which suppresses the charging and discharging of capacitor CAP1. As a result, power consumption in imaging mode MA can be reduced in the photodetector system.

[0212] Figure 32 An operational example of the light receiver 31A in the ranging mode MB is shown. (A) shows the waveform of the incident light on the photodiode PD. (B) shows the waveform of the voltage V1 at node N1. (C) shows the waveform of the voltage V11 at node N11. (D) shows the waveform of the pulse signal PLSA.

[0213] Figure 33 An example configuration of the optical receiver 31A in a ranging mode MB is shown. In a ranging mode MB, as... Figure 33 As shown, transistor MP12 is turned on, and transistor MP11 is turned off.

[0214] At time t81, when photons enter the photodiode PD ( Figure 32 (A) Avalanche amplification occurs, and current flows from the cathode to the anode of the photodiode PD. In this case, current flows from capacitor CAP11 to photodiode PD, and current flows from capacitor CAP1 to photodiode PD through resistor R11, and the voltage V11 at node N1 and the voltage V1 at node N1 begin to decrease from the supply voltage VDD. Figure 32 (B) and (C)). In ranging mode MB, capacitor CAP1 is coupled to photodiode PD via transistor MP12; therefore, the voltage drop at node N1 is approximately the same as the voltage drop at node N11.

[0215] At time t82, when the voltage V1 falls below the logic threshold of inverter IV1, the pulse signal PLSA changes from low to high. Figure 32 (D)).

[0216] Then, at time t82, when the avalanche amplification ends, voltages V1 and V11 are mostly maintained ( Figure 32 (B) and (C)).

[0217] Subsequently, at timer t84, control circuit CKT1 changes the voltage at the gate of transistor MP1 from high to low. Therefore, transistor MP1 turns on, and voltages V1 and V11 change towards the power supply voltage VDD. Figure 32 (C)(B)). The pulse signal PLSA changes from high level to low level according to this change in voltage V1. Figure 32 (D)).

[0218] Therefore, in the ranging mode (MB), the pulse signal PLSA can be increased after a short response time following the photon's arrival timing. As a result, the detection accuracy during ranging operations can be improved in this optical detection system.

[0219] Figure 34 Another configuration example of an optical receiver 31A according to this modification is shown. The optical receiver 31A includes transistors MP21 and MP22. Transistors MP21 and MP22 are P-type MOS transistors. Transistor MP21 has a gate supplied with a mode control signal SMODE, a source coupled to node N1, and a drain coupled to node N11. Transistor MP22 has a gate coupled to the output terminal of inverter IV11, a source coupled to node N1, and a drain coupled to node N11. The gate width W of transistor MP21 is... P21 and gate length L P21 and the gate width W of transistor MP22 P22 and gate length L P22 It satisfies the following expression.

[0220] W P21 / L P21 <W P22 / L P22

[0221] Therefore, the drain-source resistance of transistor MP21 when it is turned on can be greater than the drain-source resistance of transistor MP22 when it is turned on.

[0222] Figure 35Another configuration example of an optical receiver 31A according to this modification is shown. The optical receiver 31A includes transistors MN11 and MN12, resistor R11, and inverter IV12. Transistors MN11 and MN12 are N-type MOS transistors. Transistor MN11 has a gate coupled to the output terminal of inverter IV12, a drain coupled to node N1, and a source coupled to one end of resistor R11. Transistor MN12 has a gate supplied with a mode control signal SMODE, a drain coupled to node N1, and a source coupled to node N11. Inverter IV12 has an input terminal supplied with the mode control signal SMODE and an output terminal coupled to the gate of transistor MN11.

[0223] With this configuration, when the operating mode M is imaging mode MA, transistor MN11 is turned on and transistor MN12 is turned off in the light receiving unit 31A. Therefore, the cathode of the photodiode PD is coupled to the drain of transistor MP1 and the input terminal of inverter IV1 via transistor MN11 and resistor R11. Furthermore, when the operating mode M is ranging mode MB, transistor MN12 is turned on and transistor MN11 is turned off. Therefore, the cathode of the photodiode PD is coupled to the drain of transistor MP1 and the input terminal of inverter IV1 via transistor MN12.

[0224] Figure 36 Another configuration example of an optical receiver 31A according to this modification is shown. The optical receiver 31A includes transistors MN21 and MN22. Transistors MN21 and MN22 are N-type MOS transistors. Transistor MN21 has a gate coupled to the output terminal of inverter IV12, a drain coupled to node N1, and a source coupled to node N11. Transistor MN22 has a gate supplied with a mode control signal SMODE, a drain coupled to node N1, and a source coupled to node N11. The gate width W of transistor MN21 is... N21 and gate length L N21 and the gate width W of transistor MN22 N22 and gate length L N22 It satisfies the following expression.

[0225] W N21 / L N21 <W N22 / L N22

[0226] Therefore, the drain-source resistance of transistor MN21 when it is turned on can be made greater than the drain-source resistance of transistor MN22 when it is turned on.

[0227] [Other variations]

[0228] Two or more of these variations can be combined.

[0229] <2. Examples of applications of moving objects>

[0230] The technology disclosed herein (the Technology) is applicable to a variety of products. For example, the Technology disclosed herein can be implemented as a device mounted on any type of mobile body, such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, aircraft, drone, ship, or robot.

[0231] Figure 37 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system, which serves as an example of a mobile body control system to which the technology according to embodiments of this disclosure can be applied.

[0232] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 37 In the example depicted, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 1205. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0233] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: drive force generating devices for generating drive force for the vehicle, such as internal combustion engines, drive motors, etc.; drive force transmission mechanisms for transmitting drive force to the wheels; steering mechanisms for adjusting the vehicle's steering angle; braking devices for generating braking force for the vehicle, etc.

[0234] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are alternatives to buttons, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0235] The external information detection unit 12030 detects external information, including information from outside the vehicle, which is part of the vehicle control system 12000. For example, the external information detection unit 12030 is connected to an imaging unit 12031. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the external environment and receives these images. Based on the received images, the external information detection unit 12030 can perform processing such as detecting people, vehicles, obstacles, signs, text on the road surface, etc., or detecting their distances.

[0236] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0237] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is drowsy.

[0238] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained from the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, following driving based on following distance, maintaining vehicle speed, collision warning, lane departure warning, etc.

[0239] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc., based on information about the outside or inside of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can perform cooperative control for autonomous driving, which enables the vehicle to drive automatically without relying on the driver's operation.

[0240] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the outside of the vehicle obtained by the external information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam based on the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030.

[0241] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. Figure 37 In this example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0242] Figure 38 This is a diagram illustrating an example of the mounting position of the imaging unit 12031.

[0243] exist Figure 38 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0244] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, located on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, and on the upper part of the windshield inside the vehicle. Imaging unit 12101 on the front nose inside the vehicle and imaging unit 12105 on the upper part of the windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0245] Incidentally, Figure 38An example of the imaging range of imaging units 12101 to 12104 is described. Imaging range 12111 represents the imaging range of imaging unit 12101 installed at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by imaging units 12101 to 12104.

[0246] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0247] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle ahead. This nearest three-dimensional object specifically exists on the travel path of the vehicle 12100 and travels in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can preset the following distance to be maintained in front of the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Thus, coordinated control for automated driving can be performed without relying on driver operation.

[0248] For example, the microcomputer 12051 can classify the three-dimensional object data of three-dimensional objects into categories such as two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, and utility poles based on distance information obtained from imaging units 12101 to 12104. It then extracts the classified three-dimensional object data and uses this data to automatically avoid obstacles. For instance, the microcomputer 12051 identifies obstacles around vehicle 12100 as those that the driver of vehicle 12100 can visually recognize and those that are difficult for the driver to visually recognize. Then, the microcomputer 12051 determines the collision risk, representing the risk of colliding with each obstacle. If the collision risk exceeds a set value and a collision is possible, the microcomputer 12051 outputs a warning to the driver via an audio speaker 12061 or a display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0249] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the imaging images of the imaging units 12101 to 12104. For example, pedestrian identification is performed by extracting feature points from the imaging images of the imaging units 12101 to 12104 as a process of an infrared camera and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the imaging images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon or the like representing a pedestrian is displayed at a desired location.

[0250] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied to the imaging unit 12031 in the aforementioned components. This allows for improved detection accuracy in distance measurement operations within the vehicle control system 12000. This enables the vehicle control system 12000 to perform high-precision following functions based on inter-vehicle distance, speed-maintaining functions, vehicle collision warning functions, lane departure warning functions, etc.

[0251] Although the present technology has been described above with reference to some embodiments, variations and specific application examples, the present technology is not limited to these embodiments and can be modified in various ways.

[0252] For example, in the above embodiments, four light receivers 31 and four selectors 33 are provided, but this is not limiting. Instead, for example, N1 light receivers 31 and N1 selectors 33 can be provided. N1 is 3 or less or 5 or more. Furthermore, in each of the above embodiments, four switches 34 and four counters 35 are provided, but this is not limiting. Instead, for example, N2 switches 34 and N2 counters 35 can be provided. N2 is 3 or less or 5 or more. N1 and N2 can be equal to each other, such as... Figure 24 As shown, they may not be equal, such as Figure 25 and Figure 26 As shown.

[0253] It should be noted that the effects described herein are merely illustrative and non-limiting, and may include other effects.

[0254] It should be noted that this technology can have the following configurations. The detection accuracy can be improved by using this technology with the following configurations. (1)

[0256] A light detection device, comprising:

[0257] Multiple optical receivers, each including an optical receiving element, generate a first pulse signal, the first pulse signal including a pulse corresponding to the result of optical reception by the optical receiving element;

[0258] The addition unit generates a second pulse signal by selecting one or more first pulse signals from a plurality of first pulse signals generated by the plurality of optical receiving units and performing addition processing based on the selected one or more first pulse signals;

[0259] The distribution unit performs distribution processing based on the clock signal to divide the second pulse signal into multiple third pulse signals in a time-division manner;

[0260] Multiple counters are configured corresponding to the multiple third pulse signals, and each counter performs counting processing based on a corresponding one of the third pulse signals; and

[0261] The control unit sets the number of signals of the one or more pulse signals to undergo the addition process based on the corresponding count values ​​of the plurality of counters. (2)

[0263] According to the photoelectric detection device described in (1), wherein,

[0264] The control unit determines the light intensity based on the corresponding count values ​​of the plurality of counters.

[0265] When the light intensity is a first light intensity, the control unit sets the number of signals to a first number, and

[0266] When the light intensity is a second light intensity that is lower than the first light intensity, the control unit sets the number of signals to a second number that is greater than the first number. (3)

[0268] According to the photoelectric detection device described in (2), the control unit determines the light intensity based on whether the total value of the multiple count values ​​of the multiple counters reaches a predetermined count value. (4)

[0270] According to the photoelectric detection device described in (2), the control unit determines the light intensity based on whether one or more of the multiple count values ​​of the plurality of counters reach a predetermined count value. (5)

[0272] According to any one of (1) to (3) the photoelectric detection device, wherein,

[0273] The optical detection device has a first operating mode and a second operating mode, and

[0274] In the first operating mode, the addition unit generates a second pulse signal by performing addition processing, and each of the plurality of counters performs counting processing based on a corresponding one of the third pulse signals. (6)

[0276] According to the photoelectric detection device described in (5), wherein,

[0277] The number of the plurality of counters is the same as the number of the plurality of optical receivers.

[0278] The plurality of counters correspond one-to-one with the plurality of first pulse signals, and

[0279] In the second operating mode, each of the plurality of counters performs the counting process based on a corresponding one of the first pulse signals. (7)

[0281] According to the photoelectric detection device described in (6), the control unit sets the signal number based on the respective count values ​​of the plurality of counters in the second operation mode. (8)

[0283] According to the photoelectric detection device described in (5), wherein,

[0284] The number of the plurality of counters is different from the number of the plurality of optical receivers.

[0285] The plurality of counters are reconfigured to be two or more counters, the same number as the plurality of optical receivers.

[0286] The two or more counters correspond one-to-one with the plurality of first pulse signals, and

[0287] In the second operating mode, each of the two or more counters performs the counting process based on a corresponding one of the first pulse signals. (9)

[0289] According to the photoelectric detection device described in (8), the control unit sets the signal number based on the respective count values ​​of the two or more counters in the second operation mode. (10)

[0291] According to any one of (5) to (9) the photoelectric detection device, wherein,

[0292] The optical receiving element is disposed in the first path between the first node and the first power node, and

[0293] Each of the plurality of optical receivers includes:

[0294] The load element is disposed in the second path between the first node and the second power node.

[0295] A variable resistor section is disposed between the first node in the first path and the light receiving element, and

[0296] The generation unit generates the first pulse signal based on the voltage at the first node. (11)

[0298] According to the photoelectric detection device described in (10), wherein,

[0299] The variable resistor is configured to set a resistance value to a first resistance value or a second resistance value greater than the first resistance value.

[0300] In the first operating mode, the variable resistor unit sets the resistance value to the first resistance value, and

[0301] In the second operating mode, the variable resistor unit sets the resistance value to the second resistance value. (12)

[0303] According to any one of (1) to (11), the photoelectric detection device, wherein,

[0304] Each of the plurality of optical receivers includes:

[0305] A transistor having a gate, a source, and a drain coupled to the light-receiving element.

[0306] The first switch, by being turned on, supplies a first power supply voltage to the source of the transistor.

[0307] The second switch, by being turned on, supplies the second power supply voltage to the drain of the transistor, and

[0308] A control circuit that, based on the voltage at the drain of the transistor, turns on one of the first and second switches, and turns off the other of the first and second switches after a predetermined time has elapsed since the voltage at the drain changed. (13)

[0310] The photoelectric detection device according to any one of (1) to (12), wherein the light receiving element comprises an avalanche photodiode. (14)

[0312] The photoelectric detection device according to any one of (1) to (13), wherein the light receiving element comprises a single-photon avalanche diode. (15)

[0314] According to any one of (1) to (14) the photoelectric detection device, wherein,

[0315] Multiple optical detection units are set up, and

[0316] Each of the multiple optical detection units has multiple optical receivers, adders, distributors, counters, and control units. (16)

[0318] According to any one of (1) to (15) the photoelectric detection device, wherein,

[0319] Multiple light-receiving elements are disposed on the first semiconductor substrate, and

[0320] The addition unit, the distribution unit, and the plurality of counters are disposed on a second semiconductor substrate bonded to the first semiconductor substrate. (17)

[0322] A light detection system, comprising:

[0323] Light emitting part, emitting light; and

[0324] The light detection unit detects the light reflected from the object being detected by the light emitted from the light emitting unit, wherein...

[0325] The optical detection unit includes:

[0326] Multiple optical receivers, each including an optical receiving element, generate a first pulse signal, the first pulse signal including pulses corresponding to the result of optical reception by the optical receiving element.

[0327] The addition unit generates a second pulse signal by selecting one or more first pulse signals from a plurality of first pulse signals generated by the plurality of optical receiving units and performing addition processing based on the selected one or more first pulse signals.

[0328] The distribution unit performs distribution processing based on a clock signal to distribute the second pulse signal into multiple third pulse signals in a time-distribution manner.

[0329] Multiple counters are configured corresponding to the multiple third pulse signals, and each counter performs counting processing based on a corresponding one of the third pulse signals.

[0330] The control unit sets the number of signals of the one or more pulse signals to undergo the addition process based on the corresponding count values ​​of the plurality of counters.

[0331] This application claims priority to Japanese Patent Application No. 2020-183865, filed with the Japan Patent Office on November 2, 2020, the entire contents of which are incorporated herein by reference.

[0332] Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations can be made depending on design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A light detection device, comprising: A plurality of optical receivers, each of the optical receivers including an optical receiving element, and each of the optical receivers generating a first pulse signal, the first pulse signal including a pulse corresponding to the result of optical reception by the optical receiving element; The addition unit generates a second pulse signal by selecting one or more first pulse signals from a plurality of first pulse signals generated by a plurality of optical receiving units, and performing addition processing based on the selected one or more first pulse signals; The distribution unit performs the distribution process of dividing the second pulse signal into multiple third pulse signals in a time-division manner based on the clock signal; Multiple counters, each counter corresponding to a plurality of third pulse signals, and each counter performing counting processing based on the corresponding third pulse signal; as well as The control unit sets the number of one or more pulse signals that are the object of the addition process based on the respective count values ​​of the plurality of counters. The control unit determines the light intensity based on the respective count values ​​of the multiple counters. When the light intensity is a first light intensity, the control unit sets the number of signals to a first number, and When the light intensity is a second light intensity that is lower than the first light intensity, the control unit sets the number of signals to a second number that is greater than the first number.

2. The optical detection device according to claim 1, wherein, The control unit determines the light intensity based on whether the total value of multiple counts from the multiple counters reaches a predetermined count value.

3. The optical detection device according to claim 1, wherein, The control unit determines the light intensity based on whether one or more of the count values ​​of the plurality of counters have reached a predetermined count value.

4. The optical detection device according to claim 1, wherein, The optical detection device has a first operating mode and a second operating mode, and In the first operating mode, the addition unit generates the second pulse signal by performing the addition process, the allocation unit performs the allocation process, and each of the plurality of counters performs a counting process based on the corresponding third pulse signal.

5. The optical detection device according to claim 4, wherein, The number of the plurality of counters is the same as the number of the plurality of optical receivers. Each of the multiple counters corresponds one-to-one with a multiple of the first pulse signals, and In the second operating mode, each of the plurality of counters performs the counting process based on the corresponding first pulse signal.

6. The optical detection device according to claim 5, wherein, The control unit sets the number of signals based on the respective count values ​​of the plurality of counters in the second operating mode.

7. The optical detection device according to claim 4, wherein, The number of the plurality of counters differs from the number of the plurality of optical receivers. In the second operating mode, the plurality of counters are reconfigured to two or more counters, the same number as the plurality of optical receivers. The two or more counters correspond one-to-one with the plurality of the first pulse signals, and In the second operating mode, each of the two or more counters performs the counting process based on a corresponding first pulse signal in the first pulse signal.

8. The optical detection device according to claim 7, wherein, The control unit sets the number of signals based on the respective count values ​​of the two or more counters in the second operating mode.

9. The optical detection device according to claim 4, wherein, The optical receiving element is positioned on the first path connecting the first node and the first power node, and Each of the plurality of said optical receivers includes: The load element is positioned in the second path connecting the first node and the second power node. A variable resistor section is disposed in the first path between the first node and the light receiving element, and The generation unit generates the first pulse signal based on the voltage at the first node.

10. The optical detection device according to claim 9, wherein, The variable resistor section can set the resistance value to a first resistance value or a second resistance value greater than the first resistance value. In the first operating mode, the variable resistor unit sets the resistance value to the first resistance value, and In the second operating mode, the variable resistor unit sets the resistance value to the second resistance value.

11. The optical detection device according to claim 1, wherein, Each of the plurality of said optical receivers includes: A transistor having a source, a drain, and a gate coupled to the light-receiving element. A first switch, when turned on, supplies a first power supply voltage to the source of the transistor. A second switch, which, when turned on, supplies a second power supply voltage to the drain of the transistor, and The control circuit, based on the voltage at the drain of the transistor, turns on one of the first switch and the second switch and turns off the other of the first switch and the second switch after a predetermined time has elapsed since the voltage change at the drain.

12. The optical detection device according to claim 1, wherein, The light receiving element includes an avalanche photodiode.

13. The optical detection device according to claim 1, wherein, The optical receiving element includes a single-photon avalanche diode.

14. The optical detection device according to claim 1, wherein, Equipped with multiple optical detection units, and Each of the plurality of optical detection units has the plurality of optical receiving units, the addition unit, the distribution unit, the plurality of counters, and the control unit.

15. The optical detection device according to claim 1, wherein, Multiple light-receiving elements are disposed on a first semiconductor substrate, and The addition unit, the distribution unit, and the plurality of counters are disposed on a second semiconductor substrate bonded to the first semiconductor substrate.

16. A light detection system, comprising: Light emitting part, emits light; as well as The light detection unit detects the light reflected by the object being detected from the light emitted by the light emitting unit, wherein... The optical detection unit includes: A plurality of optical receivers, each of the optical receivers including an optical receiving element, and each of the optical receivers generating a first pulse signal, the first pulse signal including a pulse corresponding to the result of optical reception by the optical receiving element; The addition unit generates a second pulse signal by selecting one or more first pulse signals from a plurality of first pulse signals generated by a plurality of optical receiving units, and performing addition processing based on the selected one or more first pulse signals; The distribution unit performs the distribution process of dividing the second pulse signal into multiple third pulse signals in a time-division manner based on the clock signal; A plurality of counters, each counter corresponding to a plurality of third pulse signals, and each counter performing counting processing based on its corresponding third pulse signal; and The control unit sets the number of one or more pulse signals that are the object of the addition process based on the respective count values ​​of the plurality of counters. The control unit determines the light intensity based on the respective count values ​​of the multiple counters. When the light intensity is a first light intensity, the control unit sets the number of signals to a first number, and When the light intensity is a second light intensity that is lower than the first light intensity, the control unit sets the number of signals to a second number that is greater than the first number.

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