Pseudo-resistive circuit

Abstract

The embodiment of the present disclosure provides a pseudo-resistance circuit, which belongs to the field of analog integrated circuit design. The pseudo-resistance circuit comprises: a transistor M1 and a transistor M2 connected in series, the transistor M1 and the transistor M2 are both PMOS tubes, the gate of the transistor M1 and the gate of the transistor M2 are connected and connected to the series connection point of the transistor M1 and the transistor M2; and a bias voltage V B that can be self-adjusted with temperature acting on the substrate end of the transistor M1 and the transistor M2. The embodiment of the present disclosure improves the temperature stability of the pseudo-resistance circuit based on the substrate bias effect of the transistor, so that the pseudo-resistance circuit has a wider application scenario.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of analog integrated circuit design, and relates to a pseudo-resistor circuit. BACKGROUND

[0002] In recent years, with the emphasis on the field of biological medicine, more and more sensing circuit designs begin to face the direction of human vital sign detection and disease diagnosis. Due to the chemical action between the sensor metal probe and the gel, the alternating charge accumulates, which usually generates an electrode offset voltage (EOV) of 10 mV-100 mV. The direct current offset cancellation loop (DCOC) for electrode offset suppression generally feeds back and suppresses the offset amount at the output end through a low-pass filter. Similarly, in the chopper circuit, in order to avoid the influence of the offset amount modulated to high frequency by the chopper switch on the circuit function, a ripple suppression loop with a low-pass filter is added to the front-end circuit to suppress the offset amount.

[0003] Generally, an ideal low-pass filter will be accompanied by a large power consumption and area cost. Considering these two factors, most works choose to combine pF-level on-chip capacitors and GΩ-level equivalent resistors to achieve an extremely low cutoff frequency. The commonly used equivalent resistance structures include duty cycle resistance circuits, switched capacitor resistance circuits and PMOS pseudo resistance circuits. Among them, the first two are controlled by an external clock and are affected by the limited switching parasitic capacitance and the actual working frequency of the circuit, so their use scenarios are limited. The PMOS pseudo resistance circuit is mainly composed of a single or multiple PMOS tubes working in the sub-threshold region, and the structure is relatively simple. The double-tube PMOS pseudo resistance circuit can also get better frequency characteristics by adjusting the gate voltage bias.

[0004] Due to the advantages of good matching performance, no static power consumption and low noise, people often use a capacitively-coupled chopper instrumentation amplifier (CCIA) as the front end of a high-performance analog data acquisition unit. The disadvantage of the capacitance feedback network is that the direct current voltage cannot be input through the capacitor, while the traditional passive resistance structure is limited by the voltage margin and will introduce additional noise, so the pseudo resistance structure is also often used to provide a direct current bias point for such circuits.

[0005] Industrial-grade sensing circuits are more demanding in application environment than biological sensing circuits, and certain requirements are put forward for the normal working temperature range of the amplifier. Figure 1The existing pseudo-resistor circuit structure diagram includes a substrate and two transistors M1' and M2' (both are PMOS transistors) connected in series, and X and Y points are two output ports of the pseudo-resistor circuit. The gate of the transistor M1' and the gate of the transistor M2' are connected at the connection point of the two transistors M1' and M2', and the substrate is directly connected with the source of the transistor M1' and the source of the transistor M2'. Since the threshold voltage and other parameters of the transistor are greatly affected by temperature, under high temperature condition, the equivalent resistance of the transistor will be reduced from hundreds of GΩ to several GΩ or even lower, which damages the stability of the input node RC cutoff frequency in the active filter and the capacitance coupling instrument amplifier, and greatly limits the application of this structure. SUMMARY

[0006] The present disclosure aims to at least solve one of the technical problems existing in the prior art.

[0007] To this end, the present disclosure proposes a pseudo-resistor circuit based on the substrate bias effect of the transistor, which has high temperature stability, comprising:

[0008] The transistor M1 and the transistor M2 connected in series, the transistor M1 and the transistor M2 are PMOS transistors, and the gates of the transistor M1 and the transistor M2 are connected and connected to the series connection point of the transistor M1 and the transistor M2; and

[0009] The temperature self-adjusting bias voltage V B acting on the substrate end of the transistor M1 and the transistor M2.

[0010] In some embodiments, the temperature self-adjusting bias voltage V B is generated by a temperature control voltage generation circuit, and the temperature control voltage generation circuit comprises:

[0011] The transistor M9 connected in diode mode, the transistor M9 is a PMOS transistor, and the gate voltage of the transistor M9 is the temperature self-adjusting bias voltage V B .

[0012] The common-source common-gate current source is used to provide a bias current that does not change with temperature for the transistor M9, and make the transistor M9 work in the sub-threshold region;

[0013] The common-source common-gate current mirror is used to provide a bias voltage for the common-source common-gate current source.

[0014] In some embodiments, the source and substrate end of the transistor M9 are connected to the power supply voltage V DD .

[0015] In some embodiments, the common-source common-gate current mirror comprises transistors M3, M4, M5 and M6 which are all NMOS tubes, the substrate end of each of the transistors M3, M4, M5 and M6 is grounded; the gate of the transistor M3 is connected to the gate of the transistor M4, the source of the transistor M3 is grounded, and the drain of the transistor M3 is connected to the source of the transistor M4; the gate of the transistor M4 is connected to the drain of the transistor M4, and a reference current I ref is input to the drain of the transistor M4 to generate a voltage V b1 at the drain of the transistor M4; the gate of the transistor M5 is connected to the drain of the transistor M6, the source of the transistor M5 is grounded, and the drain of the transistor M5 is connected to the source of the transistor M6; the gate of the transistor M6 is connected to a voltage V b1 , and a mirror current I1 identical to the reference current I ref is input to the drain of the transistor M6 to generate a voltage V b2 at the drain of the transistor M6.

[0016] In some embodiments, the common-source common-gate current source comprises transistors M7 and M8 which are both NMOS tubes, the substrate end of each of the transistors M7 and M8 is grounded; the gate of the transistor M7 is connected to a voltage V b2 , the source of the transistor M7 is grounded, and the drain of the transistor M7 is connected to the source of the transistor M8; the gate of the transistor M8 is connected to a voltage V b1 , and the drain of the transistor M8 is connected to the drain of the transistor M9.

[0017] In some embodiments, the sizes of the NMOS tubes M7 and M8 are proportionally reduced to sizes that can ensure that the PMOS tube M9 operates in the sub-threshold region.

[0018] Technical features and advantages of the present disclosure:

[0019] 1. In the case of trying not to increase the complexity of the circuit, the problem of the resistance value of the pseudo-resistor structure being limited at high temperature is alleviated, and the application range of the pseudo-resistor is expanded. The equivalent resistance value of the structure can be maintained at several hundred GΩ in the temperature range of -40 to 125°C, and the temperature stability is improved by two to three orders of magnitude compared with the traditional structure. The current source added in the circuit can be proportionally reduced by the original reference source in the actual circuit, and a temperature control voltage can be generated with a single transistor, and the additional power consumption and area are very small.

[0020] 2、Compared with other improved structures of pseudo-resistor, the temperature control bias voltage is not added to the gate end of the pseudo-resistor. Since the gate of the symmetric PMOS pseudo-resistor tube is generally connected with the source (or drain), which ensures that the pseudo-resistor tube works in the sub-threshold region, the bias voltage added to the gate end will affect the two ports of the pseudo-resistor, and interfere with the transmission of the signal or direct current bias voltage. Modulating the substrate can ensure the symmetry of the transmission of the two PMOS tubes on the basis of improving the temperature stability. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of a traditional PMOS pseudo-resistor circuit.

[0022] Figure 2 It is a structural schematic diagram of a pseudo-resistor circuit structure provided by the embodiment of the present disclosure.

[0023] Figure 3 It is a structural schematic diagram of a temperature-voltage generating circuit for substrate bias of a PMOS pseudo-resistor tube provided by the embodiment of the present disclosure.

[0024] Figure 4 It is a comparison of equivalent resistance values of two kinds of pseudo-resistors under a 0.9V common-mode voltage bias, TT process angle, and-40℃-125℃ environment.

[0025] Figure 5 It is a comparison of input node RC cutoff frequencies of two kinds of pseudo-resistors under-40℃-125℃ environment when providing direct current bias for a capacitor feedback network in an actual circuit. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present application clearer and more apparent, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0027] On the contrary, the present application covers any substitution, modification, equivalent method and solution made on the essence and scope of the present application as defined by the claims. Further, in order to make the public have a better understanding of the present application, some specific details are described in the following detailed description of the present application. The present application can also be completely understood without the description of these details by those skilled in the art.

[0028] The pseudo-resistor circuit provided by the embodiment of the present disclosure is improved from the traditional pseudo-resistor structure shown in Figure 1 The structure of the pseudo-resistor circuit provided by the embodiment of the present disclosure is shown in Figure 2 The substrate end of the traditional pseudo-resistor PMOS tube is connected to the temperature self-adjusting bias voltage V B .

[0029] The pseudo-resistance circuit provided by the embodiments of the present disclosure comprises:

[0030] Transistors M1 and M2 connected in series, both of which are PMOS transistors, and the gates of the transistors M1 and M2 are connected and connected to a series connection point of the transistors M1 and M2; and

[0031] A bias voltage V B , which is self-adjustable with temperature, acting on the substrate end of the transistors M1 and M2.

[0032] In some embodiments, referring to Figure 3 The bias voltage V B is generated by a temperature control voltage generation circuit, which comprises:

[0033] A transistor M9 connected in diode mode, which is a PMOS transistor, the substrate end of the transistor M9 is connected to a power supply voltage V DD , and the gate voltage of the transistor M9 is the bias voltage V B which is self-adjustable with temperature;

[0034] A common-source common-gate current source for providing a bias current for the transistor M9 which is not self-adjustable with temperature and making the transistor M9 work in a sub-threshold region;

[0035] A common-source common-gate current mirror for providing a bias voltage for the common-source common-gate current source.

[0036] Further, the common-source common-gate current mirror comprises transistors M3, M4, M5 and M6 which are all NMOS transistors, the substrate ends of the transistors M3, M4, M5 and M6 are all connected to ground; the gate of the transistor M3 is connected to the gate of the transistor M4, the source of the transistor M3 is connected to ground, and the drain of the transistor M3 is connected to the source of the transistor M4; the gate of the transistor M4 is connected to the drain of the transistor M4, a reference current I ref is input to the drain of the transistor M4 to generate a voltage V b1 at the drain of the transistor M4; the gate of the transistor M5 is connected to the drain of the transistor M6, the source of the transistor M5 is connected to ground, and the drain of the transistor M5 is connected to the source of the transistor M6; the gate of the transistor M6 is connected to the voltage V b1 , and a mirror current I1 which is the same as the reference current I ref is input to the drain of the transistor M6 to generate a voltage V b2 at the drain of the transistor M6.

[0037] In some embodiments, the common-source common-gate current source is used to provide a bias current for the transistor M9 which is not subject to temperature variation, in which case, when the temperature changes, the gate voltage of the transistor M9 changes accordingly, i.e. a bias voltage V B which is subject to temperature self-adjustment is generated. The common-source common-gate current source comprises a transistor M7 and a transistor M8 which are both NMOS transistors, the substrate ends of the transistors M7 and M8 are both grounded; the gate of the transistor M7 is connected to a voltage V b2 , the source of the transistor M7 is grounded, and the drain of the transistor M7 is connected to the source of the transistor M8; the gate of the transistor M8 is connected to a voltage V b1 , and the drain of the transistor M8 is connected to the drain of the PMOS transistor M9.

[0038] Further, the sizes of the transistors M7 and M8 are proportionally reduced to sizes which can ensure that the transistor M9 operates in the sub-threshold region, so that the voltage generated by the transistor M9 is more suitable for the transistors M1 and M2.

[0039] In some embodiments ， , the transistor M9 is connected in a diode manner, the gate of the transistor M9 is connected to the drain of the transistor M8, and the source and substrate end of the transistor M9 are both connected to a power supply voltage V DD .

[0040] In some embodiments, the substrate-modulated double-tube PMOS pseudo-resistor structure is composed of transistors M1 and M2 which are PMOS transistors. Due to the symmetrical structure of the PMOS transistors, the transistor source-drain definition depends on the voltage size of the two ports in actual operation, and here it is assumed that V X > V Z > V Y . The substrate of the transistor M1 is connected to a bias voltage V B which is subject to temperature self-adjustment, the gate of the transistor M1 is connected to the gate of the transistor M2, the drain of the transistor M1 is used as the output end Y of the pseudo-resistor circuit provided in the embodiment, and the source of the transistor M1 is connected to the drain of the transistor M2; the substrate of the transistor M2 is connected to a bias voltage V B which is subject to temperature self-adjustment, the gate of the transistor M2 is connected to the drain of the transistor M2, and the source of the transistor M2 is used as the output end X of the pseudo-resistor circuit provided in the embodiment.

[0041] The complete circuit structure is composed of a temperature-controlled voltage generation circuit and a substrate-modulated double-tube PMOS pseudo-resistor, in which the voltage V B generated by the temperature-controlled voltage generation circuit is directly connected to the substrate end of the PMOS pseudo-resistor, and the ports X and Y are the two external ports of the improved pseudo-resistor.

[0042] The pseudo-resistance circuit structure provided by the embodiments of the present disclosure improves the stability of the pseudo-resistance circuit at different working temperatures based on a variable substrate compensation structure, and the working principle is as follows:

[0043] On the basis of the original PMOS pseudo-resistance circuit structure, the embodiments of the present disclosure add an environment temperature self-adjusting bias voltage to the substrate end of the PMOS pseudo-resistance. The threshold voltage V TH of the transistor is related to the substrate voltage V BS as follows:

[0044]

[0045] wherein V TH0 is the threshold voltage without considering the substrate modulation effect, γ is the body effect coefficient, and the typical value is between 0.3V 1 / 2 and 0.4V 1 / 2 . φ F =(kT / q)ln(N sub / n i ) is the Fermi potential, k is the Boltzmann constant, q is the electron charge, N sub is the doping concentration of the substrate, and n i is the intrinsic carrier concentration of silicon.

[0046] Further, the present disclosure uses the characteristic that the gate-source voltage of the transistor is self-adjusted with temperature to generate the required temperature-varying voltage by connecting the PMOS transistor in diode connection mode with the current source in series. By adjusting the size of the bias current and the transistor size, the above PMOS transistor works in the subthreshold region, and the channel current of the transistor working in the subthreshold region can be expressed as:

[0047]

[0048] wherein I0 is proportional to W / L, n>1 is a non-ideal factor, when the temperature rises, the absolute value |V TH | of the threshold voltage of the PMOS transistor decreases, the bias current is ensured to be unchanged, and then the absolute value |V GS | of the gate-source voltage of the PMOS transistor working in the subthreshold region decreases, that is, the generated pseudo-resistance substrate bias voltage increases with the increase of temperature. The conventional pseudo-resistance structure directly connects the substrate of the PMOS transistor with the source, so that the absolute value |V TH | of the threshold voltage of the PMOS transistor is greatly affected by temperature. The present disclosure makes the substrate voltage of the transistor proportional to the environment temperature, and with the increase of the substrate voltage V BS , the threshold voltage changes weaken, the equivalent resistance is affected by temperature, and the equivalent resistance value is maintained at the order of several hundred GΩ in the temperature range of -40℃-125℃.

[0049] Further, the bias current of the temperature-controlled voltage generation circuit can be provided by a reference current and a current mirror in the actual circuit. In order to avoid the variation of the output voltage aggravating the channel length modulation effect of the basic current mirror, the embodiment of the present disclosure adopts a common-source common-gate current mirror to accurately copy the reference current. Meanwhile, the bias current of the transistor M9 should be less than the actual reference current I ref , i.e. the common-source common-gate current Source source is proportionally reduced in size to ensure that the transistor M9 works in the sub-threshold region. The gate bias voltage of the common-source common-gate current source is provided by a common-source common-gate current mirror composed of transistors M3-M6, which makes the common-source common-gate current source have PVT stability while reducing the consumed voltage margin. The transistor M9 is connected between the power supply voltage and the common-source common-gate current source, generating a bias voltage that can be self-adjusted with temperature.

[0050] In the direct current bias resistance and active low-pass filter resistance applications faced by the present disclosure, the pseudo resistance circuit mainly perceives a direct current voltage or an input signal across it, and in stable operation, the variation amplitude of such signals is limited, so it can be assumed that the voltage across the pseudo resistance circuit is close. In order to ensure the substrate reverse bias of the PMOS tube in the pseudo resistance circuit, the approximate range of the voltage across the pseudo resistance circuit when it is working should be determined in advance, and then the size of the transistor M9 connected with the diode connection is adjusted to ensure that the substrate bias voltage of the transistor M1 and the transistor M2, i.e. the bias voltage V B , is always higher than the power supply voltage V DD .

[0051] The following is an embodiment of a pseudo resistance circuit of the present disclosure:

[0052] In this example, a high-temperature-stability pseudo resistance circuit based on a variable substrate compensation structure is prepared by using a 65nm CMOS process (which is a conventional preparation process in the art), and the simulation results are given by Figure 4 , Figure 5 .

[0053] Figure 4 The equivalent resistance values of the two pseudo resistances before and after improvement under the bias of 0.9V common mode voltage, TT process corner, and-40℃-125℃ environment are given. It can be seen that, with the increase of temperature, the equivalent resistance value of the pseudo resistance circuit before improvement (i.e. the existing pseudo resistance circuit shown in Figure 1 ) decreases from 600GΩ to about 0.5GΩ, while the equivalent resistance value of the pseudo resistance circuit after improvement (i.e. the pseudo resistance circuit provided by the embodiment of the present disclosure) is stable at about 400GΩ, which is significantly improved compared with before improvement. Figure 5The temperature variation of the input node RC cut-off frequency when the two kinds of pseudo-resistors are used to improve the DC bias resistance in the actual capacitance feedback circuit can be seen. It can be seen that although the low-pass cut-off frequency of the circuit in actual work will still be affected by other temperature-related parameters, using the improved pseudo-resistor circuit for DC biasing can still make the stability of the actual circuit improve by more than one order of magnitude.

[0054] In summary, the improved pseudo-resistor circuit can maintain an equivalent resistance value of several hundred GΩ within an environmental temperature range of-40 to 125℃, and can be applied to various application scenarios.

[0055] The above examples verify the correctness and effectiveness of the present disclosure. The above description is only for the high-temperature stability pseudo-resistor circuit of the present disclosure under a specific CMOS process, specific resistance value and specific application environment, and is not intended to limit the protection scope of the present disclosure.

[0056] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0057] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A pseudo-resistive circuit, characterized by, The application relates to a current source circuit, comprising: a transistor M1 and a transistor M2 connected in series, both of which are PMOS transistors, the gates of the transistors M1 and M2 being connected and connected to a series connection point of the transistors M1 and M2; and Bias voltage V that is self-adjustable with temperature B substrate terminal of the transistor M1 and the transistor M2; The temperature self-adjustable bias voltage V B generated by a temperature-controlled voltage generation circuit, the temperature-controlled voltage generation circuit comprising: The transistor M9 connected in diode mode is a PMOS transistor, the gate voltage of which is the bias voltage Vbias which is self-adjustable with temperature B ; a common-source common-gate current source for providing a bias current for the transistor M9 which does not change with temperature and enabling the transistor M9 to work in a sub-threshold region; a common-source common-gate current mirror for providing a bias voltage for the common-source common-gate current source; The source and substrate terminals of the transistor M9 are both connected to the power supply voltage V DD ; The common-source common-gate current mirror comprises transistors M3, M4, M5 and M6 which are all NMOS tubes, the substrate ends of the transistors M3, M4, M5 and M6 are all grounded; the gate of the transistor M3 is connected to the gate of the transistor M4, the source of the transistor M3 is grounded, and the drain of the transistor M3 is connected to the source of the transistor M4; the gate of the transistor M4 is connected to the drain of the transistor M4, and a reference current I ref is input to the drain of the transistor M4, so as to generate a voltage V b1 at the drain of the transistor M4; the gate of the transistor M5 is connected to the drain of the transistor M6, the source of the transistor M5 is grounded, and the drain of the transistor M5 is connected to the source of the transistor M6; the gate of the transistor M6 is connected to a voltage V b1 , and a mirror current I1 same as the reference current I ref is input to the drain of the transistor M6, so as to generate a voltage V b2 at the drain of the transistor M6; The common-source common-gate current source comprises a transistor M7 and a transistor M8 which are both NMOS tubes, the substrate ends of the transistor M7 and the transistor M8 are both grounded; the gate of the transistor M7 is connected to a voltage V b2 , the source of the transistor M7 is grounded, and the drain of the transistor M7 is connected to the source of the transistor M8; the gate of the transistor M8 is connected to a voltage V b1 , and the drain of the transistor M8 is connected to the drain of the transistor M9.

2. The pseudo-resistive circuit according to claim 1, characterized in that, the sizes of the NMOS transistors M7 and M8 are proportionally reduced to sizes which can ensure that the PMOS transistor M9 works in a sub-threshold region.

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