Pixel circuits and their driving methods

Abstract

This invention discloses a pixel circuit and its driving method. The pixel circuit includes a characteristic improvement module, which responds to a first control signal and a second control signal. During the characteristic improvement phase, the module transmits a first set voltage or a second set voltage to the first and second terminals of the driving transistor. This characteristic improvement phase is the preceding operating phase of the light-emitting phase. The technical solution of this invention ensures that the bias state of the driving transistor remains the same before entering the light-emitting phase in each frame before and after the refresh frequency switch. This improves the transient characteristics of the driving transistor, preventing sudden changes in the brightness of the light-emitting module during refresh frequency switching. Furthermore, it ensures that the bias state of the driving transistor remains the same before entering the light-emitting phase in low-frequency display write frames and hold frames, preventing sudden changes in the brightness of the light-emitting module. This helps to improve frequency switching and low-frequency flicker issues, thereby improving image display quality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit and its driving method. Background Technology

[0002] With the development of display technology, users have increasingly higher requirements for the display quality of the screen.

[0003] In the prior art, display panels include multiple display modes, and the refresh rate of the display panel is different in different display modes. For example, the refresh rate is 1Hz in the static image display mode, while the refresh rate is 120Hz in the game mode or video playback mode.

[0004] However, existing technologies suffer from poor display quality when the display panel switches between different refresh rates. Summary of the Invention

[0005] This invention provides a pixel circuit and its driving method to improve the display quality when switching between different refresh rates.

[0006] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a data writing module, a driving transistor, a characteristic improvement module, a light emission control module, and a light emission module;

[0007] The data writing module is used to write data voltage to the gate of the driving transistor during the data writing phase;

[0008] The light-emitting control module, the driving transistor, and the light-emitting module are connected in series between the first power input terminal and the second power input terminal. The light-emitting control module is used to control the connection state between the first electrode of the driving transistor and the first power input terminal, and / or to control the connection state between the second electrode of the driving transistor and the second power input terminal. The driving transistor is used to output driving current to the light-emitting module during the light-emitting stage.

[0009] The characteristic improvement module includes a first control terminal, a second control terminal, a first set voltage input terminal, a second set voltage input terminal, a first output terminal, and a second output terminal. The first output terminal is electrically connected to the first electrode of the driving transistor, and the second output terminal is electrically connected to the second electrode of the driving transistor. The characteristic improvement module is used to respond to a first control signal input from the first control terminal and a second control signal input from the second control terminal, and to transmit the first set voltage or the second set voltage to the first electrode and the second electrode of the driving transistor during the characteristic improvement stage. The first set voltage is input from the first set voltage input terminal, and the second set voltage is input from the second set voltage input terminal.

[0010] Within a single frame, the characteristic improvement stage is the preceding working stage of the emission stage.

[0011] Optionally, the feature improvement module includes a first feature improvement unit and a second feature improvement unit;

[0012] The control terminal of the first characteristic improvement unit is used as the first control terminal. The first terminal of the first characteristic improvement unit is electrically connected to the first set voltage input terminal, and the second terminal of the first characteristic improvement unit is electrically connected to the first output terminal. The first characteristic improvement unit is used to control the connection state between the first set voltage input terminal and the first output terminal according to the first control signal.

[0013] The control terminal of the second characteristic improvement unit serves as the second control terminal. The first terminal of the second characteristic improvement unit is electrically connected to the second set voltage input terminal, and the second terminal of the second characteristic improvement unit is electrically connected to the second output terminal. The second characteristic improvement unit is used to control the connection state between the second set voltage input terminal and the second output terminal according to the second control signal.

[0014] Optionally, at least during the characteristic improvement phase, both the first and second setting voltages are fixed voltages; the driving transistor is a P-type transistor.

[0015] The first set voltage is greater than the second set voltage; the first characteristic improvement unit is used to turn on in response to the first control signal during the characteristic improvement stage to transmit the first set voltage to the first and second terminals of the driving transistor; the second characteristic improvement unit is used to turn on or off in response to the second control signal during the characteristic improvement stage.

[0016] Alternatively, if the first set voltage is less than the second set voltage, the second characteristic improvement unit is used to turn on in response to the second control signal during the characteristic improvement stage to transmit the second set voltage to the first and second terminals of the driving transistor; the first characteristic improvement unit is used to turn on or off in response to the first control signal during the characteristic improvement stage.

[0017] Optionally, the pixel circuit also includes a compensation module. The control terminal of the compensation module is connected to a compensation control signal. The compensation module is connected between the second electrode and the gate of the driving transistor. The compensation module is used to turn on during the initialization phase and the data writing phase of the write frame, and to compensate the threshold voltage of the driving transistor during the data writing phase.

[0018] The second characteristic improvement unit is also used to, during the initialization phase, respond to the second control signal to turn on, so as to transmit the second set voltage to the gate of the driving transistor through the compensation module, so as to initialize the gate of the driving transistor.

[0019] Optionally, the pixel circuit further includes a first storage module and a second storage module; the first storage module is connected between the gate of the driving transistor and the first power input terminal, and the second storage module is connected between the first electrode of the driving transistor and the first power input terminal.

[0020] The compensation module is also used to continue compensating the threshold voltage of the driving transistor and the subthreshold swing of the driving transistor during the continuation compensation phase of the write frame.

[0021] The continuation compensation phase lies between the data writing phase and the feature improvement phase.

[0022] Optionally, the light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit. The first light-emitting control unit is connected between the first power input terminal and the first electrode of the driving transistor, and the control terminal of the first light-emitting control unit is connected to the first light-emitting control signal. The first light-emitting control unit is used to respond to the first light-emitting control signal to turn on during the light-emitting phase.

[0023] The second light-emitting control unit is connected between the second terminal of the driving transistor and the first terminal of the light-emitting module, and the control terminal of the second light-emitting control unit is connected to the second light-emitting control signal; the second light-emitting control unit is used to respond to the second light-emitting control signal to turn on during the light-emitting phase;

[0024] The second characteristic improvement unit is also used to respond to the second control signal being turned on during the initialization phase of the write frame, and the second light emission control unit is used to respond to the second light emission control signal being turned on during the initialization phase, so that during the initialization phase, the second characteristic improvement unit transmits the second setting voltage to the first end of the light emission module through the second light emission control unit to initialize the light emission module.

[0025] Optionally, the write frame includes a data writing phase, a feature improvement phase, and a light emission phase; the hold frame includes a feature improvement phase and a light emission phase.

[0026] Optionally, the driving transistor includes a P-type transistor, and in the same frame, the first set voltage in the write frame is less than the first set voltage in the hold frame.

[0027] Optionally, the effective level pulse duration of the first control signal within the frame is kept less than or equal to the effective level pulse duration of the first control signal written into the frame;

[0028] And / or keep the effective level pulse duration of the second control signal within the frame less than or equal to the effective level pulse duration of the second control signal written within the frame.

[0029] Secondly, embodiments of the present invention also provide a method for driving a pixel circuit, the method comprising:

[0030] During the data writing phase, the data writing module writes a data voltage to the gate of the driving transistor.

[0031] In response to a first control signal input from a first control terminal and a second control signal input from a second control terminal, the characteristic improvement module transmits a first set voltage or a second set voltage to the first and second terminals of the driving transistor during the characteristic improvement stage; wherein, the first set voltage is input from the first set voltage input terminal and the second set voltage is input from the second set voltage input terminal;

[0032] During the light-emitting stage, the light-emitting control module is turned on, and the driving transistor outputs driving current to the light-emitting module;

[0033] Within a single frame, the characteristic improvement stage is the preceding working stage of the emission stage.

[0034] The pixel circuit and its driving method according to embodiments of the present invention include a characteristic improvement module. This characteristic improvement module responds to a first control signal and a second control signal, transmitting a first set voltage or a second set voltage to the first and second terminals of the driving transistor during a characteristic improvement phase. This characteristic improvement phase is the preceding operating phase of the light-emitting phase. The technical solution of this embodiment ensures that the bias state of the driving transistor is the same before entering the light-emitting phase in each frame before and after the refresh frequency switch, thereby improving the transient characteristics of the driving transistor and preventing sudden changes in the brightness of the light-emitting module during refresh frequency switching. Furthermore, it ensures that the bias state of the driving transistor is the same before entering the light-emitting phase in low-frequency display write frames and hold frames, preventing sudden changes in the brightness of the light-emitting module and thus improving the problems of frequency switching and low-frequency flicker, thereby enhancing the image display quality. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0038] Figure 4 This is a timing diagram of the driving of a pixel circuit in a written frame, provided by an embodiment of the present invention;

[0039] Figure 5 This is a driving timing diagram of a pixel circuit in a holding frame provided by an embodiment of the present invention;

[0040] Figure 6 This is another timing diagram of the pixel circuit driving the writing frame provided in an embodiment of the present invention.

[0041] Figure 7This is another pixel circuit driving timing diagram for holding frames provided in an embodiment of the present invention.

[0042] Figure 8 This is another pixel circuit driving timing diagram for holding frames provided in an embodiment of the present invention.

[0043] Figure 9 This is a timing diagram of the pixel circuit driving the write frame and hold frame according to an embodiment of the present invention.

[0044] Figure 10 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention. Detailed Implementation

[0045] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0046] As described in the background section, existing technologies suffer from poor display quality when switching between different refresh rates. The inventors have discovered that this problem arises because the display panel includes pixel circuits, which in turn include driving transistors. At different refresh rates, the transient characteristics of the driving transistors differ significantly. This results in different driving currents generated by the driving transistors at the same grayscale level before and after the refresh rate switch. Since the brightness of the light-emitting device is directly related to the driving current, this ultimately leads to flickering on the display panel after switching from one refresh rate to another, affecting the display quality. Furthermore, at low frequencies, the transient characteristics of the driving transistors differ significantly between writing and holding frames, also resulting in poor display quality.

[0047] For the reasons stated above, embodiments of the present invention provide a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 1 The pixel circuit includes: a data writing module 110, a driving transistor DT, a characteristic improvement module 120, a light emission control module 130, and a light emission module 140;

[0048] The data writing module 110 is used to write a data voltage to the gate of the driving transistor DT during the data writing phase;

[0049] The light-emitting control module 130, the driving transistor DT, and the light-emitting module 140 are connected in series between the first power input terminal VDD and the second power input terminal VSS. The light-emitting control module 130 is used to control the connection state between the first electrode of the driving transistor DT and the first power input terminal VDD, and / or to control the connection state between the second electrode of the driving transistor DT and the second power input terminal VSS. The driving transistor DT is used to output driving current to the light-emitting module 140 during the light-emitting stage.

[0050] The characteristic improvement module 120 includes a first control terminal Ctrl1, a second control terminal Ctrl2, a first set voltage input terminal VEH1, a second set voltage input terminal VEH2, a first output terminal OUT1, and a second output terminal OUT2. The first output terminal OUT1 is electrically connected to the first terminal of the driving transistor DT, and the second output terminal OUT2 is electrically connected to the second terminal of the driving transistor DT. The characteristic improvement module 120 is used to respond to the first control signal input by the first control terminal Ctrl1 and the second control signal input by the second control terminal Ctrl2, and transmit the first set voltage or the second set voltage to the first and second terminals of the driving transistor DT during the characteristic improvement stage. The first set voltage is input by the first set voltage input terminal VEH1, and the second set voltage is input by the second set voltage input terminal VEH2. Within one frame, the characteristic improvement stage is the working stage preceding the light emission stage.

[0051] The concept of refresh frequency includes frame refresh frequency and data refresh frequency. In the frame refresh frequency concept, a frame is calculated based on the minimum period of one light-emitting phase, and a frame includes a write frame and a hold frame. In the data refresh frequency concept, data refresh is calculated based on the minimum period of the written data signal, and one data refresh cycle may include one write frame and several hold frames. In the embodiments of this invention, the refresh frequency mentioned refers to the data refresh frequency.

[0052] In this embodiment, during the write frame, the pixel circuit's operation includes at least a data writing stage, a characteristic improvement stage, and a light emission stage. During the hold frame, the pixel circuit's operation includes at least a characteristic improvement stage and a light emission stage.

[0053] The data writing module 110 can be directly or indirectly connected to the gate of the driving transistor DT, thereby writing data voltage to the gate of the driving transistor DT during the data writing stage. When the data writing module 110 is directly connected to the gate of the driving transistor DT, the compensation module 150 may not be required in the pixel circuit. When the data writing module 110 is indirectly connected to the gate of the driving transistor DT, the pixel circuit may include the compensation module 150. For example, the data writing module 110 can indirectly drive the first terminal of the driving transistor DT, one end of the compensation module 150 is connected to the second terminal of the driving transistor DT, and the other end is connected to the gate of the driving transistor DT. In other words, the data writing module 110 can be connected to the gate of the driving transistor DT through the driving transistor DT and the compensation module 150.

[0054] The pixel circuit also includes a light-emitting control module 130. The light-emitting control module 130 can be used to control the connection state between the first power input terminal VDD and the first terminal of the driving transistor DT, and / or to control the connection state between the second power input terminal VSS and the second terminal of the light-emitting module 140. Specifically, the light-emitting control module 130 is turned on at least during the light-emitting phase, connecting the first power input terminal VDD to the first terminal of the driving transistor DT, and connecting the second power input terminal VSS to the second terminal of the light-emitting module 140. The driving current output by the driving transistor DT can reach the light-emitting module 140, thereby driving the light-emitting module 140 to emit light.

[0055] The pixel circuit also includes a characteristic improvement module 120, which transmits a fixed voltage to the first and second terminals of the driving transistor DT during the characteristic improvement stage. Specifically, the characteristic improvement module 120 includes a first control terminal Ctrl1, a first set voltage input terminal VEH1, and a first output terminal OUT1, wherein the first output terminal OUT1 is connected to the first terminal of the driving transistor DT. The characteristic improvement module 120 can control the connection state between the first set voltage input terminal VEH1 and the first output terminal OUT1 according to the first control signal input to the first control terminal Ctrl1. The characteristic improvement module 120 also includes a second control terminal Ctrl2, a second set voltage input terminal VEH2, and a second output terminal OUT2, wherein the second output terminal OUT2 is connected to the second terminal of the driving transistor DT. The characteristic improvement module 120 can control the connection state between the second set voltage input terminal VEH2 and the second output terminal OUT2 according to the second control signal input to the second control terminal Ctrl2. The first terminal of the driving transistor DT is either the source or the drain, and correspondingly, the second terminal of the driving transistor DT is either the drain or the source. During the characteristic improvement phase, the characteristic improvement module 120 responds to the first control signal and the second control signal, transmitting either the first set voltage or the second set voltage to the first and second terminals of the driving transistor DT. Specifically, during the characteristic improvement phase, the operation of the characteristic improvement module 120 involves the following three scenarios:

[0056] (1) The characteristic improvement module 120 responds to the first control signal to conduct between the first set voltage input terminal VEH1 and the first output terminal OUT1, and responds to the second control signal to turn off between the second set voltage input terminal VEH2 and the second output terminal OUT2. Then the first set voltage input at the first set voltage input terminal VEH1 is transmitted to the first pole of the driving transistor DT, and is transmitted to the second pole of the driving transistor DT through the driving transistor DT.

[0057] (2) The characteristic improvement module 120 responds to the second control signal to conduct between the second set voltage input terminal VEH2 and the second output terminal OUT2, and responds to the first control signal to turn off between the first set voltage input terminal VEH1 and the first output terminal OUT1. Then the second set voltage input at the second set voltage input terminal VEH2 is transmitted to the second terminal of the driving transistor DT, and then transmitted to the first terminal of the driving transistor DT through the driving transistor DT.

[0058] (3) The characteristic improvement module 120 responds to the first control signal to conduct between the first set voltage input terminal VEH1 and the first output terminal OUT1, and responds to the second control signal to conduct between the second set voltage input terminal VEH2 and the second output terminal OUT2. When the first set voltage equals the second set voltage, after the characteristic improvement stage ends, the voltages of the first and second terminals of the driving transistor DT are equal. When the first set voltage is not equal to the second set voltage, there is a current between the first output terminal OUT1, the driving transistor DT, and the second output terminal OUT2 of the characteristic improvement module 120. When the first set voltage is greater than the second set voltage, the current flows from the first output terminal OUT1 through the driving transistor DT to the second output terminal OUT2. When the second set voltage is greater than the first set voltage, the current flows from the second output terminal OUT2 through the driving transistor DT to the first output terminal OUT1. Therefore, when the first set voltage is not equal to the second set voltage, after the characteristic improvement stage ends, the voltages of the first and second terminals of the driving transistor DT are also equal.

[0059] It should be noted that during the characteristic improvement stage, the light emission control module 130 is turned off to prevent the first power supply voltage input at the first power input terminal VDD from affecting the writing of the first set voltage or the second set voltage to the first and second terminals of the driving transistor DT.

[0060] In the characteristic improvement phase, both the first and second set voltages are fixed. As can be seen from the above description of the operation of the characteristic improvement module 120 in the characteristic improvement phase, the settings of the characteristic improvement module 120 ensure that the first and second terminals of the driving transistor DT can be written with the same voltage during the characteristic improvement phase. Regardless of whether it is a write frame or a hold frame, the characteristic improvement phase is the working phase preceding the light emission phase. This ensures that the bias state of the driving transistor DT is the same in each frame before and after the refresh frequency switch, thus improving the transient characteristics of the driving transistor DT and preventing sudden changes in the brightness of the light emission module 140 during refresh frequency switching. Furthermore, ensuring that the bias state of the driving transistor DT is the same in both the write and hold frames for low-frequency displays before entering the light emission phase prevents sudden changes in the brightness of the light emission module 140, thereby improving frequency switching and low-frequency flicker issues and enhancing display quality.

[0061] The pixel circuit of this embodiment includes a characteristic improvement module. This module responds to a first control signal and a second control signal, transmitting a first set voltage or a second set voltage to the first and second terminals of the driving transistor during a characteristic improvement phase. This characteristic improvement phase is the preceding operating phase of the light-emitting phase. This embodiment ensures that the bias state of the driving transistor remains the same before entering the light-emitting phase in each frame before and after the refresh frequency switch, thereby improving the transient characteristics of the driving transistor and preventing sudden changes in the brightness of the light-emitting module during refresh frequency switching. Furthermore, it ensures that the bias state of the driving transistor remains the same before entering the light-emitting phase in low-frequency display write frames and hold frames, preventing sudden changes in the brightness of the light-emitting module and thus improving frequency switching and low-frequency flicker issues, thereby enhancing image display quality.

[0062] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 2 Optionally, the feature improvement module 120 includes a first feature improvement unit 121 and a second feature improvement unit 122;

[0063] The control terminal of the first characteristic improvement unit 121 is designated as the first control terminal Ctrl1. The first terminal of the first characteristic improvement unit 121 is electrically connected to the first set voltage input terminal VEH1, and the second terminal of the first characteristic improvement unit 121 is electrically connected to the first output terminal OUT1. The first characteristic improvement unit 121 is used to control the connection state between the first set voltage input terminal VEH1 and the first output terminal OUT1 according to the first control signal.

[0064] The control terminal of the second characteristic improvement unit 122 is designated as the second control terminal Ctrl2. The first terminal of the second characteristic improvement unit 122 is electrically connected to the second set voltage input terminal VEH2, and the second terminal of the second characteristic improvement unit 122 is electrically connected to the second output terminal OUT2. The second characteristic improvement unit 122 is used to control the connection state between the second set voltage input terminal VEH2 and the second output terminal OUT2 according to the second control signal.

[0065] When the first control signal is an active level signal, the first characteristic improvement unit 121 is turned on, transmitting the first set voltage to the first output terminal OUT1. When the second control signal is an active level signal, the second characteristic improvement unit 122 is turned on, transmitting the second set voltage to the second output terminal OUT2. The first characteristic improvement unit 121 includes a first transistor T1, and the second characteristic improvement unit 122 includes a second transistor T2. Both the first transistor T1 and the second transistor T2 can be P-type transistors or N-type transistors. For example, when the first transistor T1 is a P-type transistor, a low-level signal is an active level signal, and a high-level signal is an inactive level signal. The same applies to the second transistor T2, and will not be elaborated further here.

[0066] In this embodiment, during both the hold frame and the write frame, at least during the feature improvement phase, both the first set voltage and the second set voltage are fixed voltages. In some optional embodiments of the present invention, both the first set voltage and the second set voltage may remain constant fixed voltages throughout the hold frame; and both the first set voltage and the second set voltage may also remain constant fixed voltages throughout the write frame.

[0067] In another optional embodiment of the present invention, in a frame (which may be a write frame or a hold frame), the first set voltage and the second set voltage are fixed voltages during the characteristic improvement phase, and in other operating phases (e.g., the data writing phase and the light emission phase), the first set voltage is a fixed voltage different from that during the characteristic improvement phase, and in other operating phases, the second set voltage is a fixed voltage different from that during the characteristic improvement phase.

[0068] When the driving transistor DT is a P-type transistor, the first set voltage is greater than the second set voltage; the first characteristic improvement unit 121 is used to turn on in response to the first control signal during the characteristic improvement stage to transmit the first set voltage to the first and second terminals of the driving transistor DT; the second characteristic improvement unit 122 is used to turn on or off in response to the second control signal during the characteristic improvement stage.

[0069] Specifically, when the driving transistor DT is a P-type transistor, the first terminal of the driving transistor DT is the source, and the second terminal is the drain. When the driving transistor DT is a P-type transistor, and the first set voltage is greater than the second set voltage, during the characteristic improvement stage, the first control signal is an active level signal, and the second control signal can be either an active or inactive level signal. This causes the first characteristic improvement unit 121 to turn on in response to the first control signal, transmitting the first set voltage to the first terminal of the driving transistor DT. The second characteristic improvement unit 122 turns on or off in response to the second control signal. When the second control signal is an active level signal, the second characteristic improvement unit 122 turns on. However, since the first set voltage is greater than the second set voltage, a current is formed in the pixel circuit that flows from the first set voltage input terminal VEH1 through the first characteristic improvement unit 121, the driving transistor DT, the second characteristic improvement unit 122, and to the second set voltage input terminal VEH2. Therefore, both the first and second terminals of the driving transistor DT are written with the first set voltage. When the second control signal is an invalid level signal, the second characteristic improvement unit 122 is turned off, and the first set voltage is transmitted to the second terminal of the driving transistor DT through the first characteristic improvement unit 121 and the driving transistor DT.

[0070] Alternatively, when the driving transistor DT is a P-type transistor, the first set voltage is less than the second set voltage. The second characteristic improvement unit 122 is used to turn on in response to the second control signal during the characteristic improvement stage to transmit the second set voltage to the first and second terminals of the driving transistor DT. The first characteristic improvement unit 121 is used to turn on or off in response to the first control signal during the characteristic improvement stage.

[0071] When the driving transistor DT is a P-type transistor and the first set voltage is less than the second set voltage, during the characteristic improvement stage, the first control signal can be either an invalid or valid level signal. The second control signal is a valid level signal, causing the second characteristic improvement unit 122 to turn on in response to the second control signal, transmitting the second set voltage to the second terminal of the driving transistor DT. The first characteristic improvement unit 121 turns on or off in response to the first control signal. When the first control signal is a valid level signal, the first characteristic improvement unit 121 turns on, but because the first set voltage is less than the second set voltage, a current is formed in the pixel circuit from the second set voltage input terminal VEH2 through the second characteristic improvement unit 122, the driving transistor DT, the first characteristic improvement unit 121, and back to the first set voltage input terminal VEH1. Therefore, both the second and first terminals of the driving transistor DT are written with the second set voltage. When the first control signal is an invalid level signal, the first characteristic improvement unit 121 is off, and the second set voltage is transmitted to the first terminal of the driving transistor DT through the second characteristic improvement unit 122 and the driving transistor DT.

[0072] The driving transistor can also be an N-type transistor. Those skilled in the art can make similar settings based on the relationship between the first set voltage and the second set voltage when the driving transistor is a P-type transistor, as well as the level states of the first control signal and the second control signal. This embodiment does not make specific limitations here.

[0073] Continue to refer to Figure 1 and Figure 2 The pixel circuit also includes a compensation module 150. The control terminal of the compensation module 150 is connected to a compensation control signal Sn. The compensation module 150 is connected between the second pole and the gate of the driving transistor DT. The compensation module 150 is used to turn on during the initialization phase and the data writing phase of the write frame, and to compensate the threshold voltage of the driving transistor DT during the data writing phase.

[0074] The second characteristic improvement unit 122 is also used to, during the initialization phase, respond to the second control signal to turn on, so as to transmit the second set voltage through the compensation module 150 to the gate of the driving transistor DT, so as to initialize the gate of the driving transistor DT.

[0075] Specifically, by setting the pixel circuit to include a compensation module 150, wherein, during the data writing stage, the compensation control signal Sn connected to the control terminal of the compensation module 150 is an effective level signal, so that the compensation module 150 is turned on during the data writing stage to compensate the threshold voltage of the driving transistor DT, thereby avoiding the impact of different threshold voltages of the driving transistor DT in different pixel circuits in the display panel on the display effect.

[0076] In this embodiment, during the initialization phase, the compensation control signal Sn is also an effective level signal, causing the compensation module 150 to be turned on during the initialization phase. During the initialization phase, the second control signal is also an effective level signal, causing the second characteristic improvement unit 122 to be turned on. The second set voltage is transmitted to the gate of the driving transistor DT through the second characteristic improvement unit 122 and the compensation module 150. During the initialization phase, the second set voltage is a voltage that can initialize the gate of the driving transistor DT, thereby achieving the initialization of the gate of the driving transistor DT. Furthermore, during the initialization phase, the second set voltage can be transmitted to the second and first terminals of the driving transistor DT, achieving the initialization of the gate, first terminal, and second terminal of the driving transistor DT, avoiding the influence of residual charge on the gate, first terminal, and second terminal of the driving transistor DT on the current frame display, which is beneficial for improving image retention.

[0077] Furthermore, this configuration eliminates the need for a separate module to initialize the gate of the driving transistor DT in the pixel circuit, resulting in a smaller number of modules and transistors, and consequently a smaller topological area, which is beneficial for increasing pixel density. On the other hand, it reduces leakage paths in the pixel circuit, allowing the gate potential of the driving transistor DT to be maintained more effectively, thus improving display performance.

[0078] Optionally, the transistors included in the compensation module 150 are oxide transistors, such as indium gallium zinc oxide transistors, to reduce leakage current.

[0079] Continue to refer to Figure 1 and Figure 2 Based on the above technical solution, optionally, the pixel circuit also includes a first storage module 160, which is connected between the gate of the driving transistor DT and the first power input terminal VDD. The first storage module 160 can store and maintain the gate potential of the driving transistor DT.

[0080] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, for reference. Figure 3 Optionally, the pixel circuit also includes a second storage module 170; the second storage module 170 is connected between the first terminal of the driving transistor DT and the first power input terminal VDD; the compensation module 150 is also used to continue to compensate the threshold voltage of the driving transistor DT and compensate the subthreshold swing of the driving transistor DT during the continuation compensation phase of the written frame; wherein the continuation compensation phase is between the data writing phase and the characteristic improvement phase.

[0081] Specifically, due to the high resolution of the display panel, the number of rows and columns of sub-pixels in the display panel is relatively large. Consequently, the data writing stage of each row of pixel circuits is relatively short, inevitably leading to insufficient compensation for the threshold voltage of the driving transistor DT. In this embodiment, during the continuous compensation stage, the compensation control signal Sn is an effective level signal. The compensation module 150 responds to this effective level signal and is turned on. The pixel circuit also includes a second storage module 170. The second storage module 170 can maintain the data voltage written to the first electrode of the driving transistor DT during the data writing stage during the continuous compensation stage. This allows the data voltage at the first electrode of the driving transistor DT to continue writing to the gate of the driving transistor DT through the driving transistor DT and the compensation module 150. This enables the compensation module 150 to continue compensating for the threshold voltage of the driving transistor DT during the continuous compensation stage, thereby ensuring that the threshold voltage of the driving transistor DT is fully compensated and improving the display effect.

[0082] Furthermore, during the continuation compensation phase, the subthreshold swing of the driving transistor DT can also be compensated. The subthreshold swing, also known as the S-factor, is numerically equal to the gate voltage increment required to change the drive current between the source and drain of the driving transistor DT by an order of magnitude. The magnitude of the subthreshold swing affects the magnitude of the drive current generated by the driving transistor DT. For two driving transistors DT with different subthreshold swings, even with the same gate-source voltage difference, the magnitude of the drive current generated by the driving transistor DT will differ. Therefore, compensating for the subthreshold swing of the driving transistor DT during the continuation compensation phase is beneficial for further improving the display effect.

[0083] Continue to refer to Figures 1-3 Optionally, the light-emitting control module 130 includes a first light-emitting control unit 131 and a second light-emitting control unit 132. The first light-emitting control unit 131 is connected between the first power input terminal VDD and the first pole of the driving transistor DT, and the control terminal of the first light-emitting control unit 131 is connected to the first light-emitting control signal EM1. The first light-emitting control unit 131 is used to respond to the first light-emitting control signal EM1 to turn on during the light-emitting stage.

[0084] The second light-emitting control unit 132 is connected between the second terminal of the driving transistor DT and the first terminal of the light-emitting module 140, and the control terminal of the second light-emitting control unit 132 is connected to the second light-emitting control signal EM2; the second light-emitting control unit 132 is used to respond to the second light-emitting control signal EM2 to turn on during the light-emitting stage.

[0085] The second characteristic improvement unit 122 is also used to respond to the second control signal to turn on during the initialization phase of the write frame, and the second light emission control unit 132 is used to respond to the second light emission control signal EM2 to turn on during the initialization phase, so that during the initialization phase, the second characteristic improvement unit 122 transmits the second setting voltage to the first end of the light emission module 140 through the second light emission control unit 132 to initialize the light emission module 140.

[0086] Specifically, the first light-emitting control unit 131 controls the connection state between the first power input terminal VDD and the first terminal of the driving transistor DT according to the first light-emitting control signal EM1, and the second light-emitting control unit 132 controls the connection state between the second terminal of the driving transistor DT and the second terminal of the light-emitting module 140 according to the second light-emitting control signal EM2. During the light-emitting phase, both the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are active, causing both the first light-emitting control unit 131 and the second light-emitting control unit 132 to be turned on, and the driving current generated by the driving transistor DT is output to the light-emitting module 140 to drive the light-emitting module 140 to emit light.

[0087] Furthermore, during the initialization phase, the second light-emitting control signal EM2 is at a valid level, causing the second light-emitting control unit 132 to conduct during the initialization phase. During the initialization phase, the second control signal is also at a valid level, causing the second characteristic improvement unit 122 to conduct during the initialization phase. The second set voltage is transmitted to the first terminal of the light-emitting module 140 through the second characteristic writing unit and the second light-emitting control unit 132. During the initialization phase, the second set voltage is a voltage sufficient to initialize the first terminal of the light-emitting module 140, thereby achieving the initialization of the first terminal of the light-emitting module 140. This configuration eliminates the need for a separate module for initializing the light-emitting module 140 in the pixel circuit, resulting in a smaller number of modules and transistors in the pixel circuit, leading to a smaller topological area and improved pixel density.

[0088] Continue to refer to Figure 3 The first characteristic improvement unit 121 includes a first transistor T1, and the second characteristic improvement unit 122 includes a second transistor T2.

[0089] The control terminal of the data writing module 110 is connected to the scan signal S1. The first terminal of the data writing module 110 is connected to the data voltage input terminal Vdata, and the second terminal of the data writing module 110 is connected to the first electrode of the driving transistor DT. The data writing module 110 includes a second transistor T2. The control terminal of the compensation module 150 is connected to the compensation control signal Sn. The first terminal of the compensation module 150 is connected to the second electrode of the driving transistor DT, and the second terminal of the compensation module 150 is connected to the gate of the driving transistor DT. The compensation module 150 includes a fourth transistor T4. The first light-emitting control unit 131 of the light-emitting control module 130 includes a fifth transistor T5, and the second light-emitting control unit 132 of the light-emitting control module 130 includes a sixth transistor T6.

[0090] Optional, Figure 3 In the circuit shown, the fourth transistor T4 is an oxide transistor, which is an N-type transistor, while the other transistors are all P-type transistors. The first storage module 160 includes a first capacitor C1, and the second storage module 170 includes a second capacitor C2. Figure 4 This is a driving timing diagram of a pixel circuit during frame writing, provided by an embodiment of the present invention. This driving timing can be used to drive... Figure 3 The pixel circuit shown. (Reference) Figure 3 and Figure 4 During frame writing, the pixel circuit's operation includes sequentially performed initialization phase t1, data writing phase t2, continuity compensation phase t3, characteristic improvement phase t4, and light emission phase t5.

[0091] During initialization phase t1, the second control signal is low, the second transistor T2 is turned on, and the second set voltage is transmitted to the second terminal of the driving transistor DT through the second transistor T2; the second light emission control signal EM2 is low, and the sixth transistor T6 is turned on. The second set voltage is transmitted to the first terminal of the light emission module 140 through the second transistor T2 and the sixth transistor T6, where the first terminal of the light emission module 140 can be the anode of the light emission device, thereby initializing the anode of the light emission device. When the compensation control signal Sn is high, the fourth transistor T4 is turned on, and the second set voltage is also transmitted to the gate of the driving transistor DT through the second transistor T2 and the fourth transistor T4, thus initializing the gate of the driving transistor DT; and the second set voltage is also transmitted from the second terminal of the driving transistor DT to the first terminal of the driving transistor DT, thereby simultaneously initializing the gate, the first terminal, and the second terminal of the driving transistor DT, which helps to improve the afterimage phenomenon. As can be seen from the above analysis of the working process of the pixel circuit in the initialization stage t1, the first terminal of the light-emitting module 140 can be initialized by the second transistor T2 and the sixth transistor T6, and the gate of the driving transistor DT can be initialized by the second transistor T2 and the fourth transistor T4. This eliminates the need to set separate transistors for initializing the first terminal of the light-emitting module 140 and the gate of the driving transistor DT in the pixel circuit, thereby reducing the number of devices in the pixel circuit and improving pixel density.

[0092] During the data writing phase t2, the scan signal S1 is low and the compensation control signal Sn is high. The third transistor T3 turns on in response to the low-level scan signal S1, and the fourth transistor T4 turns on in response to the high-level compensation control signal Sn. The data voltage input at the data voltage input terminal Vdata is transmitted to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the fourth transistor T4, realizing the writing of the data voltage and preliminary compensation of the threshold voltage of the driving transistor DT. Simultaneously, the data voltage at the first terminal of the driving transistor DT is stored in the second capacitor C2. Because the time of the data writing phase t2 within a frame is limited, the preliminary compensation of the threshold voltage of the driving transistor DT during the data writing phase t2 may be insufficient. In this embodiment, the threshold voltage of the driving transistor DT can be further compensated through the following extended compensation phase t3.

[0093] During the compensation continuation phase t3, the compensation control signal Sn is high, and other control signals for the pixel circuit (including the scan signal S1, the first control signal, the second control signal, the first light emission control signal EM1, and the second light emission control signal EM2) are also high. The fourth transistor T4 turns on in response to the high-level compensation control signal Sn, the driving transistor DT is weakly turned on, and all other transistors are turned off. The data voltage stored in the second capacitor C2 continues to charge the gate of the driving transistor DT, continuing to compensate for the threshold voltage of the driving transistor DT. Furthermore, during this phase, compensation can be performed on the subthreshold swing of the driving transistor DT.

[0094] In the characteristic improvement stage t4, the first control signal is low, and the compensation control signal Sn is low. The first transistor T1 turns on in response to the low-level first control signal, transmitting the first set voltage to the first terminal of the driving transistor DT. In the characteristic improvement stage t4, the first set voltage is the voltage required to turn on the driving transistor DT, allowing the first set voltage to be transmitted to the second terminal of the driving transistor DT. Therefore, at different refresh frequencies, the voltage at the first terminal of the driving transistor DT in the characteristic improvement stage t4 is the same, and the voltage at the second terminal of the driving transistor DT is also the same. Furthermore, there is voltage stress between the gate and source of the driving transistor DT, and current stress exists when the driving transistor DT is turned on. This can alter the transient characteristics of the driving transistor DT, making its transient characteristics more consistent at different refresh frequencies, which is beneficial for improving the inconsistency in brightness at the same grayscale before and after frequency switching. It should be noted that... Figure 4 The diagram schematically illustrates the case where the falling edge of the first light-emitting control signal EM1 precedes the falling edge of the second light-emitting control signal EM2. In some optional embodiments of the present invention, the falling edge of the first light-emitting control signal EM1 may coincide with the falling edge of the second light-emitting control signal EM2, so that the first light-emitting control unit 131 and the second light-emitting control unit 132 are turned on simultaneously, so that before entering the light-emitting stage t5, the first and second terminals of the driving transistor DT are both at the first set voltage.

[0095] During the light-emitting stage t5, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both at low level, and the fifth transistor T5 and the sixth transistor T6 are both turned on, driving the driving transistor DT to drive the light-emitting module 140 to emit light.

[0096] Figure 5 This is a driving timing diagram of a pixel circuit in a holding frame provided by an embodiment of the present invention. This driving timing can be used to drive... Figure 3 The pixel circuit shown. (Reference) Figure 3 and Figure 5 During frame holding, the pixel circuit's operation includes a sequential initialization phase t1, a characteristic improvement phase t4, and an emission phase t5.

[0097] During the initialization phase t1, the second control signal is low, the second transistor T2 is turned on, and the second set voltage is transmitted to the second terminal of the driving transistor DT through the second transistor T2; the second light-emitting control signal EM2 is low, and the sixth transistor T6 is turned on. The second set voltage is transmitted to the first terminal of the light-emitting module 140 through the second transistor T2 and the sixth transistor T6, wherein the first terminal of the light-emitting module 140 can be the anode of the light-emitting device, thereby realizing the initialization of the anode of the light-emitting device.

[0098] During the characteristic improvement stage t4, the first control signal is low, and the compensation control signal Sn is low. The first transistor T1 turns on in response to the low-level first control signal, transmitting the first set voltage to the first terminal of the driving transistor DT. In the characteristic improvement stage t4, the first set voltage is the voltage required to turn on the driving transistor DT, allowing it to be transmitted to the second terminal of the driving transistor DT. Therefore, at different refresh frequencies, the voltage at the first terminal of the driving transistor DT in the characteristic improvement stage t4 is the same, and the voltage at the second terminal of the driving transistor DT is also the same. Furthermore, there is voltage stress between the gate and source of the driving transistor DT, and current stress exists when the driving transistor DT is turned on. This alters the transient characteristics of the driving transistor DT, making its transient characteristics more consistent at different refresh frequencies, which helps to improve the inconsistency in brightness at the same grayscale before and after frequency switching.

[0099] During the light-emitting stage t5, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both at low level, and the fifth transistor T5 and the sixth transistor T6 are both turned on, driving the driving transistor DT to drive the light-emitting module 140 to emit light.

[0100] Figure 6 This is another driving timing diagram of the pixel circuit in the write frame provided by an embodiment of the present invention. This driving timing can be used to drive... Figure 3 The pixel circuit shown. (Reference) Figure 3 and Figure 6 During frame writing, the pixel circuit's operation includes a sequential initialization phase t1, a data writing phase t2, a duration compensation phase t3, a characteristic improvement phase t4, and a light emission phase t5. The operation of the pixel circuit in the initialization phase t1, data writing phase t2, duration compensation phase t3, and light emission phase t5 are respectively related to... Figure 4 The initialization phase t1, data writing phase t2, continuation compensation phase t3, and light emission phase t5 under the driving timing are the same, and will not be described again here.

[0101] Figure 6 The driving timing shown is Figure 4The difference in the driving timing shown is that, during the characteristic improvement stage t4, the second control signal is a low-level signal. Therefore, during the characteristic improvement stage, the second transistor T2 is also turned on. There is a current path between the first set voltage input terminal VEH1 and the second set voltage input terminal VEH2. For example, when the first set voltage is greater than the second set voltage, the current in the current path flows from the first set voltage input terminal VEH1 through the first transistor T1, the driving transistor DT, and the second transistor T2 to the second set voltage input terminal VEH2.

[0102] Figure 7 This is another driving timing diagram of a pixel circuit in a holding frame provided by an embodiment of the present invention. This driving timing can be used to drive... Figure 3 The pixel circuit shown. (Reference) Figure 3 and Figure 7 During frame holding, the pixel circuit's operation includes a sequential initialization phase t1, a characteristic improvement phase t4, and an emission phase t5. The pixel circuit's operation during initialization phase t1 and emission phase t5 is respectively related to... Figure 5 The initialization phase t1 and the light emission phase t5 under the driving timing are the same, and will not be described again here.

[0103] Figure 7 The driving timing shown is Figure 5 The difference in the driving timing shown is that, during the characteristic improvement stage, the second control signal is a low-level signal. Therefore, during the characteristic improvement stage, the second transistor T2 is also turned on. There is a current path between the first set voltage input terminal VEH1 and the second set voltage input terminal VEH2. For example, when the first set voltage is greater than the second set voltage, the current in the current path flows from the first set voltage input terminal VEH1 through the first transistor T1, the driving transistor DT, and the second transistor T2 to the second set voltage input terminal VEH2.

[0104] In the pixel circuit of this invention, except for the data writing stage t2, the time of other working stages can be adjusted. That is, the effective level pulse width of the compensation control signal Sn, the first control signal, the second control signal, the first light emission control signal EM1, and the second light emission control signal EM2 can all be adjusted, which is beneficial to realizing wideband display.

[0105] Based on the above technical solution, optionally, the driving transistor DT includes a P-type transistor, and in the same frame, the first set voltage in the write frame is less than the first set voltage in the hold frame.

[0106] Specifically, in the write frame, during the data writing phase t2 and the light emission phase t5, the gate-source voltage difference of the driving transistor DT is less than 0, and the driving transistor DT is negatively biased. The hold frame does not include the data writing phase t2; therefore, the negative bias time of the driving transistor DT in the write frame is longer than that in the hold frame. In this embodiment, by setting a first set voltage within the write frame to be less than a first set voltage within the hold frame, the degree of negative bias of the driving transistor DT during the characteristic improvement phase in the write frame is weaker than that during the characteristic improvement phase in the hold frame. This balances the difference in transient characteristics of the driving transistor DT caused by the longer negative bias time of the driving transistor DT in the write frame compared to the hold frame, thus making the transient characteristics of the driving transistor DT in the write frame and hold frame more consistent, further improving the display quality.

[0107] Combination Figures 4-7 Regardless of whether it's a write frame or a hold frame, the first and second set voltages remain constant. Therefore, the first set voltage can be adjusted during the gap between the write and hold frames, so that the first set voltage in the write frame is lower than that in the hold frame. This eliminates the need for the first set voltage to change within the frame, thus saving power.

[0108] Figure 8 This is another pixel circuit driving timing diagram for holding frames provided in an embodiment of the present invention. Figure 8 and Figure 7 The difference is that the first set voltage changes within the holding frame.

[0109] In the characteristic improvement stage of writing frames and the characteristic improvement stage of holding frames, the magnitude of the second set voltage can be equal or unequal, and this embodiment does not make specific limitations here.

[0110] Based on the above technical solution, optionally, the effective level pulse duration of the first control signal within the frame is kept less than or equal to the effective level pulse duration of the first control signal written into the frame; and / or the effective level pulse duration of the second control signal within the frame is kept less than or equal to the effective level pulse duration of the second control signal written into the frame.

[0111] Specifically, because the scan signal, compensation control signal, first light emission control signal, second light emission control signal, first control signal, and second control signal all have transitions within the write frame; while within the hold frame, the scan signal and compensation control signal do not have transitions, but the first light emission control signal, second light emission control signal, first control signal, and second control signal do have transitions, the effective level pulse duration of the first control signal within the hold frame can be set to be less than or equal to the effective level pulse duration of the first control signal within the write frame; the effective level pulse duration of the second control signal within the hold frame can be less than or equal to the effective level pulse duration of the second control signal within the write frame; the effective level pulse duration of the first light emission control signal within the hold frame can be less than or equal to the effective level pulse duration of the first light emission control signal within the write frame; the effective level pulse duration of the second light emission control signal within the hold frame can be less than or equal to the effective level pulse duration of the second light emission control signal within the write frame. This allows for further modification of the transient characteristics of the driving transistor by adjusting the effective level pulse durations of the first and second control signals within the hold frame, reducing the differences in transient characteristics of the driving transistor at different refresh frequencies, as well as the differences in transient characteristics of the driving transistor between the write frame and the hold frame, thereby improving the display quality.

[0112] Figure 9 This invention provides a driving timing diagram for a pixel circuit during the writing and holding of frames. This driving timing can be used to drive... Figure 3 The pixel circuit shown has a driving timing sequence corresponding to a refresh rate of 1Hz, comprising one write frame and multiple hold frames within 1 second. (Reference) Figure 9 For example, the write frame time is 8.3ms, and the write frame is driven at 120Hz. The remaining frames are hold frames (totaling 0.9917ms), and the hold frames can be driven at 120Hz, 240Hz, 480Hz, or higher frequencies. During the write frame, the pixel circuit's operation includes a sequential initialization phase t1, a data writing phase t2, a continuity compensation phase t3, a characteristic improvement phase t4, and a light emission phase t5. During the hold frame, the pixel circuit's operation includes a sequential initialization phase t1, a characteristic improvement phase t4, and a light emission phase t5. The specific operation processes of each stage in the write and hold frames are the same as in the above embodiment and will not be repeated here.

[0113] This invention also provides a pixel circuit driving method, which is used to drive the pixel circuit of any of the above embodiments of this invention. Figure 10 This is a flowchart of a pixel circuit driving method provided in an embodiment of the present invention, see reference. Figure 10 The driving method for this pixel circuit includes:

[0114] Step 210: The data writing module writes data voltage to the gate of the driving transistor during the data writing stage.

[0115] Step 220: In response to the first control signal input at the first control terminal and the second control signal input at the second control terminal, the characteristic improvement module transmits the first set voltage or the second set voltage to the first and second terminals of the driving transistor during the characteristic improvement stage.

[0116] The first set voltage is input from the first set voltage input terminal, and the second set voltage is input from the second set voltage input terminal.

[0117] Step 230: During the light-emitting stage, the light-emitting control module is turned on, and the driving transistor outputs driving current to the light-emitting module.

[0118] Within a single frame, the characteristic improvement stage is the preceding working stage of the emission stage.

[0119] The driving method for the pixel circuit is used to drive the pixel circuit of any of the above embodiments of the present invention, and has the beneficial effects of the driving method for the pixel circuit of any of the above embodiments of the present invention.

[0120] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, include: Data writing module, driving transistor, characteristic improvement module, light emission control module, and light emission module; The data writing module is used to write a data voltage to the gate of the driving transistor during the data writing phase; The light-emitting control module, the driving transistor, and the light-emitting module are connected in series between the first power input terminal and the second power input terminal. The light-emitting control module is used to control the connection state between the first electrode of the driving transistor and the first power input terminal, and / or to control the connection state between the second electrode of the driving transistor and the second power input terminal. The driving transistor is used to output driving current to the light-emitting module during the light-emitting phase. The characteristic improvement module includes a first control terminal, a second control terminal, a first set voltage input terminal, a second set voltage input terminal, a first output terminal, and a second output terminal; the first output terminal is electrically connected to the first electrode of the driving transistor, and the second output terminal is electrically connected to the second electrode of the driving transistor; the characteristic improvement module is used to respond to a first control signal input from the first control terminal and a second control signal input from the second control terminal, and transmit the first set voltage or the second set voltage to the first electrode and the second electrode of the driving transistor during the characteristic improvement stage; wherein, the first set voltage is input from the first set voltage input terminal, and the second set voltage is input from the second set voltage input terminal; Within a single frame, the characteristic improvement stage is the preceding working stage of the light emission stage; the characteristic improvement module includes a first characteristic improvement unit and a second characteristic improvement unit; the first characteristic improvement unit includes a first transistor, and the second characteristic improvement unit includes a second transistor; The first characteristic improvement unit is used to control the connection state between the first set voltage input terminal and the first output terminal according to the first control signal; The second characteristic improvement unit is used to control the connection state between the second set voltage input terminal and the second output terminal according to the second control signal; at least in the characteristic improvement stage, the first set voltage and the second set voltage are both fixed voltages; the driving transistor is a P-type transistor; The first set voltage is greater than the second set voltage; the first characteristic improvement unit is configured to turn on in response to the first control signal during the characteristic improvement phase to transmit the first set voltage to the first and second terminals of the driving transistor; the second characteristic improvement unit is configured to turn on or off in response to the second control signal during the characteristic improvement phase. Alternatively, if the first set voltage is less than the second set voltage, the second characteristic improvement unit is configured to, during the characteristic improvement phase, turn on in response to the second control signal to transmit the second set voltage to the first and second terminals of the driving transistor; the first characteristic improvement unit is configured to, during the characteristic improvement phase, turn on or off in response to the first control signal.

2. The pixel circuit according to claim 1, characterized in that, The control terminal of the first characteristic improvement unit serves as the first control terminal, the first terminal of the first characteristic improvement unit is electrically connected to the first set voltage input terminal, and the second terminal of the first characteristic improvement unit is electrically connected to the first output terminal. The control terminal of the second characteristic improvement unit serves as the second control terminal. The first terminal of the second characteristic improvement unit is electrically connected to the second set voltage input terminal, and the second terminal of the second characteristic improvement unit is electrically connected to the second output terminal.

3. The pixel circuit according to claim 1, characterized in that, It also includes a compensation module, the control terminal of which is connected to a compensation control signal, and the compensation module is connected between the second electrode and the gate of the driving transistor; the compensation module is used to be turned on during the initialization phase of the write frame and the data write phase, and to compensate the threshold voltage of the driving transistor during the data write phase; The second characteristic improvement unit is further configured to, during the initialization phase, respond to the second control signal to conduct, so as to transmit the second set voltage through the compensation module to the gate of the driving transistor, so as to initialize the gate of the driving transistor.

4. The pixel circuit according to claim 3, characterized in that, It also includes a first storage module and a second storage module; the first storage module is connected between the gate of the driving transistor and the first power input terminal, and the second storage module is connected between the first electrode of the driving transistor and the first power input terminal; The compensation module is also used to continue to compensate the threshold voltage of the driving transistor and the subthreshold swing of the driving transistor during the continuation compensation phase of the write frame. The continuous compensation phase is situated between the data writing phase and the feature improvement phase.

5. The pixel circuit according to claim 1, characterized in that, The light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit. The first light-emitting control unit is connected between the first power input terminal and the first electrode of the driving transistor, and the control terminal of the first light-emitting control unit is connected to a first light-emitting control signal. The first light-emitting control unit is used to respond to the first light-emitting control signal to turn on during the light-emitting phase. The second light-emitting control unit is connected between the second terminal of the driving transistor and the first terminal of the light-emitting module, and the control terminal of the second light-emitting control unit is connected to the second light-emitting control signal; the second light-emitting control unit is used to respond to the second light-emitting control signal to turn on during the light-emitting phase; The second feature improvement unit is further configured to respond to the second control signal being turned on during the initialization phase of the write frame, and the second light emission control unit is configured to respond to the second light emission control signal being turned on during the initialization phase, so that during the initialization phase, the second feature improvement unit transmits the second set voltage to the first end of the light emission module through the second light emission control unit to initialize the light emission module.

6. The pixel circuit according to claim 1, characterized in that, The write frame includes the data write phase, the feature improvement phase, and the light emission phase; the hold frame includes the feature improvement phase and the light emission phase.

7. The pixel circuit according to claim 6, characterized in that, The driving transistor includes a P-type transistor. In the same frame, the first set voltage in the write frame is less than the first set voltage in the hold frame.

8. The pixel circuit according to claim 6, characterized in that, The effective level pulse duration of the first control signal in the hold frame is less than or equal to the effective level pulse duration of the first control signal in the write frame; And / or the effective level pulse duration of the second control signal within the hold frame is less than or equal to the effective level pulse duration of the second control signal within the write frame.

9. A driving method for a pixel circuit, characterized in that, include: During the data writing phase, the data writing module writes a data voltage to the gate of the driving transistor. In response to a first control signal input from a first control terminal and a second control signal input from a second control terminal, the characteristic improvement module transmits a first set voltage or a second set voltage to the first and second terminals of the driving transistor during the characteristic improvement stage; wherein, the first set voltage is input from the first set voltage input terminal and the second set voltage is input from the second set voltage input terminal; During the light-emitting stage, the light-emitting control module is turned on, and the driving transistor outputs driving current to the light-emitting module. Within a single frame, the characteristic improvement phase is the preceding working phase of the luminescence phase; The characteristic improvement module includes a first characteristic improvement unit and a second characteristic improvement unit; the first characteristic improvement unit includes a first transistor, and the second characteristic improvement unit includes a second transistor. The first characteristic improvement unit is used to control the connection state between the first set voltage input terminal and the first output terminal according to the first control signal; The second characteristic improvement unit is used to control the connection state between the second set voltage input terminal and the second output terminal according to the second control signal; the first output terminal is electrically connected to the first electrode of the driving transistor, and the second output terminal is electrically connected to the second electrode of the driving transistor; At least during the characteristic improvement phase, both the first set voltage and the second set voltage are fixed voltages; the driving transistor is a P-type transistor; The first set voltage is greater than the second set voltage; the first characteristic improvement unit is configured to turn on in response to the first control signal during the characteristic improvement phase to transmit the first set voltage to the first and second terminals of the driving transistor; the second characteristic improvement unit is configured to turn on or off in response to the second control signal during the characteristic improvement phase. Alternatively, if the first set voltage is less than the second set voltage, the second characteristic improvement unit is configured to, during the characteristic improvement phase, turn on in response to the second control signal to transmit the second set voltage to the first and second terminals of the driving transistor; the first characteristic improvement unit is configured to, during the characteristic improvement phase, turn on or off in response to the first control signal.

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