Pixel circuit, display panel and display device

Abstract

Embodiments of the present application provide a pixel circuit, a display panel and a display device. The pixel circuit comprises a driving transistor, a storage capacitor, a compensation module and a voltage control module. The gate of the driving transistor is connected to a first node, and the driving transistor is used to generate a driving current in a light-emitting stage of the pixel circuit. The first plate of the storage capacitor is connected to the first node, and the second plate of the storage capacitor is connected to a second node. The storage capacitor is used to store a data voltage written to the gate of the driving transistor. The output of the compensation module is connected to the second node, and one input of the compensation module receives a first power voltage. The compensation module is used to compensate for the deviation of the first power voltage affecting the driving current. The voltage control module is connected to the second node, and is used to control the fluctuation of the voltage of the second node before the light-emitting stage. Embodiments of the present application can improve display uniformity and improve display effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a display panel and a display device. BACKGROUND

[0002] The display panel in the prior art includes a pixel circuit, which is used to drive a light-emitting device to emit light. The light-emitting device can be a light-emitting diode (LED), such as a mini LED or a micro LED. The light-emitting device can also be an organic light-emitting diode (OLED). The pixel circuit includes a driving transistor. In the operation of the pixel circuit, a data voltage is written to the gate of the driving transistor. The driving transistor generates a driving current under the control of the voltage difference between the gate and the source of the driving transistor. The light-emitting device emits light under the control of the driving current. However, the display panel in the prior art has the problem of poor display uniformity under the driving of the existing pixel circuit, which affects the display effect. SUMMARY

[0003] Embodiments of the present application provide a pixel circuit, a display panel and a display device to solve the technical problem of improving display uniformity and display effect.

[0004] In a first aspect, embodiments of the present application provide a pixel circuit, which includes:

[0005] a driving transistor, a gate of the driving transistor being connected to a first node, the driving transistor being configured to generate a driving current in a light-emitting phase of the operation of the pixel circuit;

[0006] a storage capacitor, a first plate of the storage capacitor being connected to the first node, a second plate of the storage capacitor being connected to a second node, the storage capacitor being configured to store a data voltage written to the gate of the driving transistor;

[0007] a compensation module, an output of the compensation module being connected to the second node, one input of the compensation module receiving a first power supply voltage, the compensation module being configured to compensate for a deviation of the first power supply voltage affecting the driving current;

[0008] a pressure control module, the pressure control module being connected to the second node, the pressure control module being configured to control a fluctuation of the voltage of the second node before the light-emitting phase.

[0009] In a second aspect, based on the same inventive concept, embodiments of the present application provide a display panel, which includes the pixel circuit provided by any of the embodiments of the present application.

[0010] In a third aspect, based on the same inventive concept, embodiments of the present application provide a display device, which includes the display panel provided by any of the embodiments of the present application.

[0011] The pixel circuit, the display panel and the display device provided by the embodiment of the present application have the following beneficial effects: the pixel circuit comprises a driving transistor and a storage capacitor, a gate of the driving transistor and a first plate of the storage capacitor are connected to a first node, and a second plate of the storage capacitor is connected to a second node. The pixel circuit further comprises a compensation module and a voltage control module connected to the second node, and the storage capacitor is connected to a first power supply voltage through the compensation module. The compensation module is used to compensate for the deviation of the first power supply voltage which affects the driving current, so that the driving current is no longer affected by the deviation of the first power supply voltage, and the deviation of the first power supply voltage is avoided to cause display unevenness. In addition, the voltage control module is used to control the fluctuation of the voltage of the second node before the light-emitting stage. Since the voltage between the two plates of the storage capacitor cannot be abruptly changed, the voltage fluctuation of the second node is controlled, so that the voltage fluctuation of the first node is controlled, and the voltage fluctuation of the first node is avoided to affect the driving current, so that the display uniformity is improved, and the display effect is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0013] Figure 1 It is a schematic diagram of a pixel circuit in a related art;

[0014] Figure 2 It is a schematic diagram of a pixel circuit provided by the embodiment of the present application;

[0015] Figure 3 It is Figure 2 It is a timing diagram of a pixel circuit in the embodiment;

[0016] Figure 4 It is Figure 2 It is a schematic diagram of the simulation test result of the working of the pixel circuit in the embodiment;

[0017] Figure 5 It is a schematic diagram of a pixel circuit provided by the embodiment of the present application;

[0018] Figure 6 It is a schematic diagram of another pixel circuit provided by the embodiment of the present application;

[0019] Figure 7 It is a schematic diagram of another pixel circuit provided by the embodiment of the present application;

[0020] Figure 8 It is Figure 7A timing diagram of the pixel circuit provided by the embodiment;

[0021] Figure 9 Another schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 6;

[0022] Figure 10 Another schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 6;

[0023] Figure 11 For Figure 10 A simulation test result diagram of the operation of the pixel circuit of the embodiment is shown in FIG. 6;

[0024] Figure 12 Another schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 6;

[0025] Figure 13 Another schematic diagram of the pixel circuit provided by the embodiment of the present application is shown in FIG. 6;

[0026] Figure 14 For Figure 13 A simulation test result diagram of the operation of the pixel circuit of the embodiment is shown in FIG. 6;

[0027] Figure 15 A schematic diagram of the display panel provided by the embodiment of the present application is shown in FIG. 6;

[0028] Figure 16 A schematic diagram of the display panel provided by the embodiment of the present application is shown in FIG. 6. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0030] The terms used in the embodiments of the present application are merely for the purpose of describing particular embodiments and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0031] Figure 1 A schematic diagram of a pixel circuit in a related art is shown in FIG. 6; Figure 1As shown, the pixel circuit includes a driving transistor Ml, a gate reset transistor M2, an anode reset transistor M3, a data write transistor M4, a threshold compensation transistor M5, a first light emitting control transistor M6, a second light emitting control transistor M7, and a storage capacitor C. The gate of the driving transistor Ml is connected to a node N-l, the source of the driving transistor Ml is connected to a node N-2, and the drain of the driving transistor Ml is connected to a node N-3. The gate reset transistor M2 is connected to the node N-l, and the anode reset transistor M3 is connected to the anode of the light emitting device P. The gate of the gate reset transistor M2 and the gate of the anode reset transistor M3 receive a scan signal S2, and both the gate reset transistor M2 and the anode reset transistor M3 receive a reset signal Vref. The data write transistor M4 is connected to the node N-2, and the threshold compensation transistor M5 is connected in series between the node N-l and the node N-3. The gate of the data write transistor M4 and the gate of the threshold compensation transistor M5 receive a scan signal S l. The gates of the first light emitting control transistor M6 and the second light emitting control transistor M7 receive a light emitting control signal E, the source of the first light emitting control transistor M6 receives a positive power supply voltage Pvdd, the drain of the first light emitting control transistor M6 is connected to the node N-2, the source of the second light emitting control transistor M7 is connected to the node N-3, and the drain of the second light emitting control transistor M7 is connected to the anode of the light emitting device P. In addition, the cathode of the light emitting device P receives a negative power supply voltage Pvee. In the operation of the pixel circuit, the driving transistor Ml generates a driving current I d = K * (Vdata - Pvdd) d which is provided to the light emitting device P to control the light emitting device P to emit light. The driving current I d = K * (Vdata - Pvdd) 2 , K being a constant related to the driving transistor.

[0032] In the display panel, a plurality of pixel circuits are provided, and the pixel circuits at different positions in the panel receive different positive power supply voltages Pvdd due to the impedance of the signal line providing the positive power supply voltage Pvdd, and the voltage drop in the signal line when current flows in the signal line. Due to the voltage drop, the positive power supply voltage Pvdd received by the pixel circuits at different positions connected to the signal line is different. The greater the sum of the driving currents in the pixel circuits connected to the signal line, the greater the deviation of the positive power supply voltage Pvdd. The deviation of the positive power supply voltage Pvdd refers to the difference between the voltage actually received by the pixel circuit and the voltage provided by the driving chip. The deviation of the positive power supply voltage Pvdd affects the size of the driving current I d , and further affects the light emitting brightness of the pixel, causing display unevenness.

[0033] In order to solve the problems in the prior art, the pixel circuit provided by the embodiment of the present application is provided with a compensation module and a voltage control module, the compensation module is used to compensate the deviation of the power supply voltage affecting the driving current, and the voltage control module is used to indirectly control the fluctuation of the gate voltage of the driving transistor, so that the driving current output by the pixel circuit is not affected by the voltage fluctuation, and the display uniformity can be improved when the pixel circuit is applied to a display panel. Figure 2 A pixel circuit schematic diagram provided by the embodiment of the present application is shown in Figure 2 The pixel circuit includes a driving transistor Tm, a storage capacitor Cst and a compensation module 10. The gate of the driving transistor Tm is connected to a first node N1, and the driving transistor Tm is used to generate a driving current in the light-emitting stage of the pixel circuit; the first plate of the storage capacitor Cst is connected to the first node N1, and the second plate of the storage capacitor Cst is connected to a second node N2, and the storage capacitor Cst is used to store a data voltage written to the gate of the driving transistor Tm. The output end of the compensation module 10 is connected to the second node N2, one input end of the compensation module 10 receives a first power supply voltage Vd, and the compensation module 10 is used to compensate the deviation of the first power supply voltage Vd affecting the driving current.

[0034] In the embodiment of the present application, the pixel circuit is coupled with a first electrode of a light-emitting device 30, the power supply receiving end in the pixel circuit receives the first power supply voltage Vd, and the second electrode of the light-emitting device 30 receives a second power supply voltage Ve. Optionally, the first electrode is the anode of the light-emitting device 30, the second electrode is the cathode of the light-emitting device 30, the first power supply voltage Vd is the positive power supply voltage, the second power supply voltage Ve is the negative power supply voltage, and the first power supply voltage Vd is greater than the second power supply voltage Ve. In combination with Figure 1 As can be known from the related art, when the pixel circuit is applied to a display panel, the first power supply voltage Vd will generate a voltage drop when transmitted on a signal line, and the voltage drop will cause a difference between the actual voltage value received by the pixel circuit and the voltage value provided by the driving chip (i.e., the deviation of the first power supply voltage Vd). The pixel circuit has different positions in the display panel, and the transmission distance of the first power supply voltage Vd is different, so the deviation is different. The voltage value deviation of the first power supply voltage Vd will affect the size of the driving current. In the prior art, the plate of the storage capacitor in the pixel circuit is directly connected to the power supply voltage, while in the present application, the second plate of the storage capacitor Cst is connected to the first power supply voltage Vd through the compensation module 10, and the compensation module 10 is used to make the driving current no longer affected by the deviation of the first power supply voltage Vd, so that the deviation of the first power supply voltage Vd does not cause display non-uniformity.

[0035] The inventors consider that the second plate of the storage capacitor Cst is connected to the second node N2, and after the compensation module 10 is connected at the position of the second node N2, the jump of the voltage signal of the control end of the compensation module 10 can affect the voltage of the second node N2, and after the storage capacitor Cst stores the data voltage, the voltage change of the second node N2 can cause the voltage change of the first node N1, that is, the gate potential of the driving transistor Tm is affected. Thus, the gate-source voltage difference of the driving transistor Tm is affected, and the size of the driving current is affected, the pixel circuit cannot provide accurate driving current to the light emitting device 30, and the display uniformity is affected. Therefore, the inventors conduct simulation tests to study the voltage change of the first node N1 in the working of the pixel circuit, and in the simulation test, Vdata=0 volt.

[0036] In an embodiment, for example, the first input end of the compensation module 10 receives the first power voltage Vd, the second input end receives the compensation voltage Vp, the first control end receives the first control signal K1, and the second control end receives the second control signal K2. The first control signal K1 is used to control the writing of the first power voltage Vd to the second node N2, and the second control signal K2 is used to control the writing of the compensation voltage Vp to the second node N2. Figure 3 For Figure 2 A timing diagram of the pixel circuit. Figure 4 For Figure 2 A simulation test result diagram of the working of the embodiment pixel circuit.

[0037] As Figure 3 shown, for example, a low-level signal is used as an enabling signal in the reset phase t1, the data writing phase t2, and the light emitting phase t3 in the working period of the pixel circuit. In the reset phase t1: the scan signal Scan2 controls the gate reset transistor T1 to be turned on, the reset signal Vref is written to the first node N1, and the second control signal K2 controls the compensation module 10 to write the compensation voltage Vp to the second node N2. In the data writing phase t2: the scan signal Scan1 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned on, the data voltage Vdata is written to the first node N1, and the threshold voltage of the driving transistor Tm is self-checked and compensated, and at the same time, the compensation module 10 maintains writing the compensation voltage Vp to the second node N2. In the light emitting phase t3: the first control signal K1 controls the compensation module 10 to write the first power voltage Vd to the second node N2, the light emitting control signal Emit controls the first light emitting control transistor T4 and the second light emitting control transistor T5 to be turned on, the driving transistor Tm is turned on, the driving current is generated, and the driving current is provided to the light emitting device 30.

[0038] By Figure 3It can be seen that the working cycle of the pixel circuit also includes a fourth time period t4. During this fourth time period: both the first control signal K1 and the second control signal K2 are disabled, the compensation module 10 is not working, and no voltage is written to the second node N2 during this stage; the second node N2 is in a floating state. During this time period, the potential of the second node N2 is easily affected by signal transitions at the control terminal of the compensation module 10. For example, when the second control signal K2 transitions from low to high, it will pull the potential of the second node N2 high. Due to the coupling effect of the storage capacitor Cst, this will also pull the potential of the first node N1 high.

[0039] Combination Figure 4 Let's take a look. Figure 4 The first curve in the diagram is a schematic diagram of the voltage change of the first node N1 in the working cycle of the pixel circuit. The unit of the vertical axis is volts (V). Figure 4 The second curve in the diagram is the timing diagram of the second control signal K2, and the unit of the vertical axis is volts. Figure 4 The third curve in the middle represents the drive current I. d The time series plot, with the vertical axis in μA. (From...) Figure 4 As shown in position ⑥ of the voltage change curve of the first node N1, it can be seen that the rise of the second control signal K2 from low to high (i.e., the rising edge) causes the potential of the first node N1 to be pulled up. When the driving transistor Tm is a P-type transistor, the increased potential of the first node N1 reduces the driving current provided by the pixel circuit. Therefore, the signal transition at the control terminal of the compensation module 10 affects the potential of the first node N1, verifying the inventor's analysis. That is, during the fourth time period, the second node N2 is in a floating state. During this period, the potential of the second node N2 is easily affected by the signal transition at the control terminal of the compensation module 10. The voltage change of the second node N2 then leads to a voltage change in the first node N1, affecting the gate potential of the driving transistor Tm, which in turn affects the gate-source voltage difference of the driving transistor Tm, thus affecting the driving current. Applying pixel circuits to a display panel will affect display uniformity.

[0040] In addition, for Figure 4 The voltage changes at the first node N1 are explained below. ① The voltage increase at position 1 is influenced by the voltage jump of the Emit control signal. ② The voltage decrease at position 1 is influenced by the falling edge of the second control signal K2. ③ The voltage decrease at position 1 corresponds to the initial moment of the reset phase t1, during which a low-voltage reset signal Vref is written to the first node N1. ④ The voltage increase at position 1 corresponds to the data writing phase t2. The voltage of the first node N1 rises rapidly at the beginning of the data writing phase t2, and then rises slowly thereafter. ⑤ The voltage increase at position 1 is influenced by the rising edge of the Scan signal Scan1. ⑦ The voltage decrease at position 1 is influenced by the falling edge of the Emit control signal.

[0041] The inventors know from the analysis of the simulation test above that the signal jump at the control end of the compensation module 10 will cause the gate voltage of the drive transistor Tm to fluctuate. In order to avoid the fluctuation of the gate potential of the drive transistor Tm, the voltage fluctuation of the second node N2 is controlled by the voltage control module before the light-emitting stage in the embodiment of the present application, and the voltage fluctuation of the second node N2 is controlled by the characteristic that the voltage between the two plates of the storage capacitor Cst cannot be abruptly changed, so that the voltage fluctuation of the first node N1 is controlled, the drive current generated in the light-emitting stage is prevented from being affected by the voltage fluctuation of the first node N1, and the display uniformity is improved and the display effect is ensured.

[0042] Figure 5 A pixel circuit schematic diagram provided by the embodiment of the present application is shown in FIG. 1. Figure 5 As shown in FIG. 1, the pixel circuit includes a drive transistor Tm, a storage capacitor Cst, a compensation module 10, and a voltage control module 20. The gate of the drive transistor Tm is connected to a first node N1, and the drive transistor Tm is used to generate a drive current in the light-emitting stage of the pixel circuit. The first plate of the storage capacitor Cst is connected to the first node N1, and the second plate of the storage capacitor Cst is connected to a second node N2. The storage capacitor Cst is used to store a data voltage written to the gate of the drive transistor Tm. The output end of the compensation module 10 is connected to the second node N2, one input end of the compensation module 10 receives a first power supply voltage Vd, and the compensation module 10 is used to compensate for the deviation of the first power supply voltage Vd affecting the drive current. The voltage control module 20 is connected to the second node N2, and the voltage control module 20 is used to control the voltage fluctuation of the second node N2 before the light-emitting stage.

[0043] The pixel circuit provided by the embodiment of the present application includes the drive transistor Tm and the storage capacitor Cst. The gate of the drive transistor Tm and the first plate of the storage capacitor Cst are connected to the first node N1, and the second plate of the storage capacitor Cst is connected to the second node N2. The pixel circuit further includes the compensation module 10 and the voltage control module 20 connected to the second node N2, and the storage capacitor Cst is connected to the first power supply voltage Vd through the compensation module 10. The deviation of the first power supply voltage Vd affecting the drive current is compensated by the compensation module 10, so that the drive current is no longer affected by the deviation of the first power supply voltage Vd, and the deviation of the first power supply voltage Vd is prevented from causing display unevenness. In addition, the voltage fluctuation of the second node N2 is controlled by the voltage control module 20 before the light-emitting stage. Since the voltage between the two plates of the storage capacitor Cst cannot be abruptly changed, the voltage fluctuation of the second node N2 is controlled, so that the voltage fluctuation of the first node N1 is controlled, and the size of the drive current is prevented from being affected by the voltage fluctuation of the first node N1, thereby improving the display uniformity and ensuring the display effect.

[0044] As shown in Figure 2 and Figure 5 The pixel circuit further comprises a gate reset transistor T1, a data write transistor T2, a threshold compensation transistor T3, a first light emitting control transistor T4 and a second light emitting control transistor T5. The first electrode of the driving transistor Tm is connected to the third node N3, the second electrode of the driving transistor Tm is connected to the fourth node N4, the data write transistor T2 is connected to the third node N3, and the threshold compensation transistor T3 is connected in series between the fourth node N4 and the first node N1. The working period of the pixel circuit comprises at least a reset stage, a data write stage and a light emitting stage. In the reset stage, the gate reset transistor T1 is turned on under the control of the scanning signal Scan2, and the first node N1 is reset by using the reset signal Vref, that is, the gate of the driving transistor Tm is reset in this stage. In the data write stage, the data write transistor T2 and the threshold compensation transistor T3 are turned on under the control of the scanning signal Scan1, and the data voltage Vdata is written to the first node N1, and the threshold voltage of the driving transistor Tm is self-checked and compensated. In the light emitting stage, the first light emitting control transistor T4 and the second light emitting control transistor T5 are turned on under the control of the light emitting control signal Emit, and in this stage the driving transistor Tm generates a driving current, and the driving current is provided to the light emitting device 30 to control the light emitting thereof.

[0045] The first electrode of the driving transistor Tm can be a source electrode, and the second electrode of the driving transistor Tm can be a drain electrode.

[0046] The transistors in the pixel circuit are all p-type transistors, and in other embodiments, the transistors in the pixel circuit are all n-type transistors.

[0047] In other embodiments, the driving transistor Tm is a p-type transistor, the threshold compensation transistor T3 and the gate reset transistor T1 are n-type transistors, and such arrangement can reduce the leakage current to the first node N1, and ensure the stability of the potential of the first node N1. When applied in a low-frequency display mode, the problem of flicker can be improved.

[0048] In other embodiments, the pixel circuit further comprises an electrode reset transistor, and the electrode reset transistor is connected to one electrode of the light emitting device 30, for example, the electrode reset transistor is connected to the electrode of the light emitting device 30 connected to the second light emitting control transistor T5, and the electrode reset transistor is used to reset the electrode of the light emitting device 30.

[0049] The voltage control module 20 is used to control the voltage fluctuation of the second node N2 after the data writing stage. The storage capacitor Cst stores the data voltage during the data writing stage and maintains the potential stability of the first node N1 during the light-emitting stage. This ensures that the driving transistor Tm continuously generates a stable driving current during the light-emitting stage. Therefore, the data writing stage and the potential stability of the second node N2 after the data writing stage are key factors affecting the light emission of the light-emitting device 30. In this embodiment, the voltage control module 20 operates after the data writing stage and does not affect the operation of the data writing stage, ensuring that the accurate data voltage is stored in the storage capacitor Cst. After completing the data writing and storage process, the voltage control module 20 controls the voltage fluctuation of the second node N2. Since the voltage between the two plates of the storage capacitor Cst cannot change abruptly, controlling the voltage fluctuation of the second node N2 also ensures that the voltage fluctuation of the first node N1 is controlled, thus preventing the voltage fluctuation of the first node N1 from affecting the magnitude of the driving current, thereby improving display uniformity and ensuring display effect.

[0050] In some implementations... Figure 6 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 6 As shown, the compensation module 10 includes a first input terminal and a second input terminal. The first input terminal receives a first power supply voltage Vd, and the second input terminal receives a compensation voltage Vp. The compensation module 10 also includes a first control terminal and a second control terminal. The first control terminal receives a first control signal K1, and the compensation module 10 writes the first power supply voltage Vd into the second node N2 under the control of the first control signal K1. The second control terminal receives a second control signal K2, and the compensation module 10 writes the compensation voltage Vp into the second node N2 under the control of the second control signal K2. During the working cycle of the pixel circuit, the enabling periods of the first control signal K1 and the second control signal K2 do not overlap. In this embodiment, the two input terminals of the compensation module 10 respectively input the first power supply voltage Vd and the compensation voltage Vp, and the first control signal K1 and the second control signal K2 control the input of the two voltages respectively.

[0051] Figure 3 The schematic timing diagram can be applied to Figure 6 The pixel circuit provided in the embodiment, combined with Figure 3 As shown in the schematic timing diagram, the enable periods of the first control signal K1 and the second control signal K2 do not overlap. The enable period of the first control signal K1 basically occurs during the light emission stage t3, while the enable period of the second control signal K2 occurs before the light emission stage t3. In the pixel circuit's operating cycle, the end time of the enable signal in the second control signal K2 (e.g., ...) Figure 3the rising edge of the K2 signal is earlier than the start time of the enable signal in the K1 signal (such as Figure 3 the falling edge of the K1 signal in the K2 signal), ensuring that the process of writing the compensation voltage Vp to the second node N2 ends before the first power voltage Vd is written to the second node N2. In this embodiment, the compensation module 10 is used to write the compensation voltage Vp and the first power voltage Vd in different stages of the operation of the pixel circuit, thereby achieving compensation for the deviation of the first power voltage Vd affecting the driving current.

[0052] As shown in Figure 3 , the working period of the pixel circuit also includes a fourth period t4. The fourth period t4 is located after the data writing stage t2 and before the light emitting stage t3. In the fourth period t4, the first control signal K1 and the second control signal K2 are both non-enabled signals, the compensation module 10 does not work, and the second node N2 is in a floating state. In this period, the potential of the second node N2 is easily affected by the signal transition of the control end of the compensation module 10, and the transition of the second control signal K2 from low to high will pull up the level of the second node N2. However, the storage capacitor Cst is connected between the second node N2 and the first node N1, and the pull-up of the level of the second node N2 will cause the level of the first node N1 to also be raised, thereby causing the driving current to decrease in the light emitting stage t3, resulting in a decrease in the brightness of the light emitting element. In the embodiment of the present application, the voltage control module 20 is provided, which can control the voltage fluctuation of the second node N2 before the light emitting stage t3, prevent the level of the second node N2 from being affected too much by the transition of the second control signal K2, reduce the voltage fluctuation of the second node N2, and thus avoid the potential of the first node N1 from being raised too much, thereby improving the display uniformity. In addition, when the potential of the first node N1 is raised, the driving current will decrease, and the decrease in the driving current will affect the light emitting efficiency of the light emitting device. The embodiment of the present application indirectly controls the raising of the potential of the first node N1 by using the voltage control module 20, thereby ensuring that the light emitting efficiency is not affected.

[0053] In some embodiments, Figure 7 , another schematic diagram of a pixel circuit provided by the embodiment of the present application is shown in Figure 7 , the compensation module 10 includes a first transistor T6 and a second transistor T7; the gate of the first transistor T6 receives the first control signal K1, the first electrode of the first transistor T6 receives the first power voltage Vd, and the second electrode of the first transistor T6 is connected to the second node N2; the gate of the second transistor T7 receives the second control signal K2, the first electrode of the second transistor T7 receives the compensation voltage Vp, and the second electrode of the second transistor T7 is connected to the second node N2.

[0054] The working process of the pixel circuit in Figure 3 is understood in combination with the timing diagram shown in Figure 7 .

[0055] During the reset phase t1: the scan signal Scan2 controls the gate reset transistor T1 to turn on and writes the reset signal Vref into the first node N1, where the potential of the first node N1 is Vref; the second control signal K2 controls the second transistor T7 to turn on and writes the compensation voltage Vp into the second node N2, where the potential of the second node N2 is Vp.

[0056] During the data writing phase t2: the scan signal Scan1 controls the data writing transistor T2 and the threshold compensation transistor T3 to turn on, writing the data voltage Vdata to the first node N1 and performing self-checking and compensation on the threshold voltage of the driving transistor Tm. Simultaneously, the second transistor T7 remains on during this phase. After the data writing is complete, the voltage at the first node N1 is Vdata + Vth, where Vth is the threshold voltage of the driving transistor Tm, and the voltage at the second node N2 is the compensation voltage Vp.

[0057] During the fifth time period t5: the second control signal K2 remains at a low level, and the second transistor T7 remains on. At the end of this time period, the second control signal K2 transitions from low to high level to control the second transistor T7 to turn off, thus ending the process of writing the compensation voltage Vp to the second node N2.

[0058] In the fourth time period t4: the second control signal K2 is high and the first control signal K1 is also high. During this period, no signal is written to the second node N2, and the second node N2 is in a floating state. Combined with... Figure 4 As can be seen from the description of the embodiment, the potential of the second node N2 is easily affected by the rising edge of the second control signal K2. During this stage, the voltage control module 20 controls the voltage fluctuation of the second node N2 to prevent the level of the second node N2 from being excessively affected by the jump of the second control signal K2. Reducing the voltage fluctuation of the second node N2 also prevents the potential of the first node N1 from rising too much.

[0059] During the light-emitting stage t3: the first control signal K1 controls the first transistor T6 to turn on and write the first power supply voltage Vd to the second node N2. After setting the voltage control module 20, considering that the potential of the second node N2 is not affected by the signal transitions of the second control signal K2 and the first control signal K1, at the beginning of the light-emitting stage t3, the second node N2 is at the ideal potential written when the second transistor T7 is turned on, i.e., the compensation voltage Vp. Then, after the first transistor T6 turns on, the potential of the second node N2 jumps from the compensation voltage Vp to the first power supply voltage Vd, and the potential change of the second node N2 is ΔV. N2Vd-Vp. Meanwhile, due to the coupling effect of the storage capacitor Cst, the voltage of the first node N1 changes with the potential of the second node N2, and the voltage of the first node N1 jumps to Vdata+Vth+ΔV N2 , that is, Vd-Vp+Vdata+Vth. In this stage, the light emitting control signal Emit controls the first light emitting control transistor T4 and the second light emitting control transistor T5 to be turned on, and the driving transistor Tm is turned on to generate a driving current and provide the driving current to the light emitting device 30.

[0060] The calculation formula of the driving current is Id=K*(Vgs-│Vth│) 2 . Vgs is the voltage difference between the gate and the source of the driving transistor Tm. In the light emitting stage t3, Vgs is the voltage difference between the gate and the source of the driving transistor Tm, that is, Vgs is the voltage difference between the first node N1 and the third node N3, the voltage of the first node N1 is Vd-Vp+Vdata+Vth, and the voltage of the third node N3 is the first power supply voltage Vd provided after the first light emitting control transistor T4 is turned on, so Vgs=Vdata-Vp+Vth. Substituting Vgs into the calculation formula of the driving current obtains Id=K*(Vdata-Vp) 2 .

[0061] Therefore, the driving current Id is only related to the data voltage Vdata and the compensation voltage Vp, and is independent of the threshold voltage Vth of the driving transistor Tm and the first power supply voltage Vd. Thus, the deviation of the first power supply voltage Vd affecting the driving current is compensated by the compensation module 10, so that the driving current is no longer affected by the deviation of the first power supply voltage Vd, and the deviation of the first power supply voltage Vd is avoided to cause display unevenness.

[0062] In combination Figure 7 and Figure 3In the working period of the pixel circuit, the gate of the data writing transistor T2 receives a scan signal Scan1, which can also be referred to as a third control signal K3, and the third control signal K3 provides an enable signal to control the data writing transistor T2 to be turned on. In the working period of the pixel circuit, the end time of the enable signal in the third control signal K3 is earlier than the end time of the enable signal in the second control signal K2. That is, after the data writing process is completed, the process of writing the compensation voltage Vp to the second node N2 by the second transistor T7 is ended. After the data writing process is completed, the voltage of the first node N1 is Vdata+Vth. After the process of writing the compensation voltage Vp to the second node N2 by the second transistor T7 is ended, the potential of the second node N2 is Vp. After the data writing is completed, a certain voltage difference is maintained between the two plates of the storage capacitor Cst. After the process of writing the compensation voltage Vp to the second node N2 by the second transistor T7 is ended, the voltage signal of the second control signal K2 jumps to pull up the level of the second node N2, and the coupling effect of the storage capacitor Cst also causes the potential of the first node N1 to change. The end time of the enable signal in the third control signal K3 is set to be earlier than the end time of the enable signal in the second control signal K2, so that the voltage difference between the two plates of the storage capacitor Cst is related to the compensation voltage Vp, and thus the influence of the first power supply voltage Vd on the driving current can be eliminated when the driving current is calculated in the light emitting stage, so that the size of the driving current is independent of the first power supply voltage Vd.

[0063] In the embodiment of the present application, the first control signal K1 controls the first transistor T6 to be turned on in the light emitting stage t3 and controls the first transistor T6 to be turned off in other stages. The first control signal K1 can be an additional signal or can reuse the original control signal in the working of the pixel circuit.

[0064] In some embodiments, Figure 8 For Figure 7 A timing diagram of the pixel circuit provided by the embodiment is as follows: Figure 8As shown, the light emitting control signal Emit is multiplexed as the first control signal K1, that is, the light emitting control signal Emit is received by the first control terminal of the compensation module 10 in the pixel circuit, that is, the control terminal of the first transistor T6 receives the light emitting control signal Emit. The first transistor T6 is turned on and off at the same time as the first light emitting control transistor T4 and the second light emitting control transistor T5 in the working period of the pixel circuit. In this way, the first transistor T6 can be ensured to write the first power supply voltage Vd to the second node N2 in the light emitting stage t3, so as to realize the compensation of the deviation of the first power supply voltage Vd by the cooperation of the first transistor T6 and the second transistor T7. Multiplexing the light emitting control signal Emit as the first control signal K1 can reduce the number of control signals required by the pixel circuit, and can save the number of wiring lines of the signal line in the display panel when applied in the display panel, thereby saving the wiring space of the display panel.

[0065] In some other embodiments, Figure 9 Another schematic diagram of the pixel circuit provided by the embodiments of the present application is shown in FIG. 6. Figure 9 As shown, the first electrode of the first light emitting control transistor T4 receives the first power supply voltage Vd; the compensation module 10 includes the first transistor T6 and the second transistor T7; the gate electrode of the first transistor T6 receives the light emitting control signal Emit, the first electrode of the first transistor T6 is connected with the second electrode of the first light emitting control transistor T4, and the second electrode of the first transistor T6 is connected with the second node N2; the gate electrode of the second transistor T7 receives the second control signal K2, the first electrode of the second transistor T7 receives the compensation voltage Vp, and the second electrode of the second transistor T7 is connected with the second node N2. The working timing of the pixel circuit in this embodiment can be understood in combination with the timing diagram shown in FIG. 7. Figure 8 Figure 9 Figure 7 The difference between the embodiments is only that the first transistor T6 in the compensation module 10 receives the first power supply voltage Vd in different ways. Figure 7 In the embodiment, the first electrode of the first transistor T6 directly receives the first power supply voltage Vd, Figure 9 In the embodiment, the first electrode of the first transistor T6 receives the first power supply voltage Vd after the first light emitting control transistor T4 is turned on. In the Figure 9 In the embodiment, in the light emitting stage t3: the light emitting control signal Emit controls the first light emitting control transistor T4 and the first transistor T6 to be turned on at the same time, the first power supply voltage Vd is transmitted to the first electrode of the first transistor T6 via the first light emitting control transistor T4, and then the first power supply voltage Vd is written to the second node N2 via the first transistor T6, so that the potential of the second node N2 jumps from the compensation voltage Vp to the first power supply voltage Vd, and then the voltage of the first node N1 jumps to Vd-Vp+Vdata+Vth through the coupling effect of the storage capacitor Cst.

[0066] ​​In this embodiment of the invention, the voltage value of the first power supply voltage Vd received at the first input terminal of the compensation module 10 is V1, and the voltage value of the compensation voltage Vp received at the second input terminal is V2, where V2 > V1. The compensation voltage Vp can be considered as an ideal power supply voltage, or a power supply voltage provided by the driver chip without voltage drop loss. Wherein, V2 = V1 + ΔV, and ΔV is the voltage drop generated when transmitting the first power supply voltage Vd on the signal line. Setting the compensation voltage Vp to be the power supply voltage provided by the driver chip can reduce the difference between the compensation voltage Vp and the first power supply voltage Vd connected to the pixel circuit, that is, reduce the voltage jump of the second node N2, and further reduce the voltage jump of the first node N1, thus reducing the impact on the driving current value.

[0067] In other embodiments, the compensation voltage Vp is an ideal voltage. The compensation voltage Vp received by the compensation module 10 in each pixel circuit of the display panel is equal. The compensation voltage Vp can be greater than the power supply voltage output by the driver chip, or the compensation voltage Vp can be less than the power supply voltage output by the driver chip.

[0068] By applying pixel circuits to display panels, dedicated lines can be used in the display panel to provide compensation voltage Vp, ensuring that there is no voltage drop during the transmission of compensation voltage Vp. The compensation voltage Vp received by the pixel circuits at all locations in the display panel is the same, thereby ensuring that the driving current generated by the pixel circuits is not affected by voltage drop and improving the display unevenness problem caused by voltage drop.

[0069] In some implementations... Figure 10 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 10 As shown, the voltage control module 20 includes a voltage limiting unit 21. The first terminal of the voltage limiting unit 21 receives a first voltage V_1, and the second terminal of the voltage limiting unit 21 is connected to the second node N2. The voltage limiting unit 21 is used to conduct when the voltage at the second node N2 is greater than the first voltage V_1, thereby pulling down the potential of the second node N2. The voltage limiting unit 21 serves to limit the potential of the second node N2, combined with… Figure 8As shown in the schematic timing diagram, the light emitting control signal Emit is multiplexed as the first control signal K1. In the fourth time period t4, the second node N2 is in a floating state, and the process of the second control signal K2 jumping from low to high will pull up the potential of the second node N2. When the potential of the second node N2 is pulled up to be higher than the first voltage V_1, the voltage limiting unit 21 pulls down the potential of the second node N2 again by using the first voltage V_1, thereby realizing the control of the fluctuation of the voltage of the second node N2, preventing the level of the second node N2 from being affected too much by the jump of the second control signal K2, reducing the voltage fluctuation of the second node N2, and thus avoiding the potential of the first node N1 from being pulled up too much. In this way, the voltage fluctuation of the first node N1 can be avoided to affect the size of the driving current, the display uniformity can be improved, the display effect can be ensured, and meanwhile, the driving current can be avoided to be reduced to affect the light emitting efficiency.

[0070] In some embodiments, as shown in Figure 10 The voltage limiting unit 21 includes a voltage limiting transistor T8, the gate of the voltage limiting transistor T8 is connected to the first pole of the voltage limiting transistor T8, the second pole of the voltage limiting transistor T8 is connected to the second node N2, and the first pole of the voltage limiting transistor T8 receives the first voltage V_1. By connecting the gate of the voltage limiting transistor T8 to the first pole, the voltage limiting transistor T8 is equivalent to a diode structure, and the diode has the performance of unidirectional conduction. When the voltage value of the second node N2 is greater than the voltage value of the first voltage V_1, the voltage limiting transistor T8 is turned on, and after being turned on, the second node N2 leaks to the first pole of the voltage limiting transistor T8, thereby being able to pull down the potential of the second node N2.

[0071] The present application is Figure 10 The working process of the pixel circuit in the embodiment is simulated and tested, and the voltage change of the first node N1 in the working process of the pixel circuit is studied. In the simulation test, Vdata=0 volt. Figure 11 For Figure 10 The simulation test result of the working process of the pixel circuit in the embodiment is shown in the schematic diagram. Figure 11 In the schematic diagram, the first curve is the timing diagram of the second control signal K2, and the unit of the vertical coordinate is volt. Figure 11 In the schematic diagram, the second curve is the timing diagram of the light emitting control signal Emit, and the unit of the vertical coordinate is volt. Figure 11 In the schematic diagram, the third curve is the voltage change diagram of the first node N1 in the working period of the pixel circuit, and the unit of the vertical coordinate is volt. Figure 11 In the schematic diagram, the fourth curve is the timing diagram of the driving current I d , and the unit of the vertical coordinate is μA. Figure 11 It is shown that the potential of the first node N1 is pulled up under the influence of the rising edge of the second control signal K2 at the position ⑥. Figure 11The fourth time period t4 is shown. It can be seen that the potential of the first node N1 decreases (see the position of the black arrow in ⑧). It can be verified that the second node N2 leaks to the first electrode of the voltage limiting transistor T8 after the voltage limiting transistor T8 is turned on, so that the potential of the second node N2 is pulled down.

[0072] In this embodiment, the voltage limiting transistor T8 is connected to the second node N2, and the voltage fluctuation of the second node N2 is controlled by the voltage limiting transistor T8, so that the voltage fluctuation of the second node N2 does not cause the voltage fluctuation of the first node N1 and affect the driving current, thereby improving the display uniformity and ensuring the display effect. In addition, when the first control signal K1 jumps from high level to low level, the potential of the second node N2 is pulled down. Due to the one-way conduction characteristic of the voltage limiting transistor T8, the voltage limiting transistor T8 does not generate a leakage current from the first electrode to the second node N2. The potential of the second node N2 is pulled down, which causes the potential of the first node N1 to be coupled and pulled down, thereby increasing the driving current and improving the luminous efficiency.

[0073] Optionally, the voltage limiting transistor T8 and the driving transistor Tm are of the same type, for example, the voltage limiting transistor T8 and the driving transistor Tm are both p-type transistors. In this way, when the pixel circuit is applied to a display panel, the manufacturing process of the display panel can be simplified.

[0074] In some embodiments, the voltage value of the first voltage V-1 is greater than the voltage value of the first power voltage Vd received by the first input end of the compensation module 10. In combination with the above description, the first voltage V-1 can be used to pull down the potential of the first node N1, thereby increasing the driving current and improving the luminous efficiency. Figure 3Based on the schematic timing diagram and related explanations, when the voltage of the second node N2 is pulled high due to the signal transition of the second control signal K2, the voltage of the second node N2 after being pulled high is greater than the first voltage V_1. The voltage limiting transistor T8 turns on, generating leakage current, which pulls the voltage of the second node N2 down, thereby controlling the voltage fluctuation of the first node N1. After the data writing phase t2 ends, the voltage of the first node N1 is Vdata + Vth, and the voltage of the second node N2 is the compensation voltage Vp. The compensation module 10 completes writing the compensation voltage Vp to the second node N2 after the data writing is finished. During the light-emitting phase t3, the first power supply voltage Vd is written to the second node N2, causing the voltage of the second node N2 to jump from the compensation voltage Vp to the first power supply voltage Vd. This, in turn, utilizes the coupling effect of the storage capacitor to cause a jump in the voltage of the first node N1, thus ensuring that the driving current generated during the light-emitting phase t3 is independent of the first power supply voltage Vd. In other words, during the light-emitting phase t3, the voltage of the second node N2 needs to be maintained at the first power supply voltage Vd. In this embodiment of the invention, the voltage value of the first voltage V-1 is set to be greater than the voltage value of the first power supply voltage Vd received by the first input terminal of the compensation module 10. Then, in the light-emitting stage t3, the voltage of the second node N2 is less than the first voltage V-1, and the voltage limiting transistor T8 is in the off state. This ensures that the voltage of the second node N2 is not affected by the voltage control module 20 in the light-emitting stage t3, thereby ensuring the potential stability of the second node N2, and further ensuring the potential stability of the first node N1, and ensuring that the pixel circuit provides a stable driving current.

[0075] In some implementations... Figure 12 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 12 As shown, the first terminal of the voltage-limiting transistor T8 is electrically connected to the second input terminal of the compensation module 10, that is, the first terminal of the voltage-limiting transistor T8 is electrically connected to the first terminal of the second transistor T7, and the compensation voltage Vp is multiplexed to the first voltage V_1. With this configuration, when the potential of the second node N2 is coupled high before the light-emitting stage t3, the voltage-limiting transistor T8 can be turned on to pull the potential of the second node N2 low. Furthermore, the first terminal of the voltage-limiting transistor T8 receives the compensation voltage Vp, and the value of the compensation voltage Vp is greater than the first power supply voltage Vd. This ensures that the voltage-limiting transistor T8 is in the off state during the light-emitting stage t3, and the voltage of the second node N2 is limited to the first power supply voltage Vd, ensuring the potential stability of the second node N2, thereby ensuring the potential stability of the first node N1 and providing a stable driving current for the pixel circuit. Simultaneously, it reduces the number of voltage signals required by the pixel circuit, saving the number of signal lines in the display panel and thus saving wiring space.

[0076] In other implementations, Figure 13Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 13 As shown, the voltage control module 20 includes a voltage regulator unit 22. The first terminal of the voltage regulator unit 22 receives a second voltage V_2, and the second terminal of the voltage regulator unit 22 is connected to the second node N2. The voltage regulator unit 22 is used to maintain the voltage between its first terminal and the second terminal and to adjust the voltage of the second node N2 when the voltage of the second node N2 fluctuates. In this embodiment, the voltage regulator unit 22 is connected to the second node N2. The voltage regulator unit 22 can maintain a stable voltage difference between its first terminal and the second terminal. Therefore, when the voltage of the second node N2 fluctuates due to the signal jump of the second control signal K2 before the light emission stage t3, the voltage regulator unit 22 can control the voltage fluctuation of the second node N2, thereby also controlling the voltage fluctuation of the first node N1. This avoids the voltage fluctuation of the first node N1 affecting the magnitude of the driving current, thereby improving the display uniformity and ensuring the display effect.

[0077] like Figure 13 As shown, the voltage regulator unit 22 includes a voltage regulator capacitor C2. The first plate of the voltage regulator capacitor C2 receives the second voltage V_2, and the second plate of the voltage regulator capacitor C2 is connected to the second node N2. The voltage between the first and second plates of the voltage regulator capacitor C2 cannot change abruptly. Therefore, after the second transistor T7 turns on and writes the compensation voltage Vp to the second node N2, the voltage difference between the two plates of the voltage regulator capacitor C2 remains constant. When the voltage of the second node N2 fluctuates due to the signal transition of the second control signal K2, the coupling effect of the voltage regulator capacitor C2 can pull back the voltage of the second node N2, thereby controlling the voltage fluctuation of the second node N2 before the light-emitting stage.

[0078] This application is for Figure 13 The operation of the pixel circuit in the embodiment was simulated. The voltage change of the first node N1 during the operation of the pixel circuit was studied. In the simulation, Vdata = 0 volts. Figure 14 for Figure 13 A schematic diagram of the simulation test results of the pixel circuit operation in the embodiment. Figure 14 The first curve in the diagram is the timing diagram of the second control signal K2, and the unit of the vertical axis is volts. Figure 14 The second curve in the diagram is the timing graph of the emission control signal Emit, with the vertical axis in volts. Figure 14 The third curve in the diagram is a schematic diagram of the voltage change of the first node N1 in the working cycle of the pixel circuit. The unit of the vertical axis is volts. Figure 14 The fourth curve in the middle represents the driving current I. d The time series plot is shown, with the vertical axis in μA. Figure 14 This shows that at position ⑥, the potential of the first node N1 is pulled high due to the rising edge of the second control signal K2, while in contrast... Figure 4It can be seen that the potential of the first node N1 is pulled up to a smaller extent in the fourth period t4. It can be verified that the coupling effect of the voltage stabilizing capacitor C2 can inhibit the voltage of the second node N2 from being pulled up to a high level by the rising edge of the second control signal K2, and further reduce the jump of the potential of the first node N1. In addition, the potential of the second node N2 will be pulled down by the falling edge of the light emitting control signal Emit in the light emitting stage t3, but the coupling effect of the voltage stabilizing capacitor C2 can inhibit the degree of being pulled down by the falling edge of the light emitting control signal Emit, that is, inhibit the feedthrough of the light emitting control signal Emit. It can be seen that the voltage stabilizing capacitor C2 can inhibit the potential of the second node N2 from being pulled up by the rising edge of the second control signal K2 and being pulled down by the falling edge of the light emitting control signal Emit, so as to control the voltage fluctuation of the first node N1, avoid the voltage fluctuation of the first node N1 affecting the size of the driving current, and thus improve the display uniformity and ensure the display effect.

[0079] In some embodiments, the first end of the voltage stabilizing unit 22 is electrically connected with the second input end of the compensation module 10, that is, the first end of the voltage stabilizing unit 22 is electrically connected with the first electrode of the second transistor T7, and then the compensation voltage Vp is multiplexed as the second voltage V_2. In the embodiment of the present application, the voltage value of the compensation voltage Vp is greater than the voltage value of the first power supply voltage Vd, and the compensation voltage Vp can be considered as an ideal power supply voltage, or a power supply voltage without voltage drop loss provided by the driving chip. The compensation voltage Vp does not have voltage drop during signal transmission, for example, there is no current in the signal line providing the compensation voltage Vp, and in application, it can ensure that the voltage values of the compensation voltage Vp received by the pixel circuits at different positions in the display panel are the same. Multiplexing the compensation voltage Vp as the second voltage V_2 can ensure that the voltage fluctuation control of the second node N2 in each pixel circuit is the same.

[0080] The second voltage V_2 can be multiplexed with other constant voltage signals required in the operation of the pixel circuit. In other embodiments, the reset signal Vref is multiplexed as the second voltage V_2.

[0081] Based on the same inventive concept, the embodiment of the present application also provides a display panel, Figure 15 The display panel provided by the embodiment of the present application is shown in the following schematic diagram: Figure 15 As shown in the figure, the display panel 100 includes the pixel circuit 01 provided by any embodiment of the present application, and the display panel includes a plurality of pixel circuits 01. The specific structure of the pixel circuit 01 has been described in the above pixel circuit related embodiments, and will not be repeated here. The display panel further includes a light emitting device, and the light emitting device is coupled with the pixel circuit 01. The light emitting device can be an organic light emitting diode or an inorganic light emitting diode.

[0082] Figure 15The pixel circuit 01 is only simplified and schematized, and only part of the structure in the pixel circuit 01 is shown. Figure 15 As shown in the figure, the display panel includes a power line 02 and a compensation signal line 03, the power line 02 provides a first power voltage Vd, and the compensation signal line 03 provides a compensation voltage Vp; the pixel circuit 01 includes a first light-emitting control transistor T4, the first light-emitting control transistor T4 in the plurality of pixel circuits 01 is connected to the power line 02; the compensation module 10 includes a second transistor T7, the second transistor T7 in the plurality of pixel circuits 01 is connected to the compensation signal line 03. In the display panel 100, the plurality of pixel circuits 01 are arranged into a pixel circuit row in a first direction x, and the plurality of pixel circuits 01 are arranged into a pixel circuit column in a second direction y. It can be seen that the first light-emitting control transistor T4 of the plurality of pixel circuits 01 in one pixel circuit column is connected to one power line 02, and the second transistor T7 of the plurality of pixel circuits 01 in one pixel circuit column is connected to one compensation signal line 03.

[0083] Figure 15 In the figure, the display panel further includes a second control line 04 and a light-emitting control line 05, the second control line 04 provides a second control signal K2, and the gate of the second transistor T7 in the plurality of pixel circuits 01 is connected to the second control line 04. The light-emitting control line 05 provides a light-emitting control signal Emit, and the light-emitting control signal Emit is multiplexed as the first control signal K1, and the gate of the first transistor T1 and the gate of the first light-emitting control transistor T4 are both connected to the light-emitting control line 05.

[0084] Figure 15 In the figure, the first pole of the first transistor T6 in the compensation module 10 is electrically connected to the power line 02, and the first end of the compensation module 10 receives the first power voltage Vd. In another embodiment, the first pole of the first transistor T6 in the compensation module 10 is electrically connected to the first light-emitting control transistor T4, and after the first light-emitting control transistor T4 is turned on, the first end of the compensation module 10 receives the first power voltage Vd.

[0085] Based on the same inventive concept, the embodiment of the present application also provides a display device, Figure 16 The display device provided by the embodiment of the present application is shown in the figure. Figure 16 As shown in the figure, the display device includes the display panel 100 provided by any embodiment of the present application. The display device provided by the embodiment of the present application can be a mobile phone, a tablet computer, a computer, a television, a smart wearable device, or the like. The display device can also be a transparent display device.

[0086] The above description is only a preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel circuit, characterized by comprising: The pixel circuit comprises: a driving transistor, a gate of the driving transistor being connected to a first node, the driving transistor being used for generating a driving current in a light-emitting phase in which the pixel circuit works; a storage capacitor, a first plate of the storage capacitor being connected to the first node, a second plate of the storage capacitor being connected to a second node, the storage capacitor being used for storing a data voltage written into the gate of the driving transistor; a compensation module, an output end of the compensation module being connected to the second node, one input end of the compensation module receiving a first power supply voltage, the compensation module being used for compensating for a deviation of the first power supply voltage affecting the driving current; the compensation module comprises a first input end and a second input end, the first input end receiving the first power supply voltage, the second input end receiving a compensation voltage; the compensation module comprises a first control end and a second control end, the first control end receiving a first control signal, the compensation module writing the first power supply voltage into the second node under control of the first control signal; the second control end receiving a second control signal, the compensation module writing the compensation voltage into the second node under control of the second control signal; an enabling period of the first control signal and an enabling period of the second control signal do not coincide in a working period of the pixel circuit; a pressure control module, the pressure control module being connected to the second node, the pressure control module being used for controlling fluctuation of a voltage of the second node before the light-emitting phase; the pressure control module comprises a voltage stabilizing unit, a first end of the voltage stabilizing unit receiving a second voltage, a second end of the voltage stabilizing unit being connected to the second node, the voltage stabilizing unit being used for maintaining a voltage between the first end and the second end thereof and adjusting the voltage of the second node when the voltage of the second node fluctuates.

2. The pixel circuit according to claim 1, wherein: the pixel circuit comprises a data writing transistor and a threshold compensation transistor, a first pole of the driving transistor being connected to a third node, a second pole of the driving transistor being connected to a fourth node, the data writing transistor being connected to the third node, the threshold compensation transistor being connected in series between the fourth node and the first node; a working period of the pixel circuit comprises a data writing phase, the data writing transistor and the threshold compensation transistor being used for being turned on in the data writing phase, writing a data voltage into the first node and compensating for a threshold voltage of the driving transistor; wherein the pressure control module is used for controlling fluctuation of the voltage of the second node after the data writing phase.

3. The pixel circuit according to claim 1, wherein: the compensation module comprises a first transistor and a second transistor; a gate of the first transistor receiving the first control signal, a first pole of the first transistor receiving the first power supply voltage, a second pole of the first transistor being connected to the second node. A gate of the second transistor receives the second control signal, a first pole of the second transistor receives the compensation voltage, and a second pole of the second transistor is connected to the second node.

4. The pixel circuit according to claim 1, wherein the pixel circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor, the drive transistor is connected in series between the first light-emitting control transistor and the second light-emitting control transistor, and a gate of the first light-emitting control transistor and a gate of the second light-emitting control transistor both receive a light-emitting control signal. The first control terminal receives the light-emitting control signal, and the light-emitting control signal is multiplexed as the first control signal.

5. The pixel circuit according to claim 4, wherein a first pole of the first light-emitting control transistor receives the first power supply voltage. The compensation module comprises a first transistor and a second transistor. A gate of the first transistor receives the light-emitting control signal, a first pole of the first transistor is connected to a second pole of the first light-emitting control transistor, and a second pole of the first transistor is connected to the second node. A gate of the second transistor receives the second control signal, a first pole of the second transistor receives the compensation voltage, and a second pole of the second transistor is connected to the second node.

6. The pixel circuit according to claim 1, wherein a voltage value of the first power supply voltage received by the first input terminal is V1, a voltage value of the compensation voltage received by the second input terminal is V2, and V2>V1.

7. The pixel circuit according to claim 6, wherein V2=V1+△V, and △V is a voltage drop generated when the first power supply voltage is transmitted on a signal line.

8. The pixel circuit according to claim 1, wherein the voltage control module comprises a voltage limiting unit, a first end of the voltage limiting unit receives a first voltage, a second end of the voltage limiting unit is connected to the second node, and the voltage limiting unit is used to turn on to pull down the potential of the second node when the voltage of the second node is greater than the first voltage.

9. The pixel circuit according to claim 8, wherein the voltage limiting unit comprises a voltage limiting transistor, a gate of the voltage limiting transistor is connected to a first pole of the voltage limiting transistor, a second pole of the voltage limiting transistor is connected to the second node, and the first pole of the voltage limiting transistor receives the first voltage.

10. The pixel circuit according to claim 9, wherein a voltage value of the first voltage is greater than a voltage value of the first power supply voltage received by the first input terminal.

11. The pixel circuit according to claim 9, wherein the first pole of the voltage limiting transistor is electrically connected to the second input terminal of the compensation module, and the compensation voltage is multiplexed as the first voltage.

12. The pixel circuit according to claim 1, wherein the voltage stabilizing unit comprises a voltage stabilizing capacitor, a first pole plate of the voltage stabilizing capacitor receives the second voltage, and a second pole plate of the voltage stabilizing capacitor is connected to the second node. ​ ​ ​ ​ ​ ​ ​ ​ ​ 13. The pixel circuit of claim 1, wherein a first end of the voltage stabilizing unit is electrically connected to the second input end of the compensation module, and the compensation voltage is multiplexed as the second voltage.

14. The pixel circuit of claim 1, wherein in a working period of the pixel circuit, an ending time of an enable signal in the second control signal is earlier than a starting time of an enable signal in the first control signal.

15. The pixel circuit of claim 14, wherein the pixel circuit further comprises a data writing transistor, a gate of the data writing transistor receives a third control signal, and a working period of the pixel circuit comprises a data writing stage, the data writing transistor is configured to open in the data writing stage to write a data voltage into the pixel circuit; in the working period of the pixel circuit, an ending time of an enable signal in the third control signal is earlier than an ending time of an enable signal in the second control signal.

16. A display panel, characterized by A display panel comprising a plurality of pixel circuits as claimed in any one of claims 1 to 15.

17. The display panel of claim 16, wherein the display panel comprises a power supply line and a compensation signal line, the power supply line provides the first power supply voltage, and the compensation signal line provides a compensation voltage; the pixel circuit comprises a first light emitting control transistor, and the first light emitting control transistor in the plurality of pixel circuits is connected to the power supply line; the compensation module comprises a second transistor, and the second transistor in the plurality of pixel circuits is connected to the compensation signal line.

18. A display device comprising: A display panel comprising the display panel of claim 16.

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