A communication method, chip and electronic device

Abstract

The application relates to the communication technical field and discloses a communication method, a chip and an electronic device. The method comprises the following steps: a first circuit sends a first signal to each slave unit; each slave unit respectively performs digital conversion processing on the first signal to obtain second signal data, the second signal data of each slave unit comprises a first conversion signal corresponding to the first signal and a first noise signal in the digital conversion processing process, and the first noise signals in the slave units are different; each slave unit obtains a corresponding modified address of each slave unit based on the second signal data in each slave unit; and a master unit communicates with each slave unit based on the corresponding modified address of each slave unit. Based on the above scheme, the slave unit address can be modified without increasing the system resources of the master control platform, the independent control of the master unit on each slave unit is realized, and the system cost is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, and in particular to a communication method, a chip and an electronic device. BACKGROUND

[0002] Inter-Integrated Circuit (IIC) or improved inter integrated circuit (I3C) is a bidirectional two-wire synchronous serial bus, which realizes data transmission between devices through a serial data line (SDA) and a serial clock line (SCL). Among them, the device that initializes the data transmission of the IIC bus and generates a clock signal that allows transmission is called a host unit (such as a controller), and any device that is addressed, that is, transported data, is called a slave unit (such as various sensors, etc.).

[0003] In some current schemes, different power supplies are provided by the host unit to the multiple slave units for independent power supply, the operation of modifying the address of the slave unit is performed, and the independent control of the host unit on the multiple slave units is realized according to the slave units with different device addresses. In the above scheme, a power supply needs to be added, resulting in a large system cost. SUMMARY

[0004] To solve the above problems, the present application provides a communication method, a chip and an electronic device.

[0005] In a first aspect, the present application provides a communication method for an electronic device, the electronic device comprising a host unit, a plurality of slave units and a first circuit. The first circuit sends a first signal to each slave unit; each slave unit respectively performs digital conversion processing on the first signal to obtain second signal data, the second signal data of each slave unit comprising a first conversion signal corresponding to the first signal and a first noise signal in the digital conversion processing process, the first noise signal in each slave unit being different; each slave unit obtains a modified address corresponding to each slave unit based on the second signal data in each slave unit; and the host unit communicates with each slave unit based on the modified address corresponding to each slave unit.

[0006] In the scheme, the first noise signal is generated in the process of digital conversion of the first signal by each slave unit, and the first noise signal has randomness, that is, the first noise signal is different, so the second signal data obtained by each slave unit is different, and thus the modification address corresponding to each slave unit can be obtained based on the second signal data in the slave unit. That is, the scheme provided by the application can modify the address of the slave unit without increasing the system resources of the host control platform, so as to realize the independent control of the host unit to each slave unit and effectively reduce the system cost.

[0007] In an implementable manner, the host unit detects that the modified addresses of at least two slave units are the same, and the host unit sends a second enabling signal to the processing module of each slave unit with the same modified address.

[0008] In an implementable manner, the processing module of each slave unit obtains the modification address corresponding to each slave unit based on the second signal data in each slave unit, which includes that the processing module of each slave unit selects a number of first preset bits from the maximum fidelity output interval in the second signal data as the address of each slave unit.

[0009] In an implementable manner, the processing module of each slave unit determines the modification address corresponding to each slave unit based on the first noise signal corresponding to each slave unit.

[0010] In an implementable manner, the processing module of each slave unit obtains the modification address corresponding to each slave unit based on the second signal data in each slave unit, which includes that the processing module of each slave unit selects a number of second preset bits from the first noise signal corresponding to each slave unit as the modification address corresponding to each slave unit.

[0011] In an implementable manner, the processing module of each slave unit selects a number of second preset bits from the first noise signal corresponding to each slave unit as the address of each slave unit, which includes that when the number of bits of the first noise signal is less than the number of second preset bits, the processing module of each slave unit performs copy splicing processing on part of the signal data in the first noise signal corresponding to each slave unit according to a preset arrangement manner, and takes the spliced data as the modification address corresponding to each slave unit.

[0012] In an implementable manner, the processing module of each slave unit obtains the modification address corresponding to each slave unit based on the second signal in each slave unit, which includes that when the value of the second signal data is greater than a first threshold, the processing module of each slave unit takes the first signal of the first circuit corresponding to the second signal data as the modification address corresponding to each slave unit.

[0013] In an implementable mode, the first circuit comprises a sensor, and the first signal is a sensing signal of the sensor; the sensor comprises a temperature sensor, a Hall sensor or a pressure sensor.

[0014] In an implementable mode, the host unit of the electronic device sends the first modification enabling signal to the processing module of each slave unit.

[0015] In a second aspect, the present application provides an electronic device, comprising a host unit, a plurality of slave units and a first circuit; each slave unit in the plurality of slave units comprises an analog-to-digital converter module and a processing module; the host unit is configured to send a first modification enabling signal to each slave unit; the first circuit is configured to send a first signal to each slave unit; each slave unit is configured to perform digital conversion processing on the first signal to obtain second signal data, each slave unit comprising a first conversion signal corresponding to the first signal and a first noise signal in the conversion process, the first noise signals in each slave unit being different; the processing module of each slave unit is configured to obtain a modification address corresponding to each slave unit based on the second signal data in each slave unit.

[0016] In an implementable mode, each slave unit comprises a power supply end, a ground end and a clock signal end, and the analog-to-digital converter module of each slave unit is connected to the power supply end, the ground end and the clock signal end of each slave unit.

[0017] In a third aspect, the present application provides a chip, which is configured to execute the communication method mentioned in the present application. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 According to some embodiments of the present application, an application scenario of an embodiment of the present application is shown;

[0019] Figure 2 According to some embodiments of the present application, a flowchart of a communication method is shown;

[0020] Figure 3 According to some embodiments of the present application, a schematic diagram of the influence of noise on the process of converting the first signal into the second signal data by the ADC module is shown;

[0021] Figure 4 According to some embodiments of the present application, a schematic diagram of converting the second signal data into the slave unit address by the ADC module is shown;

[0022] Figure 5 According to some embodiments of the present application, a schematic diagram of converting the second signal data in the slave unit into the slave unit device address is shown;

[0023] Figure 6According to some embodiments of the present invention, a schematic diagram is shown of another slave unit converting second signal data in a slave unit into a slave unit device address;

[0024] Figure 7 According to some embodiments of the present invention, a schematic diagram showing the relationship between a second signal data of an ADC module and a first signal of a first circuit is provided;

[0025] Figure 8 According to some embodiments of the present invention, a schematic diagram of a slave unit chip structure provided in this application embodiment is shown. Detailed Implementation

[0026] The embodiments of this application include, but are not limited to, a communication method, a chip, and an electronic device.

[0027] The following is combined Figure 1 This application describes the application scenarios of the embodiments of this application. For example... Figure 1 As shown, the communication method mentioned in the embodiments of this application can be used in scenarios where a master unit communicates with multiple slave units, such as slave unit 1, slave unit 2, and slave unit 3. In this application, master unit 1 can be a controller, and slave units 1, 2, and 3 can be corresponding response devices such as memory, display, and sensor, respectively. The number and type of the slave units can be set as needed, and this application does not impose any restrictions. As previously mentioned, in an IIC / I3C bus system architecture with one master unit and multiple slave units, the same master unit needs to control multiple slave units with the same device address. Due to the limitations of the IIC / I3C protocol, the IIC / I3C master unit will communicate with all slave units with the same device address simultaneously, that is, issue the same instructions to all slave units. If all IIC / I3C slave units with the same device address return data to the master unit, the IIC / I3C master unit cannot distinguish which slave unit the received data comes from, that is, the master unit cannot communicate with each slave unit individually.

[0028] As mentioned earlier, existing solutions generally require additional system resources to enable communication between the master unit and multiple slave units with the same device address.

[0029] To solve the above problems, the embodiment of the application provides a communication method. The method is used for an electronic device, the electronic device comprises a host unit, a plurality of slave unit devices and a first circuit; the method comprises the following steps: the first circuit sends a first signal to each slave unit; each slave unit respectively performs digital conversion processing on the first signal to obtain second signal data, the second signal data of each slave unit comprises a first conversion signal corresponding to the first signal and a first noise signal in the digital conversion processing process, the first noise signals in the slave units are different; each slave unit obtains a modified address corresponding to the slave unit based on the second signal data in the slave unit; and the host unit communicates with each slave unit based on the modified address corresponding to each slave unit.

[0030] It can be understood that the first noise signal is generated in the process of digital conversion processing of the first signal by each slave unit, the first noise signal has randomness, that is, the first noise signal is different, therefore, the second signal data obtained by each slave unit is different, so that the modified address corresponding to each slave unit can be obtained based on the second signal data in the slave unit, and the host unit communicates with each slave unit based on the modified address corresponding to each slave unit. That is, the scheme provided by the application can realize modifying the IIC / I3C slave unit address under the IIC / I3C architecture of one master and multiple slaves without increasing the system resources of the master control platform, so as to realize independent control of the host unit on each slave unit and effectively reduce the system cost.

[0031] The following will be described in detail Figure 2 The communication method will be described in detail. Figure 2 A flowchart of a communication method is shown, the method comprises the following steps:

[0032] S201: The first circuit sends a first signal to each slave unit.

[0033] In some embodiments, the first circuit can comprise a sensor, the sensor comprises a temperature sensor, a hall sensor or a pressure sensor or any sensor, and the first signal comprises a sensing signal sent by the sensor. The first circuit sends the sensing signal to each slave unit for any sensor in the first circuit, and each slave unit can receive the first signal through the pin with input function on each slave unit.

[0034] In some embodiments, the host unit of the electronic device sends a first modification enable signal to the processing module of each slave unit, so that each slave unit modifies the address.

[0035] S202: Each slave unit respectively performs digital conversion processing on the first signal to obtain second signal data, the second signal data of each slave unit including a first conversion signal corresponding to the first signal and a first noise signal in the digital conversion processing process, the first noise signal in each slave unit being different.

[0036] In some embodiments, an Analog to Digital Converter (ADC) module in each slave unit can perform digital conversion processing on the first signal to obtain the second signal data. Figure 3 A schematic diagram showing that the ADC module is affected by noise in the process of converting the first signal into the second signal data is shown. As Figure 3 shown, the power supply end AVDD, the clock signal end CLK, and the ground end of the ADC module all have different sizes and different data of noise. At the same time, the first signal at the input end has noise, and the second signal data converted and output by the ADC module also has noise. Since the second signal data of each slave unit includes the first noise signal, the first noise signal generated by each slave unit has randomness, and the second signal data obtained by each slave unit is not the same.

[0037] In some embodiments, the host unit detects that there are at least two slave units with the same modified address in each slave unit, and the host unit sends a second enable signal to the processing module of each slave unit with the same modified address, so that the slave units with the same modified address can further modify the address according to the method mentioned in the present application until the modified addresses of all slave units are all different.

[0038] S203: Each slave unit obtains a corresponding modified address of each slave unit based on the second signal data in each slave unit.

[0039] In some embodiments, the processing module in each slave unit selects a number of digits of a first preset bit number (or referred to as a preset bit number) from a maximum fidelity output interval of the second signal data as the address of each slave unit. The following takes M bits as the first preset bit number and takes one slave unit as an example to explain the address modification method of the slave unit: for example, as Figure 4As shown, the ADC module of each slave unit receives the first signal input by the first circuit, and converts the output second signal data to N bits (i.e. 0 bit to N-1 bit). M bits (i.e. 0 bit to M-1 bit) of the signal in the maximum fidelity interval (i.e. valid second signal data) of the output second signal data from the ADC module is selected as the device address of the slave unit, and output to the IIC module. For example, when the first signal input by the ADC module reaches the full swing of the resolution of the ADC module (i.e. the first signal input by the ADC module is all valid signal), M bits of data can be selected from N-1 bit to 0 bit (i.e. from the high bit to the low bit) of the second signal data converted and output by the ADC module as the device address of the slave unit. Wherein, N and M are two independent values, i.e. the application does not limit the size relationship between M and N, i.e. N>M or N<M or N=M, which can be mentioned in the scope of the embodiments of the application.

[0040] In some embodiments, the processing module in each slave unit determines the modified address corresponding to each slave unit based on the first noise signal corresponding to each slave unit.

[0041] In some embodiments, the processing module in each slave unit selects a number of second preset bits from the first noise signal corresponding to each slave unit as the modified address corresponding to each slave unit.

[0042] For example, as shown in Figure 4 The ADC module receives the first signal input by the first circuit, and converts the output second signal data to N bits (i.e. 0 bit to N-1 bit). The first noise signal with N bits in the second signal data output by the ADC module can be selected as the modified address corresponding to the slave unit. For example, M bits of data can be selected from 0 bit to N-1 bit (i.e. from the low bit to the high bit) of the first noise signal output by the ADC module as the device address of the slave unit.

[0043] When the number of bits of the first noise signal output by the ADC module is small, for example, the number of bits of the first noise signal is M / 4 bits, the M / 4 bits of the first noise signal can be arranged in different arrays to obtain M bits of data, and used as the device address of the slave unit. For example, 4 bits of the first noise signal with the number of bits of M / 4 bits can be copied and spliced into data with the number of bits of M bits, and used as the device address of the slave unit. Wherein, N and M are two independent values, that is, the application does not limit the size relationship between M and N, that is, N>M or N<M or N=M, which can be mentioned in the embodiment of the application.

[0044] In some embodiments, when the number of bits of the first noise signal is less than the second preset number of bits, each slave unit copies and splices part of the signal data in the first noise signal corresponding to each slave unit according to a preset arrangement manner, and uses the copied and spliced data as the modified address corresponding to each slave unit.

[0045] For example, the number of bits of the first noise signal is N bits, P bits (P<N) of data are selected from the N bits, and spliced in different arrays to obtain the device address of the slave unit with M bits, or the position of the second signal data in the N bits is disordered and the data is used as the device address of the slave unit. For example, the number of bits of the first noise signal is 4 bits, and the number of bits of the device address of the slave unit is 2 bits. 1 bit is selected from the number of bits of the first noise signal, and the selected value is copied and spliced to obtain the device address of the slave unit with 2 bits. Wherein, N and M are two independent values, that is, the application does not limit the size relationship between M and N, that is, N>M or N<M or N=M, which can be mentioned in the embodiment of the application.

[0046] S204: The host unit communicates with each slave unit based on the modified address corresponding to each slave unit.

[0047] Since the slave units have been modified to different device addresses, the host unit can communicate with the slave units with different device addresses individually, and realize independent control of the host unit over each slave unit.

[0048] The address modification method of each slave unit is illustrated below.

[0049] Figure 5 A method for modifying the device address of three slave units is shown. As Figure 5As shown, the device addresses of the slave unit 1, the slave unit 2 and the slave unit 3 are all 2-bit byte number 6C before modification, and the second signals received by the slave units are all 4-bit byte number. During the digital conversion of the first signals, the slave units generate first noise signals, and the first noise signals are random, i.e., the first noise signals are different, so the second signal data obtained by the slave units are different.

[0050] When the host unit sends the first modification enabling signal, each slave unit selects 2-bit byte number from the low bit to the high bit of the byte number in the received second signal as the device address of the slave unit. For example, the 4-bit byte number of the second signal of the slave unit 1 is 1223, and the slave unit 1 selects 2-bit byte number 23 from the low bit to the high bit of the byte number in the second signal as the device address of the slave unit 1; the 4-bit byte number of the second signal received by the slave unit 2 is 1287, and the slave unit 2 selects 2-bit byte number 87 from the low bit to the high bit of the byte number in the second signal as the device address of the slave unit 2; the 4-bit byte number of the second signal of the slave unit 3 is 1226, and the slave unit 3 selects 2-bit byte number 26 from the low bit to the high bit of the byte number in the second signal as the device address of the slave unit 3.

[0051] In some embodiments, the host unit detects that the modified addresses of at least two slave units are the same, and the host unit sends a second enabling signal to the slave units with the same modified address.

[0052] As Figure 6As shown, when the host unit sends the first enable signal, each slave unit selects 2-bit byte number from low bit to high bit of the received second signal as the device address of each slave unit. For example, the 4-bit byte number of the second signal of the slave unit 1 is 1223, and the slave unit 1 selects 2-bit byte number 23 from low bit to high bit of the byte number in the second signal as the device address of the slave unit 1; the 4-bit byte number of the second signal of the slave unit 2 is 1223, and the slave unit 2 selects 2-bit byte number 23 from low bit to high bit of the byte number in the second signal as the device address of the slave unit 2; the 4-bit byte number of the second signal of the slave unit 3 is 1226, and the slave unit 3 selects 2-bit byte number 26 from low bit to high bit of the byte number in the second signal as the device address of the slave unit 3. The host unit detects that the slave unit 1 and the slave unit 2 have the same device address at this time, and the host unit sends the second modification enable signal to the slave unit 1 and the slave unit 2. The slave unit again acquires the signal sent by the first circuit, and respectively performs digital conversion processing on the signal based on the ADC module to acquire the signal data after conversion processing. For example, the 4-bit byte number of the converted signal data acquired again is 1256, and the slave unit 1 selects 2-bit byte number 56 from low bit to high bit of the byte number in the converted signal data as the device address of the slave unit 1; the 4-bit byte number of the converted signal data acquired by the slave unit 2 is 1243, and the slave unit 2 selects 2-bit byte number 43 from low bit to high bit of the byte number in the converted signal data as the device address of the slave unit 2.

[0053] In some embodiments, the processing module in each slave unit determines that the second signal data is greater than the first threshold value, and takes the first signal of the first circuit corresponding to the second signal data in each slave unit as the modified address corresponding to each slave unit.

[0054] For example, the second signal data output by the ADC module can be used as an indirect evaluation criterion for modifying the address of the slave unit. That is, the second signal data of a certain output of the ADC module is selected as a threshold value, and when the second signal data meets the threshold value, the device address of each slave unit can be modified to the first signal of the first circuit. Figure 7 The relationship between the second signal data of the ADC module and the first signal of the first circuit is shown in the schematic diagram. Figure 7As shown, the ordinate represents the second signal data of the ADC module, and the abscissa represents the first signal of the first circuit. Ideally, the second signal data of the ADC module and the first signal of the first circuit are in a linear relationship. For example, when the threshold value of the second signal data of the ADC module is Th0, the device address of the slave unit can be modified to the data of the first signal A of the first circuit when the second signal data meets the threshold value; when the threshold value of the second signal data of the ADC module is Th1, the device address of the slave unit can be modified to the data of the first signal B of the first circuit when the second signal data meets the threshold value.

[0055] Through the above method, the address of the IIC / I3C slave unit can be modified without increasing the system resources of the master control platform under the IIC / I3C architecture of one master and multiple slaves, so as to realize the independent control of the master unit over the slave unit based on different device addresses of the slave unit. The scheme is simple and easy to implement, and the system cost is relatively low.

[0056] To solve the above problems, in some embodiments, the address of the slave unit can be modified by reversely connecting one slave unit to SCL and SDA and normally connecting another slave unit to SCL and SDA, so as to realize the independent control of the master unit over the two slave units. Although this scheme does not need to increase additional system resources, it can only cope with the case that there are only two slave units in the system architecture, and the applicable scene is limited.

[0057] The following will be described in combination with Figure 8 The slave unit chip provided by the embodiments of the present application is introduced. As shown in Figure 8 The slave unit chip provided by the embodiments of the present application has an analog region and a digital region, and the analog region is connected to the digital region. The analog region can include an ADC module, the input end of the ADC module is connected to a first circuit, and the output end is connected to the input end of a digital signal processing (DSP) module, for receiving a first signal from the first circuit and performing digital-to-analog conversion to output second signal data to the DSP module.

[0058] The digital region can include a DSP module and an IIC / I3C module (or referred to as a processing module), wherein the input end of the DSP module is connected to the output end of the ADC module, and the output end of the DSP module is connected to the IIC / I3C module. The DSP module is used to receive and process the second signal data transmitted by the ADC module, and transmit third signal data to the IIC / I3C module. The IIC / I3C module is used to receive the third signal data processed by the DSP module, and realize the data transmission between the master unit and each slave unit.

[0059] In some embodiments, the processing module can be configured to select, from the second signal data, a number of bits in the maximum fidelity output interval as the modified address corresponding to each slave unit.

[0060] The processing module can be configured to select, from the first noise signal corresponding to each slave unit, a number of bits in the second preset bit number as the modified address corresponding to each slave unit.

[0061] The processing module can be configured to perform copy and splice processing on part of the signal data in the first noise signal corresponding to each slave unit according to a preset arrangement manner, and take the copy and splice processed data as the modified address corresponding to each slave unit.

[0062] The processing module can be configured to, when determining that the value of the second signal data is greater than the first threshold, take the second signal data as the modified address corresponding to each slave unit.

[0063] Embodiments of the present application also provide an electronic device, which comprises a host unit, a plurality of slave units, and a first circuit; each slave unit in the plurality of slave units comprises an analog-to-digital converter module and a processing module;

[0064] The host unit is configured to send a first modification enable signal to each slave unit.

[0065] The first circuit is configured to send a first signal to each slave unit.

[0066] The analog-to-digital converter module of each slave unit is configured to perform digital conversion processing on the first signal respectively, and obtain second signal data; each slave unit comprises a first conversion signal corresponding to the first signal and a first noise signal in the conversion process, and the first noise signals in each slave unit are different.

[0067] The processing module of each slave unit is configured to obtain a modified address corresponding to each slave unit based on the second signal data in each slave unit.

[0068] In some embodiments, each slave unit comprises a power supply end, a ground end, and a clock signal end, and the analog-to-digital converter module of each slave unit is connected to the power supply end, the ground end, and the clock signal end of each slave unit respectively.

[0069] In some embodiments, the electronic device provided by the embodiments of the present application can be used to perform the communication method mentioned in the embodiments of the present application.

[0070] Embodiments of the present application also provide a chip, which is configured to perform the communication method mentioned in the embodiments of the present application.

[0071] Embodiments disclosed herein can be implemented in hardware, software, firmware, or any combination thereof. Embodiments of the application can be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0072] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0073] The program code can be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code can be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language can be a compiled or interpreted language.

[0074] In some cases, the disclosed embodiments can be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) medium, which can be read and executed by one or more processors. For example, the instructions can be distributed over the network or by other computer readable media. Thus, a machine-readable medium can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including without limitation floppy disks, optical disks, optical disks, CD-ROMs, magnetic cassettes or tapes, ROMs, RAMs, erasable programmable ROMs (EPROMs), electrically erasable programmable ROMs (EEPROMs), magnetic or optical cards, flash memories, or tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals digital signals, etc.). Accordingly, the machine-readable media includes any type of computer-readable media.

[0075] In the drawings, some of the structures or method features can be shown in particular arrangements and / or orders. However, it should be understood that such specific arrangements and / or orders can not be required. Instead, these features can be arranged in a different manner and / or order than shown in the illustrative drawings, in some embodiments. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments, and that feature, or other features, can be excluded from some embodiments or combined in various permutations.

[0076] It should be noted that each unit / module mentioned in the embodiments of the devices of the present application is a logical unit / module, and in physical form, one logical unit / module can be a physical unit / module, or a part of a physical unit / module, or a combination of multiple physical unit / modules, and the physical implementation form of the logical unit / module itself is not the most important, and the combination of the functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that the above-mentioned device embodiments do not have other units / modules.

[0077] It should be noted that in the examples and descriptions of the present patent, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0078] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it should be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the present application.

Claims

1. A communication method, characterized by, A communication method for an electronic device, the electronic device comprising a host unit, a plurality of slave units and a first circuit; the method comprising: the first circuit sending a first signal to the slave units; the slave units respectively performing digital conversion processing on the first signal to obtain second signal data, the second signal data of the slave units comprising first conversion signals corresponding to the first signal and first noise signals in the digital conversion processing, the first noise signals in the slave units being different, and the second signal data of the slave units being different; the slave units obtaining modified addresses corresponding to the slave units based on the second signal data in the slave units; the host unit communicating with the slave units based on the modified addresses corresponding to the slave units.

2. The communication method according to claim 1, characterized by, Further comprising: the host unit detecting that the modified addresses of at least two slave units among the slave units are the same, and the host unit sending a second enable signal to processing modules of the slave units with the same modified addresses.

3. The communication method according to claim 1 or 2, characterized by, the slave units obtaining the modified addresses corresponding to the slave units based on the second signal data in the slave units, comprising: the processing modules in the slave units selecting a first preset number of digits from a maximum fidelity output interval in the second signal data as the addresses of the slave units.

4. The communication method of claim 1 or 2, wherein the processing modules in the slave units obtaining the modified addresses corresponding to the slave units based on the second signal data in the slave units, comprising: the processing modules in the slave units determining the modified addresses corresponding to the slave units based on the first noise signals corresponding to the slave units.

5. The communication method of claim 4, wherein the processing modules in the slave units determining the modified addresses corresponding to the slave units based on the first noise signals corresponding to the slave units, comprising: the processing modules in the slave units selecting a second preset number of digits from the first noise signals corresponding to the slave units as the modified addresses corresponding to the slave units.

6. The communication method according to claim 5, wherein, the processing modules in the slave units selecting a second preset number of digits from the first noise signals corresponding to the slave units as the addresses of the slave units, comprising: when the number of bits of the first noise signals is less than the second preset number of bits, the processing modules in the slave units perform copy-splicing processing on part of the signal data in the first noise signals corresponding to the slave units according to a preset arrangement mode, and take the copy-spliced data as the modified addresses corresponding to the slave units.

7. The communication method according to claim 1 or 2, wherein, the processing modules in the slave units obtaining the modified addresses corresponding to the slave units based on the second signal data in the slave units, comprising: when the value of the second signal data is greater than a first threshold, the processing modules in the slave units take the first signal of the first circuit corresponding to the second signal data as the modified addresses corresponding to the slave units.

8. The communication method of claim 1, wherein, The first circuit includes a sensor, and the first signal is a sensing signal of the sensor. The sensor includes a temperature sensor, a Hall sensor, or a pressure sensor.

9. The communication method of claim 1, wherein Further comprising: The host unit of the electronic device sends a first modification enabling signal to the processing module of each slave unit.

10. An electronic device, comprising: The electronic device includes a host unit, a plurality of slave units, and a first circuit; each slave unit of the plurality of slave units includes an analog-to-digital converter module and a processing module; The host unit is configured to send a first modification enabling signal to each slave unit; The first circuit is configured to send a first signal to each slave unit; The analog-to-digital converter module of each slave unit is configured to perform digital conversion processing on the first signal to obtain second signal data; each slave unit includes a first conversion signal corresponding to the first signal and a first noise signal in the conversion process; the first noise signals in each slave unit are different, and the second signal data of each slave unit is different; The processing module of each slave unit is configured to obtain a modification address corresponding to each slave unit based on the second signal data in each slave unit.

11. The electronic device of claim 10, wherein, Each slave unit includes a power supply end, a ground end, and a clock signal end; the analog-to-digital converter module of each slave unit is connected to the power supply end, the ground end, and the clock signal end of each slave unit.

12. A chip, characterized by The chip is configured to perform the communication method of any one of claims 1-9.

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