A high-temperature pressure sensing chip based on a single crystal silicon wafer and a three-dimensional integration method

Abstract

The application discloses a high-temperature pressure sensing chip based on a single crystal silicon wafer and a three-dimensional integration method, and a manufacturing process of the chip comprises a force sensing resistor manufacturing step, an insulation isolation step, a high-temperature-resistant electrode and interconnection manufacturing step, a pressure-sensitive diaphragm etching step and a bonding step. The application uses a method of etching an insulation isolation groove around the force sensing resistor, filling and covering an insulation layer and precisely etching a lower layer bulk silicon of the force sensing resistor, avoids the problem of failure of a traditional single crystal silicon pn junction isolation high-temperature leakage current, does not depend on expensive materials such as SOI wafers and silicon carbide wafers, uses a general single crystal silicon wafer to realize mutual insulation isolation between Wheatstone bridge force sensing resistors, and meets high-temperature working requirements. The proposed air-tight leadless bonding method based on a through silicon via further improves the reliability of the pressure sensing chip. Meanwhile, the manufacturing method is fully compatible with a silicon-based CMOS process, and on-chip system integration can be realized.

Description

Technical Field

[0001] This invention belongs to the field of electronic technology, and in particular relates to a high-temperature pressure sensing chip based on a single-crystal silicon wafer and a three-dimensional integration method. Background Technology

[0002] In recent years, the rapid development of information technologies such as the Internet of Things, big data, and artificial intelligence has placed higher demands on the functions of electronic systems. Electronic systems not only need powerful data computing and storage capabilities, but also require sensitive perception of the external environment. This necessitates integrating chips with different functions to form a more complex "sensing-storage-computing integrated" system. Among these, sensor chips are analogous to the five senses of a person perceiving the external environment. Integrating multi-physical quantity sensor chips into a system is of great significance for the real-time monitoring and control of complex physical quantities in modern industrial scenarios. High-temperature pressure sensor chips are an important type of physical quantity sensor in modern industry, widely used for pressure measurement in high-temperature environments such as aerospace, deep well exploration, and reaction vessel control.

[0003] Although piezoresistive pressure sensing chips based on single-crystal silicon have advantages such as mature technology, high sensitivity, and good linearity, and are widely used in low-temperature environments below 120°C, their performance in high-temperature environments above 120°C fails due to increased leakage current, as the PN junction provides insulation between the force resistor and the silicon substrate. Therefore, it is generally believed that pressure sensing chips operating in high-temperature environments above 120°C cannot be manufactured using single-crystal silicon wafers. To meet the pressure measurement requirements in high-temperature environments above 120°C, high-temperature pressure sensing chips based on silicon-on-insulator (SOI) have been developed. SOI wafers introduce an insulating buried oxide layer between the top silicon layer and the silicon substrate on top of a single-crystal silicon wafer, effectively isolating leakage current between the silicon resistor and the silicon substrate, solving the problem of high-temperature isolation failure of conventional single-crystal silicon PN junctions. However, SOI wafers are expensive, typically more than ten times the price of single-crystal silicon wafers, limiting the large-scale application of high-temperature pressure sensing chips. Summary of the Invention

[0004] To address the issue of high-temperature failure of ordinary single-crystal silicon wafer pn junction isolation, the purpose of this application is to provide a high-temperature pressure sensing chip based on a single-crystal silicon wafer and a three-dimensional integration method. This not only manufactures a pressure sensing chip that can operate in high-temperature environments above 120°C using ordinary single-crystal silicon wafers, but also ensures full compatibility with silicon-based CMOS processes, enabling system-on-wafer (SOW) integration.

[0005] According to a first aspect of the embodiments of this application, a high-temperature pressure sensing chip based on a single-crystal silicon wafer is provided, the fabrication process of which includes:

[0006] Force-sensitive resistor manufacturing steps: Fabricating pressure-sensitive resistors on a single-crystal silicon wafer;

[0007] Insulation isolation steps: Etching an insulation isolation trench around the force-sensitive resistor, depositing an insulating layer in the insulation isolation trench, on the upper surface of the force-sensitive resistor and on the upper surface of the single-crystal silicon wafer, and depositing a passivation layer on the lower surface of the single-crystal silicon wafer;

[0008] High-temperature resistant lead interconnect manufacturing steps: Etch an insulating layer in the ohmic contact area of ​​the force-sensitive resistor to manufacture a high-temperature resistant lead interconnect;

[0009] The pressure-sensitive diaphragm etching step is as follows: The passivation layer is etched until the silicon on the lower surface of the force-sensitive resistor is completely etched away to obtain the pressure-sensitive diaphragm.

[0010] Bonding step: The pressure-sensitive diaphragm is vacuum bonded to the substrate to form a high-temperature pressure sensing chip with a vacuum reference cavity.

[0011] Furthermore, the manufacturing steps of the force-sensitive resistor are as follows:

[0012] The shape of a Wheatstone bridge force-sensitive resistor is photolithographically etched on the upper surface of a single-crystal silicon wafer. P-type ion implantation is then performed, the photoresist is removed, and high-temperature annealing is carried out to form a p-type force-sensitive resistor with a uniform impurity concentration distribution along the depth direction.

[0013] Furthermore, the doping concentration of the force-sensitive resistor after annealing is greater than 3E18 cm⁻¹. -3 .

[0014] Furthermore, the insulation isolation step includes:

[0015] Insulating isolation trench etching step: Photolithography and etching of insulating isolation trenches around the force-sensitive resistor on the upper surface of the single-crystal silicon wafer, wherein the depth of the insulating isolation trenches is greater than or equal to the depth of the force-sensitive resistor;

[0016] Insulating layer deposition sub-step: depositing a passivation thick film in the insulating isolation trench, on the upper surface of the force-sensitive resistor and on the upper surface of the single crystal silicon wafer, and depositing a passivation layer on the lower surface of the single crystal silicon wafer respectively.

[0017] Furthermore, the passivation thick film growth process is as follows: dry oxygen oxidation to generate a dense silicon dioxide thin layer on the surface of the single crystal silicon wafer and the insulating isolation trench; low-pressure chemical vapor deposition to generate a dense silicon dioxide layer or silicon nitride layer that is thicker than the silicon dioxide thin layer on the surface of the single crystal silicon wafer and the insulating isolation trench for insulating filling and covering; grinding and polishing to form a flat and insulating upper surface;

[0018] The passivation layer is simultaneously deposited on the lower surface of the single-crystal silicon wafer during dry oxidation and low-pressure chemical vapor deposition of silicon dioxide or silicon nitride layers on the upper surface.

[0019] Furthermore, in the passivation thick film growth process, before grinding and polishing, according to the performance requirements of the pressure sensing chip, one or more of the following methods are used to continue depositing a thick film on the wafer surface: plasma-enhanced chemical vapor deposition of silicon dioxide, low-pressure chemical vapor deposition of polycrystalline silicon, sputtering or evaporation or electroplating of metal layers.

[0020] Furthermore, the high-temperature resistant lead interconnect manufacturing step includes:

[0021] Ohmic contact window etching step: Photolithography and etching of the insulating layer above the ohmic contact area of ​​the force-sensitive resistor to form the ohmic contact window;

[0022] The steps for growing lead interconnects are as follows: implanting heavily doped ions into the silicon in the ohmic contact window and annealing; growing refractory metal silicides on the silicon in the ohmic contact window; and growing high-temperature resistant lead interconnects.

[0023] Furthermore, the structure of the metal electrode and interconnect is a high-temperature resistant composite electrode structure of titanium / titanium nitride / titanium / copper compatible with copper-tin silicon through-hole technology, or a high-temperature resistant composite electrode structure of titanium / titanium nitride / platinum / gold compatible with gold-tin transient liquid phase bonding technology.

[0024] Furthermore, the pressure-sensitive diaphragm corrosion step includes the following sub-steps:

[0025] Window etching step: A passivation layer is photolithographically etched and etched on the lower surface of a single-crystal silicon wafer to form a window;

[0026] Protective layer application sub-step: Apply a protective layer to the upper surface of the single-crystal silicon wafer;

[0027] Wet chemical etching sub-step: The lower surface of the single-crystal silicon wafer is anisotropically etched through a window using a wet chemical etching method until the single-crystal silicon layer on the lower surface of the force-sensitive resistor is no longer directly connected through any bulk silicon layer.

[0028] Protective layer removal sub-step: Remove the passivation layer on the lower surface and the protective layer on the upper surface to obtain a C-type pressure-sensitive diaphragm.

[0029] According to a second aspect of the embodiments of this application, a three-dimensional integration method for the above-mentioned high-temperature pressure sensing chip based on a single-crystal silicon wafer is provided, comprising:

[0030] The bottom bonding method involves vacuum bonding the open side of the pressure-sensitive diaphragm to the substrate, and then flip-chip bonding it to the silicon adapter board to form a three-dimensional integrated structure with other electronic chips.

[0031] The top bonding method involves vacuum bonding the non-opening side of the pressure-sensitive diaphragm to the substrate while simultaneously extracting electrical signals based on TSV. The diaphragm is then flip-bonded to a silicon adapter board to form a three-dimensional integrated structure with other electronic chips.

[0032] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0033] First, the present invention uses a method that combines etching insulating isolation trenches around the force-sensitive resistor and filling and covering the insulating layer, and precisely etching the underlying bulk silicon of the force-sensitive resistor. This avoids the problem of high-temperature leakage current failure of traditional single-crystal silicon pn junction isolation. It does not rely on expensive materials such as SOI wafers and silicon carbide wafers. It achieves mutual insulation between Wheatstone bridge force-sensitive resistors using ordinary single-crystal silicon wafers. The manufactured single-crystal silicon pressure sensing chip can work stably in high-temperature environments above 120°C.

[0034] Second, this invention proposes a hermetically tight leadless bonding method compatible with through-silicon via (TSV) technology, which simultaneously completes the vacuum sealing of the pressure sensor based on the sealing ring and the electrical signal extraction based on the TSV in a single bonding process.

[0035] Third, the single-crystal silicon material used in this invention is fully compatible with silicon-based CMOS technology, enabling on-chip system integration.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0038] Figure 1 This is a process flow diagram of the high-temperature pressure sensing chip based on a single-crystal silicon wafer according to the present invention, wherein... Figure 1 (a) in Figure 1 (i) in the diagram represents the structural diagram of each process;

[0039] Figure 2This is a schematic diagram of on-chip system integration of a pressure sensing chip and an integrated circuit chip, in which... Figure 2 (a) in the diagram is a schematic diagram of integration via bonding to the bottom of the pressure-sensitive diaphragm. Figure 2 (b) in the diagram is a schematic diagram of integration via bonding to the top of the pressure-sensitive diaphragm;

[0040] Figure 3 This is a schematic diagram of the leadless package based on through-silicon vias and sealing rings of the present invention, wherein... Figure 3 (a) is a schematic cross-sectional view of a leadless package based on through-silicon vias and sealing rings. Figure 3 (b) is a top view of the pressure-sensitive diaphragm. Figure 3 (c) is a top view of the substrate with through-silicon vias corresponding to the pressure-sensitive diaphragm.

[0041] In the figure: 1. Monocrystalline silicon wafer; 2. Force-sensitive resistor; 3. Insulating isolation trench; 4. Passivation thick film; 5. Passivation layer; 6. Monocrystalline silicon layer; 7. Ohmic contact window; 8. Lead interconnect; 9. Window; 10. Protective layer; 11. Substrate; 12. Vacuum reference cavity; 13. Bonding substrate; 14. TSV; 15. Substrate sealing ring; 16. Pressure-sensitive diaphragm; 17. Diaphragm sealing ring; 18. Pad; 19. Tin sealing ring; 20. Tin microbump; 21. Integrated circuit chip; 22. Silicon wafer adapter board. Implementation

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0043] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0044] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The invention is illustrated using an absolute pressure piezoresistive pressure sensor chip fabricated based on a single-crystal silicon wafer as an example. However, the application scope of the pressure sensor chip applicable to the present invention is not limited to the absolute pressure structure, but also applicable to gauge pressure and differential pressure structures; the shape of the pressure-sensitive diaphragm applicable to the present invention is not limited to the C-type diaphragm, but also applicable to E-type diaphragms and other structures.

[0045] This application provides a high-temperature pressure sensing chip based on a single-crystal silicon wafer 1, the fabrication process of which is as follows: Figure 1 As shown. Figure 1 As shown in (a) in this embodiment, the piezoresistive high-temperature pressure sensor chip is manufactured using an N(100) type double-sided polished single-crystal silicon wafer 1 as the material.

[0046] Manufacturing steps of force-sensitive resistor 2: Fabricate a pressure-sensitive semiconductor force-sensitive resistor 2 on a single-crystal silicon wafer 1;

[0047] Specifically, the shape of the force-sensitive resistor of the Wheatstone bridge is photolithographically etched on the upper surface of the single-crystal silicon wafer 1, followed by high-concentration p-type ion implantation, removal of photoresist, and high-temperature annealing. Figure 1 As shown in (b), a p-type force-sensitive resistor 2 with a uniform impurity concentration distribution along the depth direction is formed. In this embodiment, the doping concentration after annealing is preferably greater than 3E18cm⁻¹. -3 The typical depth of the part where the concentration is uniform in the depth direction is about 1 micrometer, usually within 1 micrometer.

[0048] Insulation isolation steps: Etching insulation isolation trench 3 around the force-sensitive resistor 2, depositing an insulating layer in the insulation isolation trench 3, on the upper surface of the force-sensitive resistor 2 and on the upper surface of the single crystal silicon wafer 1, and depositing a passivation layer on the lower surface of the single crystal silicon wafer.

[0049] Specifically, this step may include the following sub-steps: etching of insulating isolation trenches and deposition of insulating layer.

[0050] Etching steps for insulating isolation grooves: (e.g.) Figure 1 As shown in (c), an insulating isolation trench 3 surrounding the force-sensitive resistor 2 is photolithographically etched and etched on the upper surface of the single-crystal silicon wafer 1, wherein the depth of the insulating isolation trench 3 should be greater than or equal to the depth of the portion with uniform doping concentration.

[0051] Insulating layer deposition sub-steps: such as Figure 1 As shown in (d), a passivation thick film 4 is deposited in the insulating isolation trench 3, on the upper surface of the force-sensitive resistor 2 and on the upper surface of the single crystal silicon wafer 1, and a passivation layer 5 is deposited on the lower surface of the single crystal silicon wafer 1.

[0052] Specifically, the passivation thick film 4 has two main functions: one is to protect and insulate the force-sensitive resistor 2, and the other is to form a gas-tight pressure-sensitive diaphragm of a certain thickness together with the single-crystal silicon layer 6 on the plane where the force-sensitive resistor 2 is located. The main function of the passivation layer 5 is to act as a passivation layer for subsequent anisotropic etching.

[0053] In this embodiment, the preferred growth process for the passivation thick film 4 is as follows: dry oxidation to form a dense silicon dioxide thin layer (30~100 nm) on the surface of the single-crystal silicon wafer 1 and the insulating isolation trench 3; low-pressure chemical vapor deposition (LPCVD) to form a dense and relatively thick silicon dioxide layer (500 nm~2 μm) or a silicon nitride layer (50~200 nm) on the surface of the single-crystal silicon wafer 1 and the insulating isolation trench 3 for insulating filling and coverage. After this, depending on the performance requirements of the pressure sensing chip, one or more methods such as plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide, LPCVD of polycrystalline silicon, sputtering or evaporation, or electroplating of metal layers can be used to continue depositing a thick film on the wafer surface; grinding and polishing form a smooth and insulating upper surface.

[0054] In this embodiment, the passivation layer 5 is grown by simultaneously depositing a passivation layer of the same thickness on the lower surface while performing dry oxidation and LPCVD silicon dioxide / silicon nitride layer on the upper surface of the single crystal silicon wafer 1.

[0055] Manufacturing steps for high-temperature resistant electrodes and interconnects: Etching an insulating layer in the ohmic contact area of ​​force-sensitive resistor 2 to manufacture high-temperature resistant electrodes and interconnects;

[0056] Specifically, this step may include an etching sub-step for the ohmic contact window 7 and an electrode and interconnect growth sub-step:

[0057] Etching steps for ohmic contact window 7: Photolithography and etching of the passivation thick film 4 above the ohmic contact area of ​​the force-sensitive resistor 2, as shown. Figure 1 As shown in (e), an ohmic contact window 7 is formed;

[0058] Electrode and interconnect growth steps: Heavy doping ion implantation and annealing are performed on the silicon in the ohmic contact window; refractory metal silicides are grown on the silicon in the ohmic contact region; high-temperature resistant interconnects are grown, such as... Figure 1 As shown in (f);

[0059] Specifically, a self-aligned method is preferred to grow refractory metal silicides such as titanium disilicide (TiSi2) on silicon in the ohmic contact window to form a good gold-semiconductor contact; a high-temperature resistant lead interconnect 8 (metal electrode and interconnect) is preferred to be grown by physical vapor deposition (PVD) and lift-off methods. The structure of the high-temperature resistant metal electrode and interconnect is preferably a titanium / titanium nitride / titanium / copper (Ti / TiN / Ti / Cu) high-temperature resistant composite electrode structure compatible with copper-tin through-silicon via (TSV) process, or it can be a titanium / titanium nitride / platinum / gold (Ti / TiN / Pt / Au) high-temperature resistant composite electrode structure compatible with gold (Au)-tin (Sn) transient liquid phase bonding process.

[0060] The pressure-sensitive diaphragm etching step involves etching the passivation layer 5 until the silicon on the lower surface of the force-sensitive resistor 2 is completely etched away to obtain the pressure-sensitive diaphragm. This step may include the following sub-steps:

[0061] Window 9 etching step: Photolithography and etching of passivation layer 5 on the lower surface of single crystal silicon wafer 1 to form window 9;

[0062] Sub-steps for applying protective layer 10: (e.g.) Figure 1 As shown in (g), a protective layer 10 is applied to the upper surface of the single-crystal silicon wafer 1;

[0063] Specifically, the protective layer 10 can be a corrosion-resistant protective adhesive or a corrosion-resistant clamp.

[0064] Wet chemical etching sub-step: The lower surface of the single crystal silicon wafer 1 is anisotropically etched through window 9 using wet chemical etching until the single crystal silicon layer 6 on the lower surface of the force-sensitive resistor 2 is no longer directly connected through any silicon layer.

[0065] In this way, the upper and side surfaces of each force-sensitive resistor 2 are completely separated by insulating isolation trenches 3 filled with passivation thick film 4, while the lower surface has no silicon phase connection, relying on air or vacuum for insulation isolation. Alternatively, after anisotropic etching, a silicon dioxide layer can be deposited on the back side of the single-crystal silicon wafer 1 using PECVD to provide insulation and passivation protection for the lower surface of the force-sensitive resistor 2. The etching solution is preferably, but not limited to, tetramethylammonium hydroxide (TMAH) solution, allowing for precise control of the anisotropic etching rate and depth.

[0066] Protective layer removal sub-step: Remove the passivation layer 5 on the lower surface and the protective layer 10 on the upper surface to obtain a C-type pressure-sensitive diaphragm, such as... Figure 1 As shown in (h) in the diagram.

[0067] Bonding step: Vacuum bond the C-type pressure-sensitive diaphragm 16 to the substrate 11 to form a high-temperature pressure sensing chip with a vacuum reference cavity 12.

[0068] Specifically, for this step, either bottom bonding or top bonding can be used, such as... Figure 1 As shown in (i), this is a schematic diagram of a high-temperature pressure sensor chip formed by bottom bonding. Vacuum bonding methods include, but are not limited to, silicon-silicon bonding, anodic bonding based on high-temperature resistant glass, glass solder bonding, metal thermocompression bonding, transient liquid phase bonding, and BCB bonding.

[0069] In the pressure sensing chip completed according to the above steps, the surrounding area and upper surface of each force-sensitive resistor 2 forming the Wheatstone bridge are filled and covered with a silicon dioxide / silicon nitride layer, and the lower surface has an air / vacuum or silicon dioxide layer. Therefore, each force-sensitive resistor 2 is insulated from each other, and there is no problem of high-temperature leakage current failure. Furthermore, because the force-sensitive resistors are p-type with a diameter higher than 3E18 cm⁻¹, -3 The high concentration of doping suppresses intrinsic excitation at high temperatures, maintaining a positive temperature coefficient. Furthermore, the high-temperature resistant ohmic contact electrodes and interconnects, such as Si / TiSi2 / Ti / TiN / Ti / Cu and Si / TiSi2 / Ti / TiN / Pt / Au, ensure the high-temperature reliability of the metal-semiconductor contact. Therefore, the high-temperature pressure sensing chip proposed in this invention can achieve the same high-temperature operating capability using only ordinary and inexpensive single-crystal silicon wafers without relying on SOI wafers.

[0070] This application also provides a three-dimensional integration method for the above-mentioned high-temperature pressure sensing chip based on a single-crystal silicon wafer. Figure 2 The diagram shows a system-on-chip integration of a pressure sensing chip and an integrated circuit chip, which can form a "sensing-storage-computing integrated" wafer system with complex functions such as sensing, low-latency on-chip data transmission, data processing, and result storage. Figure 2 (a) is a schematic diagram of integration by bonding the bottom of the pressure-sensitive diaphragm 16. Specifically, it is a schematic diagram of 2.5D / 3D heterogeneous integration of the bottom of the pressure-sensitive diaphragm 16 to the substrate 11 and then to the integrated circuit chip 21 on the silicon wafer adapter 22. The packaging process of the pressure sensor using this method is relatively simple. Figure 2 (b) is a schematic diagram of integration via top bonding of the pressure-sensitive diaphragm 16. Specifically, it is a schematic diagram of the structure in which the top of the pressure-sensitive diaphragm 16 is bonded to the bonding substrate 13 with TSV and sealing ring, and then integrated with the integrated circuit chip 21 on the silicon wafer adapter 22 for 2.5D / 3D heterogeneous integration. The force-sensitive resistor, metal electrode and interconnect of the pressure sensor using this packaging method are located inside the sealing ring and isolated from the external atmosphere, which has higher reliability when working in harsh environments.

[0071] For embodiments where integration is achieved via top bonding of the pressure-sensitive diaphragm 16, Figure 3 Image (a) is a schematic cross-sectional view of the leadless package based on through-silicon vias (TSVs) and sealing rings of the present invention. Figure 2 (b) is a top view of the pressure-sensitive diaphragm 16. Figure 3 (c) is a top view of the bonding substrate 13 with through-silicon vias corresponding to the pressure-sensitive diaphragm 16, as shown in Figure 16. Figure 3As shown, the three-dimensional integration method for high-temperature pressure sensing chips based on single-crystal silicon wafers may include:

[0072] Step 1: Preferably, a silicon dioxide passivation layer is deposited on the cavity side of the pressure-sensitive diaphragm 16 using PECVD to protect the force-sensitive resistor 2. A film surface layer is then fabricated on the membrane side of the pressure-sensitive diaphragm 16 as shown in the image. Figure 2 Diaphragm sealing ring 17 shown in (b) of the diagram.

[0073] Step 2: Fabricate the bonding substrate 13, such as Figure 3 As shown in (c), in addition to the TSV 14 and tin microbumps 20, the bonding substrate 13 also has a substrate sealing ring 15 and a tin sealing ring 19 corresponding to the position of the diaphragm sealing ring 17. The diaphragm sealing ring 17 and the substrate sealing ring 15 are preferably made of copper or gold, and are preferably grown by electroplating. The tin sealing ring 19 and the tin microbumps 20 are preferably grown by electroplating.

[0074] Step 3: As Figure 2 As shown in (a), the pads 18 of the pressure-sensitive diaphragm 16 are aligned with the tin microbumps 20 on the TSV 14, and the diaphragm sealing ring 17 of the pressure-sensitive diaphragm is aligned with the tin sealing ring 19 on the substrate sealing ring 15. Wafer-level transient liquid phase bonding is preferably performed under vacuum, heating conditions of 250°C to 300°C, and pressure of 0.5 to 1 MPa. In this way, the vacuum sealing of the pressure sensor based on the sealing ring and the extraction of the electrical signal based on the TSV are simultaneously completed in a single bonding process. After bonding, the tin should be completely depleted, forming a stable copper-tin intermetallic compound Cu3Sn with a high melting point phase at the bonding interface.

[0075] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0076] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A high-temperature pressure sensing chip based on a single-crystal silicon wafer, characterized in that, Its manufacturing process includes: Force-sensitive resistor manufacturing steps: Fabricating pressure-sensitive resistors on a single-crystal silicon wafer; Insulation isolation steps: Etching insulation isolation trenches around the force-sensitive resistor, depositing an insulating layer in the insulation isolation trenches, on the upper surface of the force-sensitive resistor and on the upper surface of the single-crystal silicon wafer, and depositing a passivation layer on the lower surface of the single-crystal silicon wafer, wherein the insulation isolation trenches are only provided on the side of the force-sensitive resistor, and no insulation isolation trenches are provided below the force-sensitive resistor; High-temperature resistant lead interconnect manufacturing steps: Etch an insulating layer in the ohmic contact area of ​​the force-sensitive resistor to manufacture a high-temperature resistant lead interconnect; The pressure-sensitive diaphragm etching step is as follows: The passivation layer is etched until the silicon on the lower surface of the force-sensitive resistor is completely etched away to obtain the pressure-sensitive diaphragm. Bonding step: The pressure-sensitive diaphragm is vacuum bonded to the substrate to form a high-temperature pressure sensing chip with a vacuum reference cavity.

2. The chip according to claim 1, characterized in that, The manufacturing steps of the force-sensitive resistor are as follows: The shape of a Wheatstone bridge force-sensitive resistor is photolithographically etched on the upper surface of a single-crystal silicon wafer. P-type ion implantation is then performed, the photoresist is removed, and high-temperature annealing is carried out to form a p-type force-sensitive resistor with a uniform impurity concentration distribution along the depth direction.

3. The chip according to claim 2, characterized in that, After annealing, the doping concentration of the force-sensitive resistor is greater than 3E18cm. -3 .

4. The chip according to claim 1, characterized in that, The insulation isolation steps include: Insulating isolation trench etching step: Photolithography and etching of insulating isolation trenches around the force-sensitive resistor on the upper surface of the single-crystal silicon wafer, wherein the depth of the insulating isolation trenches is greater than or equal to the depth of the force-sensitive resistor; Insulating layer deposition sub-step: depositing a passivation thick film in the insulating isolation trench, on the upper surface of the force-sensitive resistor and on the upper surface of the single crystal silicon wafer, and depositing a passivation layer on the lower surface of the single crystal silicon wafer respectively.

5. The chip according to claim 4, characterized in that, The passivation thick film growth process is as follows: dry oxygen oxidation to generate a dense silicon dioxide thin layer on the surface of the single crystal silicon wafer and the insulating isolation trench; low-pressure chemical vapor deposition to generate a dense silicon dioxide layer or silicon nitride layer that is thicker than the silicon dioxide thin layer on the surface of the single crystal silicon wafer and the insulating isolation trench for insulating filling and covering; grinding and polishing to form a flat and insulating upper surface. The passivation layer is simultaneously deposited on the lower surface of the single-crystal silicon wafer during dry oxidation and low-pressure chemical vapor deposition of silicon dioxide or silicon nitride layers on the upper surface.

6. The chip according to claim 5, characterized in that, In the passivation thick film growth process, before grinding and polishing, according to the performance requirements of the pressure sensing chip, one or more of the following methods are used to continue depositing a thick film on the wafer surface: plasma-enhanced chemical vapor deposition of silicon dioxide, low-pressure chemical vapor deposition of polycrystalline silicon, sputtering or evaporation or electroplating of metal layers.

7. The chip according to claim 1, characterized in that, The high-temperature resistant lead interconnect manufacturing steps include: Ohmic contact window etching step: Photolithography and etching of the insulating layer above the ohmic contact area of ​​the force-sensitive resistor to form the ohmic contact window; The steps for growing lead interconnects are as follows: implanting heavily doped ions into the silicon in the ohmic contact window and annealing; growing refractory metal silicides on the silicon in the ohmic contact window; and growing high-temperature resistant lead interconnects.

8. The chip according to claim 7, characterized in that, The interconnected structure is a titanium / titanium nitride / titanium / copper high-temperature resistant composite electrode structure compatible with copper-tin silicon through-hole technology, or a titanium / titanium nitride / platinum / gold high-temperature resistant composite electrode structure compatible with gold-tin transient liquid phase bonding technology.

9. The chip according to claim 1, characterized in that, The pressure-sensitive diaphragm corrosion step includes the following sub-steps: Window etching step: A passivation layer is photolithographically etched and etched on the lower surface of a single-crystal silicon wafer to form a window; Protective layer application sub-step: Apply a protective layer to the upper surface of the single-crystal silicon wafer; Wet chemical etching sub-step: The lower surface of the single-crystal silicon wafer is anisotropically etched through a window using a wet chemical etching method until the single-crystal silicon layer on the lower surface of the force-sensitive resistor is no longer directly connected through any bulk silicon layer. Protective layer removal sub-step: Remove the passivation layer on the lower surface and the protective layer on the upper surface to obtain a C-type pressure-sensitive diaphragm.

10. A three-dimensional integration method for a high-temperature pressure sensing chip based on a single-crystal silicon wafer as described in any one of claims 1-9, characterized in that, include: The bottom bonding method involves vacuum bonding the open side of the pressure-sensitive diaphragm to the substrate, and then flip-chip bonding it to the silicon adapter board to form a three-dimensional integrated structure with other electronic chips. The top bonding method involves vacuum bonding the non-opening side of the pressure-sensitive diaphragm to the substrate while simultaneously extracting electrical signals based on TSV. The diaphragm is then flip-bonded to a silicon adapter board to form a three-dimensional integrated structure with other electronic chips.

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