Calibration method for on-chip large-scale optical switch array for benes architecture

Abstract

The application provides a calibration method for an on-chip large-scale optical switch array of a Benes architecture, which comprises the following steps: firstly, selecting a target path; then, judging a crosstalk path and minimizing the influence of the crosstalk path; then, scanning the voltage of a next-stage target switch through by the target path, finding the voltage at which the output end detects the strongest light intensity and maintaining the voltage; maintaining the switch state required by the path of all previous-stage switches on the target path, scanning the target switch of the stage, and obtaining the result; finally, replacing the optical path connection, repeating the relevant steps, and completing the calibration of all switches; the method is accurate and reliable in test result, and can improve the overall working performance of the on-chip large-scale optical switch array of the Benes architecture and make the working state more stable, and can be applied to the test of on-chip large-scale optical switch arrays of Benes architectures of various scales, and provides a basic scheme for optoelectronic packaging test, and has a wide application prospect in an optoelectronic interconnection information exchange network.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of on-chip large-scale optical switch array testing, and particularly relates to a calibration method for an on-chip large-scale optical switch array of a Benes architecture. BACKGROUND

[0002] With the increasing demand for data traffic, optical switch array chips capable of inputting optical signals at any port and outputting from any port have attracted widespread attention from academia and industry as important devices for optical switching networks. Silicon-based optoelectronic devices have been widely used in data centers, 5G base stations and cloud processing due to their compact structure, CMOS process compatibility and other characteristics. Silicon-based electro-optical switch arrays have the advantages of small switching delay, high bandwidth utilization efficiency and low operating power consumption, and can be used to enhance the information carrying capacity of data centers, increase data traffic, provide reconfigurable optoelectronic integrated path solutions for short-distance communication networks and metropolitan long-distance communication networks, and improve transmission rate and data capacity while reducing power consumption. The on-chip large-scale optical switch array chip of the Benes architecture needs to be electrically packaged and connected to a printed circuit board (PCB) through wire bonding, and the voltage driving terminals and communication ports of the upper computer are led out through the circuit board to control the optical switch. In the on-chip large-scale optical switch array of the Benes architecture, each optical switch has two working states: a straight-through (Bar) state and a cross (Cross) state, corresponding to two working voltages: a straight-through state voltage and a cross state voltage. Due to the existence of process precision and process error during production, the initial state and working voltage of each optical switch in the array are not the same, and need to be calibrated and tested by scientific methods. In the existing test method, a monitor needs to be introduced in the path to observe the working voltage of the switch, and the present application can complete the calibration of the working voltage of the switch without using a monitor, reducing the size and design complexity of the optical switch array and optimizing the test speed. SUMMARY

[0003] The present application is a calibration method for an on-chip large-scale optical switch array of a Benes architecture.

[0004] The present application is implemented by adopting the following technical solutions:

[0005] The application discloses a calibration method for an on-chip large-scale optical switch array of a Benes architecture, and belongs to the technical field of optical switch arrays. i-j The switch in the switch array is named as S i-j The switch in the switch array is named as S

[0006] Step 1) Calibrating the working voltage of the switch First, a target path is selected, different voltages are applied to each switch in the on-chip large-scale optical switch array of the Benes architecture to adjust the target path, and when the output end of the on-chip large-scale optical switch array of the Benes architecture path detects the strongest light intensity, the working voltage of the switch through which the target path passes is obtained, and the switch through which the target path passes is referred to as a target switch; a group of input and output ports of the on-chip large-scale optical switch array of the Benes architecture is selected, the input and output ports form the input and output ends of the target path, and then the switch connected to the group of input and output ports is the target switch;

[0007] After the optical path and the circuit are connected, two (p+1) level switches connected to the target switch of the p level are respectively applied with a group of voltages with corresponding step values in the voltage range that the switch can withstand, wherein p=1, if the voltage range that the switch can withstand is less than 5V, the step value is 0.01V, and if the voltage range that the switch can withstand is greater than or equal to 5V, the step value is 0.1V; the process of applying the group of voltages with corresponding step values in the voltage range that the switch can withstand to the switch is referred to as "scanning the voltage of the switch"; the target path and the target switch are determined according to the scanning result, and the applied voltage is cancelled after the scanning voltage result is obtained;

[0008] Step 2) The path through another (p+1)th switch is defined as a crosstalk path. After determining the target path and the crosstalk path, the influence of the crosstalk path needs to be minimized before the subsequent test. If p = 1, the voltage of the (p+1)th crosstalk switch is scanned without controlling any target switch in the target path, and the voltage at which the output end detects the weakest light intensity is found and maintained, i.e., the crosstalk switch has the lowest influence on the path at this time, and then step 3) is performed. If p > 1, the voltage of the (p+1)th crosstalk switch is scanned after maintaining the voltage required by the target path of all the previous target switches at the pth level, and the voltage at which the output end detects the weakest light intensity is found and maintained.

[0009] Step 3) The voltage of the (p+1)th target switch through which the target path passes is scanned, and the voltage at which the output end detects the strongest light intensity is found and maintained. The voltage of the pth switch through which the target path passes is scanned, and the voltage at which the output end detects the strongest and weakest light intensity is recorded, i.e., the calibration voltage of the cross or through state of the pth switch.

[0010] Step 4) Let p' = p+1. When p' < 2n-1, the value of p' is brought into p and step 2) is returned. Otherwise, if p' ≥ 2n-1, the calibration voltage of the switch state required by the target path is applied to the (p'-1)th switch through which the target path passes, the voltage of the p'th target switch through which the path passes is scanned, and the voltage at which the output end detects the strongest and weakest light intensity is recorded, i.e., the calibration voltage of the cross or through state of the p'th switch. At this point, the state voltage of all target switches on the target path is calibrated, i.e., when calibrating the switch at the current level, all switches at the previous level in the target path need to be energized to the switch state required by the path, and the state of the switch at the next level in the crosstalk path is adjusted to the weakest light intensity detected by the output end, and then the state of the switch at the next level in the target path is adjusted to the strongest light intensity detected by the output end. Under this condition, the voltage of the switch at the current level through which the target path passes is scanned, and the voltage at which the output end detects the strongest and weakest light intensity is recorded, i.e., the calibration voltage of the cross and through states of the switch at the current level is obtained.

[0011] Step 5) Selecting the path without the calibrated optical switch as the target path, testing the optical switch without the calibrated voltage on the path, according to the characteristics of the Benes architecture, there are N / 2 paths that can pass through non-repeated optical switches to form a path from the input to the output, that is, there are N / 2 optional target paths, replacing the optical path connection to match the input and output ports of the selected target path, setting p' = 1, and bringing the value of p' into p and returning to step 2) to continue testing in the order of steps, and returning to step 2) to continue testing the process repeatedly N / 2-1 times to test all target paths, and the calibrated voltage of all switches can be obtained after the test is completed.

[0012] Further technical solutions are:

[0013] In step 1), due to the cumulative error of the switches in the later stage during manufacturing, when reaching the p+1 stage switch, the two switches in the p+1 stage must receive signals with different strengths, and the two switches have different influences on the target switch in the p stage, so the switch with obvious transmission loss fluctuation and large fluctuation interval of the output detection signal when scanning the switch voltage is selected as the target switch, and the path through the target switch is the target path to increase the accuracy of the test results.

[0014] Compared with the prior art, the beneficial effects of the present application are:

[0015] 1. The method simplifies the design method of the large-scale optical switch array on the Benes architecture chip, which is different from the method of inserting an optoelectronic conversion monitor in the array path during the design of the optical switch array chip to detect the working state of the switch when calibrating the working voltage of the switch. The method does not need to add a monitor during chip design by reasonably planning the test order of the optical switch, which reduces the complexity of the chip path, thus improving the optical transmission efficiency and reducing unnecessary loss.

[0016] 2. The method uses the interference crosstalk path and minimizes the influence of the crosstalk path on the target path through the judgment of the target path and the crosstalk path in step 1), so that the test results are more accurate and reliable, and the working performance of the large-scale optical switch array on the Benes architecture chip is improved as a whole, and the working state is more stable.

[0017] 3. The method is flexible and can be extended to the test of large-scale optical switch arrays on Benes architectures of various scales, providing a reasonable solution for the test of 32x32 Benes architecture large-scale optical switch array, 64x64 Benes architecture large-scale optical switch array and higher scale array.

[0018] In conclusion, the present application provides a scientific and accurate calibration method for large-scale optical switch array on chip for Benes architecture, which provides a basic scheme for optoelectronic package testing and has a broad application prospect in optoelectronic interconnection information exchange network. BRIEF DESCRIPTION OF DRAWINGS

[0019] The present application will be further described below in conjunction with the accompanying drawings:

[0020] Figure 1 The present application provides a flow chart of the calibration method for large-scale optical switch array on chip for Benes architecture.

[0021] Figure 2 The present application provides a structure schematic diagram of the switch array based on the calibration method for large-scale optical switch array on chip for Benes architecture.

[0022] Figure 3 The present application provides a schematic diagram of optical path and circuit construction based on the calibration method for large-scale optical switch array on chip for Benes architecture.

[0023] Figure 4 The present application provides a switch calibration voltage of the switch array of the embodiment.

[0024] Figure 5 The present application provides an output O1 channel spectrum diagram of the switch array of the embodiment after modulation.

[0025] Figure 6 The present application provides an output O2 channel spectrum diagram of the switch array of the embodiment after modulation.

[0026] Figure 7 The present application provides an output O3 channel spectrum diagram of the switch array of the embodiment after modulation.

[0027] Figure 8 The present application provides an output O4 channel spectrum diagram of the switch array of the embodiment after modulation.

[0028] The present application will be further described below in conjunction with the accompanying drawings:

[0029] To solve the problems raised in the background art, the present application provides a calibration method for large-scale optical switch array on chip for Benes architecture. Benes architecture is a reconfigurable non-blocking form of planar multi-path multi-stage interconnection network architecture, and N×N Benes switch array has N inputs and N outputs, a total of 2n-1 stages, wherein n=log2N. The switches in the column close to the output port are defined as the first stage switches, the next column is defined as the second stage switches, and the last stage is the 2n-1 stage switches; the uppermost switch of each stage is defined as the first switch of the stage, the next row is defined as the second switch of the stage, and the lowermost row is defined as the N / 2th switch of the stage. i-jName the switches in the switch array, where S i-j This represents the j-th switch in the i-th stage. The calibration method for the Benes architecture on-chip large-scale optical switch array described in this invention consists of two parts: the first part is the optical path and circuit construction, and the second part is the switch array test scheme. A simplified flowchart of the calibration method for the Benes architecture on-chip large-scale optical switch array is attached. Figure 1 As shown.

[0030] Optical and electrical circuit construction, such as Figure 3 As shown, the on-chip large-scale optical switch array (HS-OSA) of the Benes architecture requires a tunable laser connected to one input port of the optical switch array. The output port of the HS-OSA of the Benes architecture is connected to a beam splitter, splitting the output signal light into two paths. One path is connected to an optical power meter, and the optical power received by the power meter can be read in the customized software on the host computer. The other output signal of the beam splitter is connected to a photodetector. A multi-channel voltage output driver board applies voltage to the optical switches in the optical switch array to change their operating state, thus changing the output signal light. The photodetector can display the detected light intensity as current. A data acquisition card collects the voltage applied by the voltage source meter and the current signal output by the photodetector, and the effect of applying different voltages on the output port signal light can be displayed on the host computer. The multi-channel voltage output driver board required for the HS-OSA circuit construction of the Benes architecture is divided into a control section and an output section. The control section consists of a central processing chip and a digital-to-analog converter chip, while the output section consists of multiple sets of amplifier circuits. By programming the FPGA and having the host computer send a signal, the multi-channel voltage output ports can be controlled to output a continuous and stable voltage. The optical switch array is connected to a printed circuit board (PCB) for connection via metal wire bonding. This PCB has voltage drive terminals, which are connected to the output ports of a multi-channel voltage output driver board via DuPont wires. A DC regulated power supply powers the multi-channel voltage output driver board.

[0031] The following specific example further illustrates the calibration method for on-chip large-scale optical switch arrays for the Benes architecture provided by this invention.

[0032] Example 1:

[0033] This example uses a 4×4 Benes architecture on-chip large-scale optical switch array. (See attached...) Figure 2 As shown, the 4×4 Benes architecture on-chip large-scale optical switch array has four input ports and four output ports, with three levels of switches in the path, each level having two switching units.

[0034] Optical and electrical circuit construction: the 1310 nm laser is connected to the input I1 port of the optical switch array, and the output port O1 of the optical switch array is connected to the beam splitter. One of the detected signal lights is connected to the optical power meter, and the other is connected to the photodetector. The photodetector is connected to the upper computer through the data acquisition card to form an optical switch control voltage scanning system. The electrical circuit part is connected to the printed circuit board through wire bonding, and the pins are connected to the multi-channel voltage output drive board through the Dupont line. The multi-channel voltage output drive board is connected to the upper computer through the data acquisition card to form a control system. The multi-channel voltage output drive board can simultaneously apply multiple voltages to maintain the switch state.

[0035] The test steps are as follows:

[0036] Step 1) Array test starts with I1 port as input and O1 port as output receiving end. According to the topology, there are two paths from I1 to O1, which are I1 input to S 3-1 , S 3-1 is adjusted to pass-through state, and light is transmitted to S 2-1 through path ⑤; S 2-1 is adjusted to pass-through state, and light is transmitted to S 1-1 through path ①; S 1-1 is adjusted to pass-through state, and light is output from O1. The second path is I1 input to S 3-1 , S 3-1 is adjusted to cross state, and light is transmitted to S 2-2 through path ⑦; S 2-2 is adjusted to pass-through state, and light is transmitted to S 1-1 through path ②; S 1-1 is adjusted to cross state, and light is output from O1. At this time, p = 1, so the multi-channel voltage output drive board is used to scan the voltage of S 1-1 connected to S 2-1 and the voltage of S 2-2 .

[0037] In this example, the switch type is silicon-based electro-optic Mach-Zehnder switch, and the maximum voltage that the switch can withstand is 4V. Therefore, when scanning the switch voltage, a set of voltages from -1.1V to +1.1V with a step interval of 0.01V is applied. The effect on the output end of the optical path is observed, and the path with obvious transmission loss fluctuation and large fluctuation interval is taken as the target path.

[0038] The test sample in this example obtains the result that S 2-2 has a significant impact, so the second path described above is taken as the target path, i.e. the target path is: input from I1 port to S 3-1 , through path ⑦ to S 2-2 , and then through path ② to S1-1 Finally, the output is from port O1. After obtaining the result of the voltage scan, the applied voltage is canceled.

[0039] Step 2) will pass through S 2-1 The light transmitted along the path is defined as crosstalk, at which point p=1, so without controlling S 1-1 and S 3-1 Scan S under the circumstances 2-1 Find the voltage among the voltages that makes the photodetector detect the weakest light intensity. This voltage is the one that causes S in the crosstalk path to... 2-1 The voltage with the least impact on the target path is selected using a multi-channel voltage output driver board to output S. 2-1 The control voltage is maintained at this voltage, meaning that light will not be input to S through path ⑤ at this time. 1-1 middle.

[0040] Step 3) Scan the voltage of the target switch at level p+1, i.e., scan S. 2-2 Find the voltage that causes the photodetector to detect the strongest light intensity among the voltages in the target path; this voltage is the one that causes S to be detected most strongly. 2-2 The voltage that has the greatest impact on the target path, namely S 2-2 All received signal light is input to S from path ②. 1-1 Using a multi-channel voltage output driver board to supply S 2-2 Apply this voltage, adjust it to this, and S is now... 1-1 All the received light comes from S through path ②. 2-2 Scan S 1-1 The voltage at which the photodetector detects the strongest light intensity is S. 1-1 The voltage at the crossover state; the voltage at which the photodetector detects the weakest light intensity is S. 1-1 Voltage in the direct-flow state. S 1-1 The switching state voltage has been calibrated.

[0041] Step 4) Let p' = p + 1, that is, p' = 2. Determine that p' < 3, so substitute the value of p' into p and return to step 2): Use the multi-channel voltage output driver board to maintain S. 1-1 The voltage applied to S before the crossover state is canceled. 2-2 The voltage; further determine p+1=3, so proceed to step 3): "Scan S" 3-1 Find the voltage that produces the strongest light intensity detected at the output terminal and maintain it at that voltage, meaning that as much light as possible is input to S through path ⑦. 2-2 In the middle. Scan S 2-2 The voltage at which the photodetector detects the strongest light intensity is S. 2-2 The voltage in the direct-on state; the voltage at which the photodetector detects the weakest light intensity is S. 2-2Voltage in the crossover state. S 2-2 The switching state voltage has been calibrated. Let p' = p + 1, i.e., p' = 3. If p' ≥ 2n - 1, then use the multi-channel voltage output driver board to supply voltage to S. 2-2 Apply the pass-through voltage and scan S 3-1 The voltage at which the photodetector detects the strongest light intensity is S. 3-1 The voltage at the crossover state; the voltage at which the photodetector detects the weakest light intensity is S. 3-1 Voltage in the direct-flow state. S 3-1 The switch state voltages have been calibrated. All switches on this path have been calibrated.

[0042] Step 5) Repeat the above steps to test other switches by changing the input port. Reset the multi-channel voltage output driver board, i.e., do not apply modulation voltage to any switch. Select the I4 port input, and select the optical path as: S 3-2 Set to crossover state, light enters S through path ⑥. 2-1 S 2-1 Set to direct mode, light passes through path ③ and is input to S. 1-2 Connect the output to O4. Let p' = 1, substitute the value of p' into p and return to step 2): "After passing through S..." 2-2 The light transmitted along the path is defined as crosstalk, at which point p=1, so without controlling S 1-2 and S 3-2 Scan S under the circumstances 2-2 Find the voltage among the voltages that makes the photodetector detect the weakest light intensity. This voltage is the one that causes S in the crosstalk path to... 2-2 The voltage with the least impact on the target path is selected using a multi-channel voltage output driver board to output S. 2-2 The control voltage is maintained at this voltage, meaning that light will not be input to S through path ④ at this time. 1-2 middle."

[0043] Continue to step 3): "Scan the voltage of the target switch at level p+1, i.e., scan S..." 2-1 Find the voltage that causes the photodetector to detect the strongest light intensity among the voltages in the target path; this voltage is the one that causes S to be detected most strongly. 2-1 The voltage that has the greatest impact on the target path, namely S 2-1 All received signal light is input to S from path ③. 1-2 Using a multi-channel voltage output driver board to supply S 2-1 Apply this voltage, adjust it to this, and S is now... 1-2 All the received light comes from S through path ③. 2-1 .

[0044] Scan S 1-2 The voltage at which the photodetector detects the strongest light intensity is S.1-2 The voltage at the crossover state; the voltage at which the photodetector detects the weakest light intensity is S. 1-2 Voltage in the direct-flow state. S 1-2 The switching state voltage has been calibrated. Proceed to step 4): "Let p' = p + 1, i.e., p' = 2. We determine p' < 3, so we substitute the value of p' into p and return to step 2): 'Use the multi-channel voltage output driver board to maintain S...' 1-2 The voltage applied to S before the crossover state is canceled. 2-1 The voltage'; further determine p+1=3, so proceed to step 3): 'Scan S' 3-2 Find the voltage that produces the strongest light intensity detected at the output and maintain it at that voltage, meaning that as much light as possible is input to S through path ⑥. 2-1 middle.

[0045] Scan S 2-1 The voltage at which the photodetector detects the strongest light intensity is S. 2-1 The voltage in the direct-on state; the voltage at which the photodetector detects the weakest light intensity is S. 2-1 Voltage in the crossover state. S 2-1 The switching state voltage has been calibrated.

[0046] Let p' = p + 1, i.e., p' = 3. If p' ≥ 2n - 1, then use the multi-channel voltage output driver board to supply S. 2-1 Apply the pass-through voltage and scan S 3-2 The voltage at which the photodetector detects the strongest light intensity is S. 3-2 The voltage at the crossover state; the voltage at which the photodetector detects the weakest light intensity is S. 3-2 Voltage in the direct-through state.

[0047] S 3-2 The switch state voltages have been calibrated. All switches on this path have been calibrated. At this point, the cross-connect and through-connect state voltages of all switches have been calibrated.

[0048] Figure 4 The diagram shows the crossover and shoot-through state voltage results of each optical switch in the 4×4 Benes architecture on-chip large-scale optical switch array of this example, obtained after the above steps. To verify the accuracy and reliability of these results and to ensure the switch array operates in a good working state, any signal input terminal can be selected, and voltage adjustment paths can be applied to all optical switches according to the results. Signals are received at all output terminals, and crosstalk is observed. There are multiple combinations of switch states for adjusting the path; one is selected for verification testing. In this example, voltage is applied to all optical switches to adjust them to the crossover state. Figure 5For signal input port I3, output port O1, crosstalk port O2, O3 and O4, the optical power of different wavelength signal light at each output port is shown in the form of loss diagram; Figure 6 For signal input port I4, output port O2, crosstalk port O1, O3 and O4, the optical power of different wavelength signal light at each output port is shown in the form of loss diagram; Figure 7 For signal input port I1, output port O3, crosstalk port O1, O2 and O4, the optical power of different wavelength signal light at each output port is shown in the form of loss diagram; Figure 8 For signal input port I2, output port O4, crosstalk port O1, O2 and O3, the optical power of different wavelength signal light at each output port is shown in the form of loss diagram. It can be seen that the crosstalk of crosstalk port is lower than the signal of signal transmission port, and the optical switch array works well after debugging.

Claims

1. A calibration method for on-chip large-scale optical switch arrays using the Benes architecture. The Benes architecture is a reconfigurable, non-blocking planar multipath, multi-level interconnect network architecture. An N×N Benes switch array has N inputs and N outputs, with a total of 2n-1 levels, where n = log₂N. The column of switches closest to the output port is defined as the first-level switch, the next column as the second-level switch, and so on, with the last level being the 2n-1th level. The topmost switch in each level is defined as the first switch of that level, the next row as the second switch, and so on, with the bottom row being the N / 2th switch of that level. i-j Name the switches in the switch array, where S i-j This represents the j-th switch in the i-th stage, characterized in that... The specific method is as follows: Step 1) Calibrating the switch operating voltage: First, the target path needs to be selected. By applying different voltages to each switch in the Benes architecture on-chip large-scale optical switch array, the target path is turned on. When the output terminal of one path of the Benes architecture on-chip large-scale optical switch array detects the strongest light intensity, the operating voltage of the switch passing through the target path can be obtained. The switch passing through the target path is called the target switch. Select a set of input and output ports of the Benes architecture on-chip large-scale optical switch array. This set of input and output ports constitutes the input and output terminals of the target path. The switch connected to this set of input and output ports is the target switch. After establishing the optical and electrical connections, a set of voltages with corresponding step values ​​within the voltage range that the two p+1 level switches connected to the p-level target switch are applied, where p = 1. If the voltage range that the switch can withstand is less than 5V, the step value is 0.01V; if the voltage range that the switch can withstand is greater than or equal to 5V, the step value is 0.1V. This process of applying a set of voltages with corresponding step values ​​within the voltage range that a switch can withstand to a switch is called "scanning the voltage of a switch". The target path and target switch are determined based on the scanning results. After obtaining the scanning voltage results, the applied voltage is canceled. Step 2) The path through another p+1 level switch is defined as the crosstalk path. After determining the target path and the crosstalk path, the impact of the crosstalk path needs to be minimized before subsequent testing. If p=1, without controlling any target switch in the target path, scan the voltage of the crosstalk switch of the p+1 level, find the voltage that makes the output terminal detect the weakest light intensity and maintain it at this voltage. That is, at this time, the crosstalk switch has the least impact on the path, and then proceed to step 3). If p>1, maintain the switch state voltage required for the target path of all the previous target switches of the p level, cancel the voltage previously applied to the target switch of the p level and make further judgments: If p+1=2n-1, proceed directly to step 3). If p+1<2n-1, that is, the p+1 level switch is not the last level switch, scan the voltage of the crosstalk switch of the p+1 level, find the voltage that makes the output terminal detect the weakest light intensity and maintain it at this voltage. Step 3) Scan the voltage of the target switch at level p+1 along the target path, find the voltage that makes the output terminal detect the strongest light intensity and maintain this voltage; scan the voltage of the switch at level p along the target path, and record the voltage values ​​that make the output terminal detect the strongest and weakest light intensity, which are the calibration voltages for the cross or through state of this level p switch, respectively. Step 4) Let p' = p+1. When p' < 2n-1, substitute the value of p' into p and return to step 2). Otherwise, if p' ≥ 2n-1, apply the calibration voltage of the target path to the p'-1 level switch. Scan the voltage of the p' level target switch passed by the path and record the voltage values ​​when the output terminal detects the strongest and weakest light intensity. These are the calibration voltages of the cross or through state of this p' level switch, respectively. At this point, the state voltage calibration of all target switches on the target path is complete. That is, when calibrating the switches of this stage, it is necessary to apply voltage to all the switches in the preceding stage of the target path to the required switch state of the path, apply voltage to adjust the state of the next stage switch in the crosstalk path until the output terminal detects the weakest light intensity, and then apply voltage to adjust the state of the next stage switch in the target path until the output terminal detects the strongest light intensity. Under this condition, scan the voltage of the switches of this stage that the target path passes through, and record the voltage values ​​when the output terminal detects the strongest and weakest light intensity. The calibration voltage of the crossover and through states of the switches of this stage can then be obtained. Step 5) Select the path that does not pass through the optical switch whose calibration result has been obtained above as the target path. Test the optical switches on this path whose calibration voltage has not yet been determined. According to the characteristics of the Benes architecture, there are N / 2 paths that can be formed from the input to the output through non-repeating optical switches. There are N / 2 selectable target paths. Change the optical path connection so that the input and output ports match the newly selected target path. Let p' = 1, substitute the value of p' into p, and return to step 2). Then continue to test in the order of steps. Return to step 2) and continue to test. Repeat this process N / 2-1 times to test all target paths. After the test is completed, the calibration voltage of all switches can be obtained.

2. The calibration method for on-chip large-scale optical switch arrays for Benes architecture according to claim 1, characterized in that, In step 1), due to the accumulation of errors generated during the manufacturing of each switch in the subsequent stage, when the two switches in the p+1 stage reach the p+1 stage, the signal strength received by them will inevitably be different. The influence of these two switches on the target switch in the p stage will be different. Therefore, the switch with obvious transmission loss fluctuation and large fluctuation range obtained from the output terminal detection signal when scanning the switch voltage is taken as the target switch, and the path through this target switch is taken as the target path to increase the accuracy of the test results.

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