System and method for adaptive partitioning of quantization bins integrated in an image sensor

Abstract

The application discloses a system and method for adaptive division of quantization intervals integrated in an image sensor, which comprises the following steps: firstly, a single-slope analog-to-digital converter with a fixed slope k1 is used to collect a cell image to obtain a quantization result before a normal cell image is collected; then, a first-order edge detection of the image is realized through an Up-down counter; the edge detection result is fed back to a column-shared configurable slope generator to output two different slopes k2 and k3; finally, the image sensor system normally collects the cell image, the column-shared configurable slope generator outputs the slope k2 for quantization in a background or an unattended gray interval, and the column-shared configurable slope generator outputs the slope k3 for quantization in a cell or an attended gray interval; the application effectively solves the problems of complex system operation and high professional operation requirement caused by the fact that the existing multi-slope analog-to-digital converter cannot adaptively divide quantization intervals according to different cell types.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, specifically relating to a system and method for adaptively dividing quantization intervals integrated into an image sensor. Background Technology

[0002] Lensless microscopy systems offer advantages such as small size, large field of view, and low cost, playing a crucial role in the field of point-of-care cell detection. However, because lensless microscopy systems follow the transmission imaging mechanism, the inability to focus and magnify results in excessively low contrast in the overall cell image.

[0003] Currently, existing methods for improving cell imaging contrast mainly include off-chip digital domain stretching and on-chip analog domain stretching. Off-chip digital domain stretching is simple to implement, but requires a PC or FPGA, increasing cost and lacking portability. On-chip analog domain stretching utilizes a configurable multi-frequency counter to coarsely quantize the background grayscale range and finely quantize the grayscale range of the cells of interest. This increases the quantization accuracy of the cell grayscale range while maintaining the same ADC quantization accuracy, providing higher precision and clearer details for subsequent digital image processing. However, the cell grayscale range changes significantly with variations in the acquisition environment and cell sample. Firstly, because this stretching occurs before the analog-to-digital converter, the slope adjustment points corresponding to the grayscale range must be modified according to the image sensor chip parameters. Secondly, the human intervention requires a high level of operator skill. Therefore, currently, lensless microscopy systems can only process fixed cells or require a large number of registers within the chip to store different adjustment schemes, significantly impacting the market value of lensless microscopy systems. Summary of the Invention

[0004] The purpose of this invention is to provide a system and method for adaptively dividing quantization intervals integrated into an image sensor, effectively solving the problem that existing lensless microscopy systems, when using on-chip analog domain contrast stretching to improve the quantization accuracy of cell grayscale intervals, cannot automatically adjust the slope and divide the quantization intervals. Another objective of this invention is to provide a method for adaptively dividing quantization intervals using the aforementioned system.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] The system for adaptively dividing quantization intervals integrated into an image sensor specifically includes: a column-parallel single-slope analog-to-digital converter, a column-parallel first-order edge detection circuit, a column-shared configurable ramp generator, a column-shared timing circuit, a column-shared 7-bit shift register, a column-shared 8-bit numerical comparator, a column-shared register MAX, and a column-shared register MIN.

[0007] The column-parallel first-order edge detection circuit includes a subtractor, an 8-bit numerical comparator, and four 8-bit registers, namely register MAX_derta. [j] Register MIN_derta [j] Register MAX_data [j] Register MIN_data [j] ;

[0008] The column-shared timing circuit generates the timing control signals for the entire system; the column-parallel single-slope analog-to-digital converter converts the acquired optical signals into digital signals; the column-shared configurable ramp generator generates multi-slope output signals, which, together with the column-parallel single-slope analog-to-digital converter, complete the nonlinear conversion from analog to digital signals; the column-parallel first-order edge detection circuit performs one-dimensional edge detection of the image, specifically performing subtraction calculations on the digital signals of adjacent rows in the column, comparing the subtraction results, storing the maximum and minimum values ​​of the subtraction results for the column, and storing the corresponding digital signals; the column-shared 7-bit shift register and column-shared 8-bit numerical comparator compare the final output results of the column-parallel first-order edge detection circuits for all columns, thereby determining the grayscale division range of the sample.

[0009] A method for adaptively dividing quantization intervals integrated into an image sensor includes the following steps:

[0010] Step 1: The column-shared timing control circuit provides timing for the entire circuit, controlling the image sensor to operate in column-parallel processing with drum exposure. First, the light signal V is read out from the n×n pixel array. [i；j] When changing cell samples, the system enters linear quantization mode. The column-parallel first-order edge detection circuit is initialized with the column sharing a 7-bit shift register. The column-parallel single-slope analog-to-digital converter quantizes the light signal V in the n×n pixel array at a fixed slope k1. [i；j] Linear to digital signal N [i；j] ;

[0011] Step 2: Under the drum exposure method, the light signal V of the n×n pixel array [i；j] Output line by line, outputting the second row of the transformed result N from each column. [2；j] Initially, the column-parallel first-order edge detection circuit begins subtracting adjacent rows, i.e., calculating the difference D. [i；j] =N [i；j] -N [i+1；j] ;

[0012] Step 3: According to D [i；j] Then compare the positive and negative signs, when D [i；j] When it is positive, compare |D using a comparator.[i；j] | with the MAX_derta stored in the register of this column [j] Size, when |D [i；j] |>MAX_derta [j] D [i；j] Write to register MAX_derta [j] In the middle, at the same time, N [i；j] Write to register MAX_data [j] After completing the operation, return to step 2; similarly, when D... [i；j] When it is negative, compare |D| using a comparator. [i；j] | with the MIN_derta stored in the register of this column [j] Size, when |D [i；j] |>MIN_derta [j] D [i；j] Write to register MIN_derta [j] In the middle, at the same time, N [i；j] Write to register MIN_data [j] After completing the operation, return to step 2;

[0013] Step 4: Repeat steps 2 and 3 above until 128 lines of optical signal are acquired and processed;

[0014] Step 5: Compare the differences between columns by using a shared 7-bit shift register and a shared 8-bit value comparator to compare the MAX_derta values ​​of each column sequentially. [1] To MAX_derta [n] The numerical value, when MAX_derta [j+1] >MAX_derta [j] At that time, MAX_data [j+1] Stored in the column shared register MAX; then compare columns MIN_derta sequentially. [1] to MIN_derta [n] The numerical value, when MIN_derta [j+1] >MIN_derta [j] At that time, MIN_derta [j+1] Stored in the column shared register MIN;

[0015] Step 6: Feed back the values ​​stored in the column shared register MAX and column shared register MIN to the column shared timing control circuit, and then the column shared timing control circuit adjusts the column shared configurable ramp generator to generate two different slopes, k2 and k3 respectively;

[0016] Step 7: The image sensor enters non-linear acquisition mode, quantizes at a fixed slope k2 for grayscale values ​​from 0 to MIN, at a fixed slope k3 for grayscale values ​​from MIN to MAX, and at a fixed slope k2 for grayscale values ​​from MAX to 255, and outputs non-linear results.

[0017] Furthermore, the specific implementation of step 2 is as follows:

[0018] The subtraction of adjacent rows begins in the subtractor of the column-parallel first-order edge detection circuit, i.e., the difference D. [i；j] =N [i；j] -N [i+1；j] An up-down counter is used to implement the numerical subtractor function. Unlike conventional up-down counters, the up counter cannot stop while performing subtraction. Therefore, the up and down counters are separated into independent up and down counters. The up counter is 8 bits and the down counter is 9 bits. The up counter counts sequentially starting from 0, while the down counter starts counting in reverse order with the output Up<7:0> of the previous cycle as the initial value. The extra bit, the highest bit, is the sign bit, 0 for positive and 1 for negative. This way, the size relationship between the two numbers does not need to be considered during the subtraction process. It is always Up<7:0> of the previous cycle minus Up<7:0> of the next cycle. A 9-bit counter with a sign bit is used to store the 8-bit subtraction result.

[0019] Compared with the prior art, the beneficial effects of the present invention are: it effectively solves the problem that lensless microscopy imaging systems can only perform contrast stretching processing on fixed cells or need to configure a large number of registers in the chip to store different contrast adjustment schemes, which greatly improves the market value of lensless microscopy imaging systems. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the system structure of the present invention, which integrates adaptive quantization interval division in an image sensor;

[0021] Figure 2 This is a flowchart illustrating the workflow of the method for adaptively dividing quantization intervals integrated into an image sensor according to the present invention.

[0022] Figure 3 A schematic diagram of a column-parallel first-order edge detection circuit integrated into an image sensor for adaptively dividing quantization intervals;

[0023] Figure 4 This is a schematic diagram illustrating the subtraction function implemented using an up-down counter;

[0024] Figure 5 Images of hydroxyl microspheres taken using an optical microscope;

[0025] Figure 6 This is an image of hydroxyl microspheres obtained after nonlinear quantization following adaptive division of the quantization interval by this system.

[0026] In the diagram: 1 - n×n pixel array; 2 - parallel single-slope analog-to-digital converter; 3 - parallel first-order edge detection circuit; 301 - subtractor; 302 - register MAX_derta. [j] ;303 - Register MAX_data [j] ;304 - Register MIN_data [j] ;305 - Register MIN_derta [j] ; 306 - Comparator; 4 - Column shared sequential circuitry; 5 - Column shared 7-bit shift register; 6 - Column shared configurable ramp generator; 7 - Column shared 8-bit numerical comparator; 8 - Column shared register MAX; 9 - Column shared register MIN. Detailed Implementation

[0027] The present invention will now be described in detail with reference to the accompanying drawings, examples, and specific embodiments.

[0028] like Figure 1 As shown, the system for adaptively dividing the quantization interval integrated in the image sensor specifically includes: 2. Column-parallel single-slope analog-to-digital converter, 3. Column-parallel first-order edge detection circuit, 6. Column-shared configurable ramp generator, 4. Column-shared timing circuit, 5. Column-shared 7-bit shift register, 7. Column-shared 8-bit numerical comparator, 8. Column-shared register MAX, and 9. Column-shared register MIN.

[0029] The column-parallel first-order edge detection circuit 3 includes a subtractor 301, an 8-bit numerical comparator 306, and four 8-bit registers, namely registers MAX_derta. [j] 302. Register MIN_derta [j] 305. Register MAX_data [j] 303. Register MIN_data [j] 304;

[0030] The column-shared timing circuit 4 generates the timing control signal for the entire system; the column-parallel single-slope analog-to-digital converter 2 converts the acquired optical signal into a digital signal; the column-shared configurable ramp generator 6 generates a multi-slope output signal, which, together with the column-parallel single-slope analog-to-digital converter 2, completes the nonlinear conversion from analog signal to digital signal; the column-parallel first-order edge detection circuit 3 completes the one-dimensional edge detection of the image, specifically performing the subtraction calculation of the digital signals of adjacent rows in the column, comparing the subtraction results, storing the maximum and minimum values ​​of the subtraction results in the column, and storing the corresponding digital signals; the column-shared 7-bit shift register 5 and the column-shared 8-bit numerical comparator 7 compare the final output results of the column-parallel first-order edge detection circuit 3 for all columns, thereby determining the grayscale division range of the sample.

[0031] like Figure 2 As shown, the system and method for adaptively dividing quantization intervals integrated into an image sensor are implemented according to the following steps:

[0032] Step 1: The column-shared timing control circuit 4 provides timing for the entire circuit, controlling the image sensor to operate in column-parallel processing with drum exposure. First, the light signal V is read from the n×n pixel array 1. [i；j] When changing cell samples, the system first enters linear quantization mode. The column-parallel first-order edge detection circuit 3 and the column-shared 7-bit shift register 5 are initialized. The column-parallel single-slope analog-to-digital converter 2 performs quantization at a fixed slope k1, converting the light signal V in the n×n pixel array 1 into a linear quantization mode. [i；j] Linear to digital signal N [i；j] ;

[0033] Step 2: Under the drum exposure method, the light signal V read from the n×n pixel array 1 [i；j] Output line by line, transforming the result N from the second row of each column. [2；j] Initially, the subtraction of adjacent rows, i.e., the difference D, is performed in the column-parallel first-order edge detection circuit 3. [i；j] =N [i；j] -N [i+1；j] The specific process is as follows: Figure 3 As shown, considering the area limitation of the column-parallel processing circuit, the area of ​​a traditional numerical subtractor does not meet the requirement. Therefore, an up-down counter is used to implement the function of the numerical subtractor 301. Unlike a conventional up-down counter, the up counter cannot stop while performing subtraction, so the up and down counters are separated, i.e., separate up and down counters. Figure 4The diagram illustrates the working principle of an up-down counter for subtraction. The up counter is 8 bits, and the down counter is 9 bits. The up counter counts sequentially starting from 0, while the down counter starts counting in reverse order from the output Up<7:0> of the previous cycle's up counter. The extra bit (the most significant bit) is the sign bit, with 0 for positive and 1 for negative. This eliminates the need to consider the relative size of the two numbers during subtraction; it always involves subtracting the up<7:0> of the next cycle from the previous cycle's up<7:0>. A 9-bit counter with a sign bit is used to store the 8-bit subtraction result.

[0034] Step 3: According to D [i；j] Then compare the positive and negative signs, when D [i；j] When positive, S3 is turned on, and |D is compared through the 8-bit numerical comparator 306. [i；j] | with the column register MAX_derta [j] The size of 302, when |D [i；j] |>MAX_derta [j] When comparator 306 outputs S1 high and S2 low, D... [i；j] Write to register MAX_derta [j] In 302, N will be simultaneously [i；j] Write to register MAX_data [j] In step 303, after completing the operation, return to step 2; when D [i；j] When the value is negative, S4 is turned on, and |D is compared through the 8-bit numerical comparator 306. [i；j] |With the MIN_derta stored in this column register [j] The size of 305, when |D [i；j] |>MIN_derta [j] When comparator 306 outputs S1 low and S2 high, it will convert D... [i；j] Write to register MIN_derta [j] In 305, N will be simultaneously [i；j] Write to register MIN_data [j] In error 304, after completing the operation, return to step 2;

[0035] Step 4: Repeat steps 2 and 3 above until 128 lines of optical signal are acquired and processed;

[0036] Step 5: Compare the differences between columns, and sequentially select the MAX_derta values ​​of the two columns using the shared 7-bit shift register 5. [j] The value of 302 is then compared with the two columns MAX_derta using the column-shared 8-bit value comparator 7. [j]The size 302 is achieved by using a column-shared 7-bit shift register 5 and a column-shared 8-bit value comparator 7 to implement MAX_derta. [1] To MAX_derta [n] Comparison of numerical values, when MAX_derta [j+1] >MAX_derta [j] At that time, MAX_data [j+1] Stored in the column shared register MAX8; then compare each column MIN_derta sequentially. [j] 302, which is MIN_derta [1] to MIN_derta [n] The numerical value, when MIN_derta [j+1] >MIN_derta [j] At that time, MIN_derta [j+1] Stored in column shared register MIN9;

[0037] Step 6: Feed back the values ​​stored in column shared registers MAX8 and MIN9 to column shared timing control circuit 4, and then column shared timing control circuit 4 adjusts column shared configurable ramp generator 6 to generate two different slopes, k2 and k3 respectively;

[0038] Step 7: The image sensor enters non-linear acquisition mode, quantizes at a fixed slope k2 for grayscale values ​​from 0 to MIN, at a fixed slope k3 for grayscale values ​​from MIN to MAX, and at a fixed slope k2 for grayscale values ​​from MAX to 255, and outputs non-linear results.

[0039] The system proposed in this invention is based on an existing image sensor capable of nonlinear quantization. On this basis, it achieves adaptive division of quantization intervals and adaptive quantization accuracy in different regions, thereby improving the imaging quality of the target object. This system only needs to be activated when updating the sample.

[0040] Figure 5 This is a grayscale image of hydroxyl microspheres taken with an optical microscope. The image has a resolution of 512×128 pixels and a quantization precision of 8 bits. Figure 6 The image shows hydroxyl microspheres obtained after nonlinear quantization following adaptive division of the quantization interval by this system. It can be seen that the quality of the cell portion in the image is significantly improved, while the accuracy of the background portion is significantly reduced.

[0041] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. A system for adaptively dividing quantization intervals integrated into an image sensor, characterized in that, Specifically, it includes: Column-parallel single-slope analog-to-digital converter, column-parallel first-order edge detection circuit, column-shared configurable ramp generator, column-shared timing circuit, column-shared 7-bit shift register, column-shared 8-bit numerical comparator, column-shared register MAX, column-shared register MIN; The column-parallel first-order edge detection circuit includes a subtractor, an 8-bit numerical comparator, and four 8-bit registers, namely register MAX_derta. [j] Register MIN_derta [j] Register MAX_data [j] Register MIN_data [j] ; The column-shared timing circuit generates the timing control signals for the entire system; the column-parallel single-slope analog-to-digital converter converts the acquired optical signals into digital signals; the column-shared configurable ramp generator generates multi-slope output signals, which, together with the column-parallel single-slope analog-to-digital converter, complete the nonlinear conversion from analog to digital signals; the column-parallel first-order edge detection circuit performs one-dimensional edge detection of the image, specifically performing subtraction calculations on the digital signals of adjacent rows in the column, comparing the subtraction results, storing the maximum and minimum values ​​of the subtraction results for the column, and storing the corresponding digital signals; the column-shared 7-bit shift register and column-shared 8-bit numerical comparator compare the final output results of the column-parallel first-order edge detection circuits for all columns, thereby determining the grayscale division range of the sample.

2. A method for adaptively dividing quantization intervals integrated into an image sensor, characterized by comprising the following steps: Step 1: The column-shared timing control circuit provides timing for the entire circuit, controlling the image sensor to operate in column-parallel processing with drum exposure. First, the light signal V is read out from the n×n pixel array. [i;j] When changing cell samples, the system enters linear quantization mode. The column-parallel first-order edge detection circuit is initialized with the columns sharing a 7-bit shift register. The column-parallel single-slope analog-to-digital converter quantizes the light signal V in the n×n pixel array at a fixed slope k1. [i;j] Linear to digital signal N [i;j] ; Step 2: Under the drum exposure method, the light signal V read from the n×n pixel array [i;j] Output line by line, outputting the second row of the transformed result N from each column. [2;j] Initially, the column-parallel first-order edge detection circuit begins subtracting adjacent rows, i.e., calculating the difference D. [i;j] =N [i;j] -N [i+1;j] ; Step 3: According to D [i;j] Then compare the positive and negative signs, when D [i;j] When it is positive, compare |D using a comparator. [i;j] | with the MAX_derta stored in the register of this column [j] Size, when |D [i;j] |>MAX_derta [j] D [i;j] Write to register MAX_derta [j] In the middle, at the same time, N [i;j] Write to register MAX_data [j] After completing the operation, return to step 2; similarly, when D... [i;j] When it is negative, compare |D| using a comparator. [i;j] | with the MIN_derta stored in the register of this column [j] Size, when |D [i;j] |>MIN_derta [j] D [i;j] Write to register MIN_derta [j] In the middle, at the same time, N [i;j] Write to register MIN_data [j] After completing the operation, return to step 2; Step 4: Repeat steps 2 and 3 above until 128 lines of optical signal are acquired and processed; Step 5: Compare the differences between columns by using a shared 7-bit shift register and a shared 8-bit value comparator to compare the MAX_derta values ​​of each column sequentially. [1] To MAX_derta [n] The numerical value, when MAX_derta [j+1] >MAX_derta [j] At that time, MAX_data [j+1] Stored in the column shared register MAX; then compare columns MIN_derta sequentially. [1] to MIN_derta [n] The numerical value, when MIN_derta [j+1] >MIN_derta [j] At that time, MIN_derta [j+1] Stored in the column shared register MIN; Step 6: Feed back the values ​​stored in the column shared register MAX and column shared register MIN to the column shared timing control circuit, and then the column shared timing control circuit adjusts the column shared configurable ramp generator to generate two different slopes, k2 and k3 respectively; Step 7: The image sensor enters non-linear acquisition mode, quantizes at a fixed slope k2 for grayscale values ​​from 0 to MIN, at a fixed slope k3 for grayscale values ​​from MIN to MAX, and at a fixed slope k2 for grayscale values ​​from MAX to 255, and outputs non-linear results.

3. The method for adaptively dividing quantization intervals integrated in an image sensor according to claim 2, characterized in that, The specific steps of step 2 are as follows: The subtraction of adjacent rows begins in the subtractor of the column-parallel first-order edge detection circuit, i.e., the difference D. [i;j] =N [i;j] -N [i+1;j] An up-down counter is used to implement the numerical subtractor function. Unlike conventional up-down counters, the up counter cannot stop while performing subtraction, so the up and down counters are separated into separate up and down counters. The up counter is 8 bits and the down counter is 9 bits. The up counter counts sequentially starting from 0, while the down counter starts counting in reverse order with the output Up<7:0> of the previous cycle's up counter as the initial value. The extra bit, the highest bit, is the sign bit, 0 for positive and 1 for negative. This way, the size relationship between the two numbers does not need to be considered during the subtraction process. It is always Up<7:0> of the previous cycle minus Up<7:0> of the next cycle. A 9-bit counter with a sign bit is used to store the 8-bit subtraction result.

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