Method for detecting a memory

Abstract

The embodiment of the present disclosure provides a memory detection method, which relates to the technical field of semiconductors, and comprises the following steps: writing first storage data into all storage units of a memory; reading the first storage data of each storage unit in a first reading sequence, and then writing second storage data into the storage unit, so that the storage data of adjacent storage units is different; shortening the precharge time of a bit line and a reference bit line connected to the storage unit; and if the storage data of a next storage unit is different from the first storage data, proving that the first preset time when an error occurs is the precharge time corresponding to the memory. Thus, the precharge time of different memories can be tested to divide the advantages and disadvantages of the memories.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for detecting memory. Background Technology

[0002] In Dynamic Random Access Memory (DRAM), the memory array consists of multiple banks, and each bank consists of multiple repeating cells. When data needs to be read from a cell, the cell must first be addressed. Typically, a word line is selected to activate it. Then, the bit line connected to the cell on that word line is opened, and the voltage difference between the bit line and the reference bit line is amplified by an inductive amplifier (SA). This voltage difference is then transmitted to the I / O line to complete the memory read operation. After closing the word line and before opening another word line, a precharge operation is required for the bit line and the reference bit line to bring their potentials back to the same reference value. This ensures the authenticity of the data stored in the cell connected to the other bit line. Therefore, the precharge time directly affects the quality of the memory. However, there is no effective means in related technologies to detect the memory precharge time. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a method for testing a memory, which is used to test the precharge time of the memory.

[0004] This disclosure provides a method for detecting a memory, the memory including multiple memory banks, each memory bank including multiple memory cells arranged in a rectangular array, wherein the detection method includes the following steps:

[0005] Step a: Write the first stored data to all storage cells of the memory;

[0006] Step b: Read the first storage data of each storage cell according to the first reading order. After reading each storage cell, write the second storage data to the storage cell. The second storage data is different from the first storage data. Precharge the bit line and the reference bit line connected to the storage cell for a first preset time. The first preset time is less than the precharge time. Then, read the storage data of the next storage cell and determine whether the storage data of the next storage cell is the same as the first storage data.

[0007] In some embodiments, after the step of reading the first stored data of each of the storage cells in a first read order, the method further includes:

[0008] Step c: Read the second storage data of each storage unit according to the second reading order. After reading each storage unit, write the first storage data to the storage unit and precharge the bit line and the reference bit line connected to the storage unit for a first preset time. The first preset time is less than the precharge time. Then read the storage data of the next storage unit and determine whether the storage data of the next storage unit read is the same as the second storage data.

[0009] The second reading order is the reverse of the first reading order.

[0010] In some embodiments, after step c, the method further includes:

[0011] If the data stored in the next storage unit is the same as the first storage data when read in the first reading order, and the data stored in the next storage unit is the same as the second storage data when read in the second reading order, the value of the first preset time in step b is gradually shortened, and steps b and c are repeated until the data stored in the next storage unit is different from the first storage data when read in the first reading order or different from the second storage data when read in the second reading order.

[0012] In some embodiments, after step a and before step b, the detection method further includes: reducing the equalization voltage of the memory.

[0013] In some embodiments, after step a and before step b, the detection method further includes: writing a first voltage to each of the memory cells, the first voltage being less than the turn-on voltage of the word lines in the memory cells.

[0014] In some embodiments, a second voltage is written to each of the memory banks, the second voltage being greater than the turn-off voltage of the transistors connected to word lines in the memory banks.

[0015] In some embodiments, the memory further includes an equalizer unit disposed between the bit line and the reference bit line;

[0016] The equalization voltage is applied to the bit line and the reference bit line through the equalizer unit.

[0017] In some embodiments, the equalizer unit includes a first transistor, a second transistor, and a third transistor;

[0018] The gates of the first transistor, the second transistor, and the third transistor are connected;

[0019] The source of the first transistor is connected to the bit line, and the drain of the first transistor is connected to the reference bit line.

[0020] The source of the second transistor is connected to the bit line, and the drain of the second transistor is connected to the source of the third transistor.

[0021] The drain of the third transistor is connected to the reference bit line.

[0022] In some embodiments, the equalizer unit further includes a first signal line, which is connected to the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor, respectively. The first signal line is used to provide voltage to the equalizer unit to turn the equalizer unit on or off.

[0023] In some embodiments, the drain of the second transistor and the source of the third transistor are also connected to a second signal line, which is used to provide a reset voltage to the bit line and the reference bit line.

[0024] In some embodiments, the memory includes a read circuit and peripheral circuitry, the read circuit being connected to the bit line and used to transmit the memory data connected to the bit line to the peripheral circuitry.

[0025] In some embodiments, the readout circuit includes: a readout transistor, the gate of which is connected to a third signal line, the third signal line being used to control the readout transistor to be turned on or off;

[0026] The source of the read transistor is connected to the bit line, and the drain of the read transistor is connected to the peripheral circuit.

[0027] In some embodiments, the drain of the read transistor is connected to the peripheral circuit via a fourth signal line.

[0028] In some embodiments, the memory further includes a sensing amplifier disposed between the bit line and the corresponding reference bit line, for amplifying the voltage difference between the bit line and the corresponding reference bit line.

[0029] In some embodiments, the sensing amplifier includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0030] The gate of the fourth transistor is connected to the reference bit line, and the source of the fourth transistor is connected to the bit line.

[0031] The gate of the fifth transistor is connected to the bit line, the source of the fifth transistor is connected to the reference bit line, the drain of the fifth transistor is connected to the drain of the fourth transistor, and is connected to the first power line, which is used to provide a low potential voltage.

[0032] The gate of the sixth transistor is connected to the reference bit line, and the source of the sixth transistor is connected to the bit line.

[0033] The gate of the seventh transistor is connected to the bit line, the source of the seventh transistor is connected to the reference bit line, the drain of the seventh transistor is connected to the drain of the sixth transistor, and is connected to the second power line, which is used to provide a high potential voltage.

[0034] In some embodiments, the fourth transistor and the fifth transistor are both N-type transistors, and the sixth transistor and the seventh transistor are both P-type transistors.

[0035] In the memory detection method provided in this embodiment, the equalization voltage of the memory is reduced. Knowing that this will increase the time required for both the potential of the bit lines and the potential of the reference bit lines to be reset to the reference potential, and after sequentially reading the first stored data of each memory cell according to the first read order, the second stored data of that memory cell is written backwards, making the stored data of adjacent memory cells different. Then, the pre-charge time of the bit lines and reference bit lines connected to that memory cell is shortened to increase the probability of an error when reading the next memory cell. If the stored data of the next memory cell is different from the first stored data, then the first preset time for an error is the pre-charge time corresponding to that memory. This setting allows for testing the pre-charge time of different memories, distinguishing between good and bad memories, and meeting the performance requirements of different users.

[0036] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the memory detection method provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the distribution of memory banks in a memory provided in an embodiment of the present disclosure;

[0039] Figure 2 This is a schematic diagram of the structure of a storage cell in a memory provided in an embodiment of this disclosure;

[0040] Figure 3 A process flow diagram of the memory detection method provided in the embodiments of this disclosure;

[0041] Figures 4 to 7 A distribution diagram of the first stored data in the memory detection method provided in this embodiment of the present disclosure;

[0042] Figures 8 to 13 A schematic diagram of each stage in step b of the memory detection method provided in this embodiment of the disclosure;

[0043] Figures 14 to 16 A schematic diagram of each stage in step c of the memory detection method provided in the embodiments of this disclosure;

[0044] Figure 17 A timing diagram for reading the next memory cell in the memory detection method provided in this embodiment of the present disclosure;

[0045] Figure 18 A circuit diagram of a memory provided for an embodiment of this disclosure.

[0046] Figure label:

[0047] 100: Memory cell; 110: Memory unit; 111: Transistor; 112: Capacitor; 120: Equalizer unit; 130: First signal line; 140: Second signal line; 150: Third signal line; 160: Fourth signal line. Detailed Implementation

[0048] There is no effective means in related technologies to detect the precharge time of memory, thus making it impossible to distinguish the quality of memory. Based on this, in the embodiments of this disclosure, by reducing the equalization voltage of the memory, and knowing that it will increase the time required for the potential of the bit line and the potential of the reference bit line to be reset to the reference potential, after reading the first stored data of each memory cell according to the first read order, the second stored data of the memory cell is written backwards, so that the stored data of adjacent memory cells are different, and the precharge time of the bit line and the reference bit line connected to the memory cell is shortened, thereby increasing the probability of error when reading the next memory cell. If the stored data of the next memory cell is different from the first stored data, it proves that the first preset time when the error occurs is the precharge time of the memory. In this way, the precharge time of different memories can be tested to distinguish the quality of memory and meet the performance requirements of different users.

[0049] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0050] The memory detection method provided in this disclosure is used to detect the precharge time of the memory, wherein the memory may include a plurality of repeating memory banks 100, and each memory bank 100 includes a plurality of memory cells 110, such as... Figure 1 As shown, multiple storage cells 110 are arranged in a rectangular array. It should be noted that... Figure 1 The diagram shows only a portion of the storage cells in a single memory bank 100, not the entire memory bank 100. This embodiment will use the structure of a single memory bank 100 as an example to illustrate the memory detection method in detail.

[0051] The memory also includes multiple bit lines (BL) and multiple word lines (WL), wherein each memory cell 110 is connected to one bit line (BL) and one word line (WL) respectively, for writing and reading data.

[0052] The memory bit lines are divided into multiple bit line groups, each with 8 bit lines BL. For ease of description below, the bit lines in each bit line group can be denoted as BL0, BL1, BL2...BL7.

[0053] like Figure 1As shown, bit lines BL0 and BL4 are located in the same row. An inductive amplifier SA is positioned between bit lines BL0 and BL4; that is, one end of the inductive amplifier SA is connected to bit line BL0, and the other end is connected to bit line BL4. Among multiple memory cells 110 located in the same row, several memory cells 110 are connected to bit line BL0, and several memory cells 110 are connected to bit line BL4. Figure 1 As shown in the example, there are 8 storage cells 110 in the first row, of which four storage cells 110 are connected to bit line BL0 and the other four storage cells 110 are connected to bit line BL4.

[0054] When it is necessary to read the stored data of the memory cell 110 connected to the bit line BL0, the bit line BL4 needs to be used as the reference bit line. When it is necessary to read the stored data of the memory cell 110 connected to the bit line BL4, the bit line BL0 needs to be used as the reference bit line.

[0055] Similarly, bit lines BL1 and BL5 are in the same row, and there is an inductor amplifier SA between them; bit lines BL2 and BL6 are in the same row, and there is an inductor amplifier SA between them; bit lines BL3 and BL7 are in the same row, and there is an inductor amplifier SA between them.

[0056] like Figure 2 As shown, each memory cell 110 includes a transistor 111 and a capacitor 112. The gate of transistor 111 is connected to the word line WL, the source of transistor 111 is connected to the bit line BL, and the drain of transistor 111 is connected to the capacitor 112. It should be noted that the source of transistor 111 can also be connected to the capacitor 112. Correspondingly, the drain of transistor 111 is connected to the bit line BL.

[0057] In addition, multiple word lines WL are arranged in columns, and the multiple word lines WL are divided into multiple word line groups. Each word line group has 8 word lines WL. For the convenience of the following description, the word lines in each word line group can be referred to as WL0, WL1, WL2...WL7. Each word line is connected to the storage unit 110 located in the same column.

[0058] like Figure 3 As shown, the memory detection method includes the following steps:

[0059] Step a: Write the first stored data to all storage cells in the memory.

[0060] For example, the storage unit 110 is first initialized to activate the storage unit 110, and then a write operation is performed to write first stored data into the storage unit 110, wherein the first stored data in adjacent rows may be the same or different.

[0061] In one example, such as Figure 4 and Figure 5 As shown, the first stored data in adjacent rows can be the same; for example, the first stored data can be all "1" or all "0".

[0062] In another example, such as Figure 6 and Figure 7 As shown, the first stored data in adjacent rows can be different, for example, such as Figure 6 As shown, the first stored data in storage cell 110 in the first row is "1", and the first stored data in storage cell 110 in the second row is "0"; for example, as... Figure 7 As shown, the first stored data in the storage cell 110 in the first row is "0", and the first stored data in the storage cell 110 in the second row is "1".

[0063] After writing the first stored data to all memory cells, the equalization voltage of the memory is reduced to create a relatively poor experimental environment for the memory. Consequently, the time required for both the potential of the bit line and the potential of the reference bit line to be reset to the reference potential will increase. However, determining the accurate value of the time required for both the potential of the bit line and the potential of the reference bit line to be reset to the reference potential has become a current challenge.

[0064] Based on the aforementioned difficulties, the embodiments of this disclosure perform the following detection operations, which can accurately determine the precharge time of the memory.

[0065] Step b: Read the first storage data of each storage cell 110 according to the first reading order. Then, write the second storage data to the storage cell. The second storage data is different from the first storage data. Perform a first preset time pre-charge on the bit line and reference bit line connected to the storage cell. The first preset time is less than the pre-charge time. Then, read the storage data of the next storage cell and determine whether the storage data of the next storage cell is the same as the first storage data.

[0066] The first reading order can be understood as reading the first stored data of the first row of storage cells in the direction from the first storage cell to the last storage cell in each row, then reading the first stored data of the next row of storage cells, and so on, until the first stored data of the last row of storage cells has been read. To facilitate the description of the memory detection method, let's take the case where the first stored data in adjacent rows is the same and the first stored data is "0" as an example. The stored data of each storage cell 110 can be as follows: Figure 5 As shown.

[0067] After all the first storage data has been written to each storage unit 110, the first storage data of each storage unit 110 is read in the first reading order. After each storage unit 110 is read, the second storage data is written to that storage unit 110. The first storage data and the second storage data are different.

[0068] For example, such as Figures 8 to 13 As shown, when reading the stored data of each memory cell 110 connected to bit line BL0, bit line BL4 can be used as the reference bit line / BL.

[0069] Along the first direction X, that is, the direction from the first storage cell 110 to the last storage cell 110 in each row, the first storage data of each storage cell 110 connected to it is read sequentially using bit line BL0, and the second storage data is written backward. Before reading the remaining storage cells 110 except for the first storage cell 110, bit line BL0 and bit line BL4 need to be precharged for a first preset time. The first preset time is less than the precharge time, which makes it difficult for bit line BL0 and bit line BL4 to return to the same reference potential value, increasing the probability of error when reading the first storage data on the second to fourth storage cells 110 connected to bit line BL0.

[0070] For example, to read Figure 8 Taking the data in the memory cell connected to the first bit line BL0 as an example, during normal reading, such as Figure 17 As shown in (a), typically, word line WL0 is first enabled, and the actual stored data "0" of the first memory cell 110 is read using bit line BL0. Then, the second stored data "1" is written back to the first memory cell 110. At this time, the potential of bit line BL0 is greater than that of the reference bit line / BL. If the second stored data "1" is written back, and the bit line BL0 and the reference bit line / BL4 are pre-charged normally, the bit line BL0 and the reference bit line / BL4 will return to the same reference potential V. BLP Then, when the bit line BL0 is used to read the stored data of the second storage cell 110, the stored data read from the second storage cell 110 is "0".

[0071] However, in this embodiment, the bit line and the reference bit line are pre-charged for a first preset time, and the first preset time is less than the pre-charge time tRP, such as... Figure 17 As shown in (b), after a pre-charge period of the first preset time, the potential of bit line BL and the potential of reference bit line / BL did not return to the reference potential V. BLP This ensures that the potential of bit line BL is still greater than the potential of reference bit line / BL. Thus, after being amplified by the inductive amplifier, the actual stored data of the second storage cell 110 is "1", which is the opposite of the theoretical first stored data "0".

[0072] Among them, the precharge time is the timing parameter tRP (Row Precharge Time, abbreviated as tRP). tRP is the time between the precharge command (PRE) of the previous word line and the activation command (ACT) of the next word line in DRAM, which is used to characterize the speed at which the DRAM array recovers to the precharge state.

[0073] like Figure 10 As shown, then, along the first direction X, the first storage data of each storage cell 110 connected to it is read sequentially using bit line BL4. At this time, bit line BL0 can be used as a reference bit line / BL. After reading the first storage data of each storage cell 110, the second storage data is written back to the storage cell 110. Before reading the remaining storage cells 110 except for the first storage cell 110 located after the inductive amplifier SA, bit line BL0 and bit line BL4 need to be pre-charged for a first preset time. The first preset time is less than the pre-charge time, making it difficult for bit line BL0 and bit line BL4 to return to the same reference potential value, which increases the probability of error when reading the first storage data on the second to fourth storage cells 110 connected to bit line BL4.

[0074] Following this pattern, along the first direction, the first stored data in each storage unit 110 in the second, third, and fourth rows is read sequentially, and the second stored data is written backwards. When reading the stored data in the next storage unit 110, the bit line and reference bit line connected to the storage unit 110 are pre-charged for a first preset time, which is less than the pre-charge time.

[0075] In this embodiment, by writing the second storage data "1" to the previous storage cell, the potential on the bit line BL is made higher than the potential of the reference bit line / BL, and the first preset time is less than the pre-charge time, thereby creating an error probability of reading the storage data of the next storage cell 110. If the storage data of the next storage cell 110 is different from the first storage data "0", it proves that the first preset time when the error occurs is the pre-charge time corresponding to the memory.

[0076] If the stored data of the next storage unit 110 is the same as the first stored data "0", the value of the first preset time needs to be reset so that the value of the first preset time is less than the first preset time when it was read for the first time. Step b is repeated until the stored data of the next storage unit 110 is different from the first stored data "0". This proves that the first preset time when the error occurred is the precharge time corresponding to the memory.

[0077] In this embodiment, the equalization voltage of the memory is reduced. Knowing that this increases the time required for both the bit line potential and the reference bit line potential to reset to the reference potential, and after sequentially reading the first stored data of each memory cell in the first read order, the second stored data of that memory cell is written backwards, making the stored data in adjacent memory cells different. Then, the pre-charge time of the bit line and reference bit line connected to that memory cell is shortened to increase the probability of errors when reading the next memory cell. If the stored data of the next memory cell is different from the first stored data, then the first preset time for an error is the pre-charge time corresponding to that memory. This setting allows for testing the pre-charge time of different memories to differentiate their performance and meet the performance requirements of different users.

[0078] In some embodiments, such as Figure 14 As shown, the second storage data of each storage cell is read in the second reading order. After each storage cell is read, the first storage data is written to the storage cell, and the bit line and reference bit line connected to the storage cell are precharged for a first preset time. The first preset time is less than the precharge time. The storage data of the next storage cell is read, and it is determined whether the storage data of the next storage cell is the same as the second storage data. The second reading order is the reverse of the first reading order.

[0079] In this embodiment, the second reading order can be understood as follows: following the direction from the last storage cell to the first storage cell in each row, after reading the first storage data of the last storage cell, the first storage data of the previous storage cell is read, and so on, until the first storage data of the first storage cell in the first row is read.

[0080] For example, such as Figure 14As shown, first, the second storage data "1" of each storage cell connected to bit line BL7 is read. At this time, BL3 can be used as the reference bit line / BL.

[0081] Along the second direction Y, that is, the direction from the last storage cell 110 to the first storage cell 110 in each row, the second storage data "1" of each storage cell 110 connected to it is read sequentially using bit line BL7, and the first storage data "0" is written backwards. Before reading the remaining storage cells 110 except the last storage cell 110, bit line BL7 and bit line BL3 need to be precharged for a first preset time. The first preset time is less than the precharge time, which makes it difficult for bit line BL7 and bit line BL3 to return to the same reference potential value, increasing the probability of error when reading the first storage data on the penultimate storage cell 110 connected to bit line BL7.

[0082] Then, along the second direction, such as Figure 15 As shown, the second storage data "1" of each storage cell connected to bit line BL3 is read. At this time, bit line BL0 can be used as reference bit line / BL. After reading the first storage data of each storage cell 110, the first storage data "0" is written back to the storage cell 110.

[0083] In this way, urge, such as Figure 16 As shown, along the second direction, the second stored data "1" in each storage unit 110 of the third row, the second row, and the first row is read sequentially, and the second stored data "0" is written backwards. The data distribution diagram can be further referenced. Figure 5 .

[0084] When reading the stored data of each storage cell in the first reading order, when reading the first stored data of the first storage cell 110 connected to each bit line along the first direction, since there is no storage cell in front of it, the stored data of the first storage cell 110 connected to each bit line will always be "0" and no error will occur. Therefore, based on the consideration of improving the accuracy of the detection method, this embodiment also performs reverse reading. This setting provides each storage cell with an opportunity to make an error, thereby improving the accuracy of the detection method.

[0085] It should be noted that when reading the stored data of each storage unit in the second reading order, if the stored data of the next storage unit 110 is the same as the second stored data "1", the value of the first preset time needs to be reset so that the value of the first preset time is less than the value of the first preset time during the first reading, and step c is repeated until the stored data of the next storage unit 110 is different from the first stored data "1", then it is proven that the first preset time when the error occurred is the precharge time corresponding to the memory.

[0086] In some embodiments, after step a and before step b, the memory detection method includes:

[0087] A first voltage is written into each memory bank 100. The first voltage is less than the turn-on voltage Vpp of the word line WL in the memory bank 100. When reading the stored data of the memory cell 110 connected to a certain word line, the turn-on degree of the transistor connected to that word line is reduced. When reading 1 or 0, during the charge sharing stage, the ΔV of the bit line BL will decrease, making the SASensing margin boundary too small, causing the sensing amplifier SA data to flip incorrectly, and making it easy to read incorrectly.

[0088] In some embodiments, a second voltage is written to each memory bank 100, the second voltage being greater than the turn-off voltage Vkk of the word line in the memory bank 100.

[0089] This configuration reduces the degree of transistor shutdown connected to the word line, causing data stored in the memory cell connected to that word line to leak onto the bit line BL, affecting ΔV on the bit line BL. When reading the stored data of the memory cell connected to the next word line adjacent to that word line, it will cause a data flip error in the sensing amplifier SA, making it easy to read incorrectly.

[0090] For example, refer to Figure 8 and Figure 17 (b) When the second voltage applied to word line WL0 is greater than the turn-off voltage, the turn-off degree of the transistor is weakened, which causes the capacitor to leak current to the bit line BL0 connected to the memory cell 10, thereby causing the charge of the memory cell connected to word line WL0 to still be transferred to the bit line BL0, so as to achieve the purpose of the potential of bit line BL0 being greater than the potential on the reference bit line / BL4.

[0091] When word line WL1 is reopened, since word line WL1 and word line WL0 share a set of bit lines and a reference bit line, when reading data from the memory cell connected to word line WL1, the potential of bit line BL is still greater than the potential on the reference bit line / BL. After the potential difference between bit line BL and reference bit line / BL is amplified by the inductive amplifier SA, the stored data read from the memory cell 110 connected to word line WL1 is "1", which is opposite to the first stored data "0" of the memory cell 110. This proves that the first preset time when an error occurs is the precharge time corresponding to the memory.

[0092] It should be noted that after the memory structure is fabricated, the memory needs to be designed for test (DFT). Therefore, test circuits are set in the peripheral circuit area of ​​the memory. In the actual testing process, the test circuits can be activated and a first voltage and a second voltage can be applied to each memory cell.

[0093] In some embodiments, such as Figure 18 As shown, the memory also includes an equalizer unit 120 disposed between the bit line BL and the reference bit line / BL, through which an equalizer voltage is applied to the bit line BL and the reference bit line / BL.

[0094] The equalizer unit 120 includes a first transistor P1, a second transistor P2, and a third transistor P3 disposed between the bit line BL and the reference bit line / BL.

[0095] The gates of the first transistor P1, the second transistor P2, and the third transistor P3 are connected and connected to the first signal line 130. The first signal line 130 is used to provide voltage to the equalizer unit 120 to turn the equalizer unit 120 on or off. That is, the first signal line 130 is used to provide a high level or a low level to the gates of the first transistor P1, the second transistor P2, and the third transistor P3 to turn the aforementioned transistors on or off.

[0096] The source of the first transistor P1 is connected to the bit line BL, and the drain of the first transistor P1 is connected to the reference bit line / BL.

[0097] The source of the second transistor P2 is connected to the bit line BL, and the drain of the second transistor P2 is connected to the source of the third transistor P3.

[0098] The drain of the third transistor P3 is connected to the reference bit line / BL. The drain of the second transistor P2 and the source of the third transistor P3 are also connected to the second signal line 140. The second signal line 140 is used to provide a reset voltage to the bit line BL and the reference bit line / BL. The second signal line 140 is connected to the external circuit and is used to provide a reset voltage V to the bit line BL and the reference bit line / BL. BLP .

[0099] In some embodiments, continue to refer to Figure 18 The memory includes a read circuit and peripheral circuitry (not shown in the figure). The read circuit is connected to the bit lines. The read circuit is activated to transfer the stored data of the memory cells connected to the bit lines to the peripheral circuitry.

[0100] For example, the read circuit includes: a read transistor YSW, the gate of the read transistor YSW is connected to a third signal line 150, the third signal line 150 is used to control the read transistor YSW to be turned on or off; the source of the read transistor YSW is connected to a bit line BL, and the drain of the read transistor YSW is connected to a peripheral circuit, wherein a fourth signal line 160 is provided between the drain of the read transistor YSW and the peripheral circuit.

[0101] When the potential of the third signal line 150 is high, the read transistor YSW is turned on, and the source and drain of the read transistor YSW are connected, so that the potential on the bit line BL is transmitted to the peripheral circuit through the fourth signal line 160, and then the peripheral circuit is used to read the potential on the bit line BL.

[0102] In some embodiments, in order to improve the accuracy of data reading from the memory, an inductive amplifier SA is typically provided in the memory. The inductive amplifier SA is located between the bit line BL and the reference bit line / BL corresponding to the bit line BL. One end of the inductive amplifier SA is connected to the bit line BL and the other end is connected to the reference bit line / BL, and it is used to amplify the voltage difference between the bit line BL and the reference bit line / BL corresponding to the bit line BL.

[0103] For example, the inductive amplifier SA includes a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, and a seventh transistor P7.

[0104] The gate of the fourth transistor P4 is connected to the reference bit line / BL, and the source of the fourth transistor P4 is connected to the bit line BL.

[0105] The gate of the fifth transistor P5 is connected to the bit line BL, the source of the fifth transistor P5 is connected to the reference bit line / BL, the drain of the fifth transistor P5 is connected to the drain of the fourth transistor P4, and is connected to the first power line NCS, which is used to provide a low potential voltage.

[0106] The gate of the sixth transistor P6 is connected to the reference bit line / BL, and the source of the sixth transistor P6 is connected to the bit line BL.

[0107] The gate of the seventh transistor P7 is connected to the bit line BL, the source of the seventh transistor P7 is connected to the reference bit line / BL, the drain of the seventh transistor P7 is connected to the drain of the sixth transistor P6, and is connected to the second power supply line PCS, which is used to provide a high potential voltage.

[0108] In this embodiment, the fourth transistor P4 and the fifth transistor P5 are both N-type transistors, and the sixth transistor P6 and the seventh transistor P7 are both P-type transistors.

[0109] In this embodiment, when the data "1" is read using the bit line BL, the sensing amplifier SA can pull the potential on the bit line BL up to the highest potential Vary, while pulling the potential on the reference bit line / BL down to the lowest potential Vss, so as to amplify the voltage difference between the bit line BL and the corresponding reference bit line / BL, which facilitates the reading by the reading circuit.

[0110] When reading the stored data of the memory cell 110 connected to word line WL1 in the first reading order, the main processes include the following: After word line WL0 is closed and reset, the equalizer unit 120 is turned off and word line WL1 is turned on to open the memory cell 110 connected to word line WL1, so that the data in memory cell 110 shares the potential with the bit line BL. Since the potential on bit line BL and the reference bit line / BL are not reset to the reference potential V when word line WL0 is turned on. BLP The potential of bit line BL is still higher than that of the reference bit line / BL. After word line WL1 is turned on, the inductive amplifier SA is turned on. The inductive amplifier SA is used to quickly pull the potential of bit line BL to the highest potential Vary and quickly pull the potential of the reference bit line / BL to the lowest potential Vss, so as to amplify the potential difference between bit line BL and reference bit line / BL. Then the read circuit is turned on, and the data in memory cell 110 is transmitted to the peripheral circuit through the fourth signal line 160 to obtain the data of memory cell 110 connected to word line WL1.

[0111] In this process, this disclosure increases the probability of a read error in the next memory cell adjacent to the memory cell by reducing the precharge time of the bit lines and reference bit lines connected to the memory cell, reducing the turn-on voltage of the word lines connected to the memory cell, and increasing the turn-off voltage of the word lines connected to the memory. This makes it easier to test the precharge time of the memory cell and to screen the quality of the memory.

[0112] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0113] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.

[0114] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for detecting a memory, characterized in that, The memory includes multiple memory banks, and each memory bank includes multiple memory cells arranged in a rectangular array. The detection method includes the following steps: Step a: Write the first stored data to all storage cells of the memory; Step b: Read the first storage data of each storage cell according to the first reading order. After reading each storage cell, write the second storage data to the storage cell. The second storage data is different from the first storage data. Precharge the bit line and reference bit line connected to the storage cell for a first preset time. The first preset time is less than the precharge time. Then, read the storage data of the next storage cell and determine whether the storage data of the next storage cell is the same as the first storage data.

2. The method for detecting a memory according to claim 1, characterized in that, After the step of reading the first stored data of each of the storage cells in the first reading order, the method further includes: Step c: Read the second storage data of each storage unit according to the second reading order. After reading each storage unit, write the first storage data to the storage unit and precharge the bit line and the reference bit line connected to the storage unit for a first preset time. The first preset time is less than the precharge time. Then, read the storage data of the next storage unit and determine whether the storage data of the next storage unit is the same as the second storage data. The second reading order is the reverse of the first reading order.

3. The method for detecting a memory according to claim 2, characterized in that, Following step c, the method further includes: If the data stored in the next storage unit is the same as the first storage data when read in the first reading order, and the data stored in the next storage unit is the same as the second storage data when read in the second reading order, the value of the first preset time in step b is gradually shortened, and steps b and c are repeated until the data stored in the next storage unit is different from the first storage data when read in the first reading order, or the data stored in the next storage unit is different from the second storage data when read in the second reading order.

4. The detection method according to any one of claims 1-3, characterized in that, After step a and before step b, the detection method further includes: reducing the equalization voltage of the memory.

5. The method for detecting a memory according to any one of claims 1-3, characterized in that, After step a and before step b, the detection method further includes: A first voltage is written to each of the memory banks, the first voltage being less than the turn-on voltage of the word line in the memory bank.

6. The method for detecting a memory according to claim 5, characterized in that, A second voltage is written to each of the memory banks, the second voltage being greater than the turn-off voltage of the transistors connected to the word lines in the memory banks.

7. The method for detecting a memory according to claim 4, characterized in that, The memory also includes an equalizer unit disposed between the bit line and the reference bit line; The equalization voltage is applied to the bit line and the reference bit line through the equalizer unit.

8. The method for detecting a memory according to claim 7, characterized in that, The equalizer unit includes a first transistor, a second transistor, and a third transistor; The gates of the first transistor, the second transistor, and the third transistor are connected; The source of the first transistor is connected to the bit line, and the drain of the first transistor is connected to the reference bit line. The source of the second transistor is connected to the bit line, and the drain of the second transistor is connected to the source of the third transistor. The drain of the third transistor is connected to the reference bit line.

9. The method for detecting a memory according to claim 8, characterized in that, The equalizer unit further includes a first signal line, which is connected to the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor, respectively. The first signal line is used to provide voltage to the equalizer unit to turn the equalizer unit on or off.

10. The method for detecting a memory according to claim 9, characterized in that, The drain of the second transistor and the source of the third transistor are also connected to a second signal line, which is used to provide a reset voltage to the bit line and the reference bit line.

11. The method for detecting a memory according to any one of claims 1-3, characterized in that, The memory includes a read circuit and peripheral circuits. The read circuit is connected to the bit line and is used to transmit the storage data connected to the bit line to the peripheral circuits.

12. The method for detecting a memory according to claim 11, characterized in that, The readout circuit includes: a readout transistor, the gate of which is connected to a third signal line, the third signal line being used to control the readout transistor to be turned on or off; The source of the read transistor is connected to the bit line, and the drain of the read transistor is connected to the peripheral circuit.

13. The method for detecting a memory according to claim 12, characterized in that, The drain of the read transistor is connected to the peripheral circuit via a fourth signal line.

14. The method for detecting a memory according to any one of claims 1-3, characterized in that, The memory also includes a sensing amplifier, which is disposed between the bit line and the corresponding reference bit line to amplify the voltage difference between the bit line and the corresponding reference bit line.

15. The method for detecting a memory according to claim 14, characterized in that, The inductive amplifier includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The gate of the fourth transistor is connected to the reference bit line, and the source of the fourth transistor is connected to the bit line. The gate of the fifth transistor is connected to the bit line, the source of the fifth transistor is connected to the reference bit line, the drain of the fifth transistor is connected to the drain of the fourth transistor, and is connected to the first power line, which is used to provide a low potential voltage. The gate of the sixth transistor is connected to the reference bit line, and the source of the sixth transistor is connected to the bit line. The gate of the seventh transistor is connected to the bit line, the source of the seventh transistor is connected to the reference bit line, the drain of the seventh transistor is connected to the drain of the sixth transistor, and is connected to the second power line, which is used to provide a high potential voltage.

16. The method for detecting a memory according to claim 15, characterized in that, The fourth and fifth transistors are both N-type transistors, and the sixth and seventh transistors are both P-type transistors.

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