Gate drive circuit and display device

Abstract

The application discloses a gate driving circuit and a display device. The gate driving circuit comprises a plurality of cascaded gate driving units. Each gate driving unit comprises at least a driving module. An input end of the driving module is connected with a clock signal. The driving module is used for outputting a driving signal corresponding to the clock signal according to a control signal received by a controlled end of the driving module. The gate driving circuit further comprises a control unit. One end of the control unit is connected with the controlled end of the driving module of an Nth gate driving unit. The other end of the control unit is connected with the controlled end of the driving module of an N+Mth gate driving unit. The control unit is used for controlling the controlled end of the Nth driving module to be connected with the controlled end of the N+Mth driving module. The phase of the clock signal connected with the input end of the Nth driving module is opposite to the phase of the clock signal connected with the input end of the N+Mth driving module. Through the above structure, the noise resistance of the gate driving circuit is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display panel, in particular to a gate drive circuit and a display device. BACKGROUND

[0002] Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and has been widely applied, for example, in liquid crystal television, mobile phone, personal digital assistant, digital camera, computer screen or notebook computer screen, etc. Flat panel display has an irreplaceable position.

[0003] GDL (Gate Driver less) technology is to use the original array process of the liquid crystal display panel to manufacture the driving circuit of the horizontal scanning line on the substrate around the display area, so that it can replace the external integrated circuit board to complete the driving of the horizontal scanning line. By using the GDL technology to manufacture the gate driver on the thin film transistor array substrate, the space can be saved, so that the liquid crystal display panel can be more suitable for being manufactured as a narrow frame or frameless display product.

[0004] In the GDL circuit, ideally, the output waveform of each GDL unit should be a single waveform. In fact, due to the existence of parasitic capacitance in the GDL unit circuit, the voltage of the Q point (controlled end) will be coupled by other signals, especially the CLK (clock) signal, which will cause the driving transistor to be turned on in the non-display stage, and the output waveform will be affected. At the same time, because of the existence of the noise reduction TFT in the GDL unit, the output waveform will recover quickly. However, if the noise reduction TFT is not designed well, or the characteristics of the noise reduction TFT are deteriorated after long-term operation of the panel, the noise in the output waveform will be larger, which will affect the display. SUMMARY

[0005] The technical problem solved by the present application is to provide a gate drive circuit and a display device to improve the stability of panel display.

[0006] To solve the above problems, the application provides a gate drive circuit, which comprises a plurality of cascaded gate drive units, each of which comprises at least a drive module, an input end of the drive module is connected with a clock signal, and the drive module is used for outputting a drive signal corresponding to the clock signal according to a control signal received by a controlled end of the drive module, wherein the gate drive circuit further comprises a control unit, one end of the control unit is connected with the controlled end of the drive module of the Nth gate drive unit, and the other end of the control unit is connected with the controlled end of the drive module of the N+Mth gate drive unit, so as to control the controlled end of the Nth drive module to be connected with the controlled end of the N+Mth drive module, wherein the phase of the clock signal connected with the input end of the Nth drive module is opposite to the phase of the clock signal connected with the input end of the N+Mth drive module.

[0007] The control unit controls the controlled end of the Nth drive module to be connected with the controlled end of the N+Mth drive module at a low potential voltage.

[0008] The control unit comprises at least a first transistor, a gate of the first transistor is connected with a first control signal, one of a source and a drain of the first transistor is connected with the controlled end of the drive module of the Nth gate drive unit, and the other of the source and the drain of the first transistor is connected with the controlled end of the drive module of the N+Mth gate drive unit.

[0009] The control unit further comprises a second transistor, a gate of the second transistor is connected with an output end of the N+2Mth gate drive unit, a source of the second transistor is connected with a first voltage signal, and a drain of the second transistor is connected with the gate of the first transistor, so as to control the first transistor to be turned on by the first voltage signal when the N+2Mth gate drive unit is scanned.

[0010] The control unit further comprises a third transistor, a gate of the third transistor is connected with an output end of the N-2Mth gate drive unit, a source of the third transistor is connected with a second voltage signal, and a drain of the third transistor is connected with the gate of the first transistor, so as to control the first transistor to be turned off by the second voltage signal when the N-2Mth gate drive unit is scanned.

[0011] The gate drive unit of each stage further comprises a first control module and a second control module, the first control module of the Nth stage is connected with the driving signal output by the driving module of the N+Hth stage, and is used for inputting a first control signal to the controlled end of the driving module of the Nth stage; the second control module of the Nth stage is connected with the driving signal output by the driving module of the N+Lth stage, and is used for inputting a second control signal to the controlled end of the driving module of the Nth stage; the controlled end of the driving module of the Nth stage is connected with the first control module of the Nth stage and the second control module of the Nth stage respectively, and the input end of the driving module of the Nth stage is connected with the clock signal, and is used for outputting the driving signal according to the clock signal.

[0012] Wherein, M≥H≥1, 2M≥L≥M.

[0013] The gate drive circuit further comprises a reset unit, the reset unit is connected with the gate of the first transistor, and the voltage of the gate of the first transistor is reset before driving the gate drive circuit.

[0014] The gate drive unit of the Nth stage to the N+2M-1th stage is a time sequence period.

[0015] The application further provides a display device, wherein the display device comprises a display area and a non-display area, and the non-display area is provided with the gate drive circuit in any of the embodiments, and is used for providing a row scanning driving signal for the display area.

[0016] The gate drive circuit comprises a driving module, the controlled end of the driving module is easily affected by the coupling of the clock signal of the input end, the controlled end of the Nth driving module is connected with the controlled end of the N+Mth driving module through the control unit, the phase of the clock signal connected with the input end of the Nth driving module is opposite to the phase of the clock signal connected with the input end of the N+Mth driving module, the capacitance connected with the controlled end of the Nth driving module and the controlled end of the N+Mth driving module is increased, the anti-noise capability of the driving module is improved, the effect of the clock signal coupling on the controlled end of the driving module is reduced, and the stability of the gate drive circuit and the panel display is improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0018] Figure 1 FIG. 1 is a structural schematic diagram of an embodiment of a gate drive circuit according to the present application;

[0019] Figure 2 FIG. 2 is a circuit structural schematic diagram of an embodiment of a gate drive circuit according to the present application;

[0020] Figure 3 FIG. 3 is a structural schematic diagram of an embodiment of a gate drive unit according to the present application;

[0021] Figure 4 FIG. 4 is a first timing schematic diagram of a gate drive circuit according to the present application;

[0022] Figure 5 FIG. 5 is a second timing schematic diagram of a gate drive circuit according to the present application;

[0023] Figure 6 FIG. 6 is a structural schematic diagram of an embodiment of a display device according to the present application.

[0024] Q drive module controlled end; Gout drive signal; VGH first voltage signal; VGL second voltage signal; VDS first control signal; VSD second control signal; N1 first control module; N2 second control module; CLK clock signal; T1 first transistor; T2 second transistor; T3 third transistor; 61 display area; 62 non-display area. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of the present application.

[0026] The terms used in the embodiments of the present application are merely for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated otherwise, "a plurality of" generally includes at least two, but does not exclude the case of including at least one.

[0027] It should be understood that the term "and / or" as used herein merely describes associated objects, and can exist in three forms: A and / or B, A or B, and A and B. In addition, the character " / " in the present application specification and claims generally represents an "or" relationship between the front and rear associated objects. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0028] It should be understood that the terms "include", "contain" or any other variation used herein are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitation, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0029] It should be noted that if the present application embodiments involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, motion condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications will also change accordingly.

[0030] Reference to "embodiments" herein means that the specific features, structures or characteristics described in conjunction with the embodiments can be included in at least one embodiment of the present application. The phrase appears in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment to other embodiments. The skilled person explicitly and implicitly understands that the embodiments described herein can be combined with other embodiments.

[0031] The design idea of the present application is: by connecting the Q points of two CLK (clock signal) opposite gate drive circuits, the Q points are coupled by the CLK signal and mutually offset, thereby increasing the capacitance connected to the Q point, improving the noise immunity of the gate drive unit, reducing the coupling effect of the CLK signal on the Q point, and further improving the stability of the GDL and panel display.

[0032] The present application provides a gate drive circuit, which is also a GDL circuit, please refer to Figure 1 , Figure 1 The structure diagram of an embodiment of the gate drive circuit of the present application. As Figure 1As shown, the gate drive circuit 1 comprises a plurality of cascaded gate drive units, each of which comprises at least one drive module, and the drive module comprises a control end (Q point), an input end and an output end. The input end of the drive module is connected to a clock signal CLK, and is configured to output a drive signal Gout corresponding to the clock signal CLK according to a control signal received by the control end.

[0033] The drive module of the Nth gate drive unit is an Nth drive module.

[0034] In this embodiment, the gate drive circuit further comprises a control unit, one end of the control unit is connected to the control end Q_N of the drive module of the Nth gate drive unit, and the other end is connected to the control end Q_N+M of the drive module of the N+Mth gate drive unit, and is configured to control the control end Q_N of the Nth drive module to be connected to the control end Q_N+M of the N+Mth drive module. The clock signal connected to the input end of the Nth drive module is opposite in phase to the clock signal connected to the input end of the N+Mth drive module. Wherein, N≥1, M≥1.

[0035] Specifically, the input end of the Nth drive module is connected to a first clock signal CLK1, and the input end of the N+Mth drive module is connected to a first+M clock signal CLK1+M. The phase of the Nth clock signal CLK1 is opposite to that of the first+M clock signal CLK1+M. In this embodiment, the gate drive circuit can include 2M-1 clock signals.

[0036] In this embodiment, the control unit is configured to control the control end of the Nth drive module to be connected to the control end of the N+Mth drive module at a low voltage, that is, when the Nth drive module and the N+Mth drive module do not output the drive signal Gout / are not working. Thus, the capacitance connected to the Q point is increased, the Q point on the Nth stage is affected by the capacitive coupling effect of the first clock signal CLK1, and the Q point on the N+Mth stage is affected by the capacitive coupling response of the second clock signal CLK1+M, which are offset to each other, thereby reducing the coupling effect of the clock signal CLK on the Q points of each stage, and further improving the stability of the GDL and the panel display.

[0037] In one embodiment, the control unit comprises a first transistor T1, a second transistor T2 and a third transistor T3. For details, please refer to Figure 2 , Figure 2 The figure is a circuit structure schematic diagram of one embodiment of the gate drive circuit of the present application. The second transistor T2 and the third transistor T3 are used to control the on / off timing of the first transistor T1, and in other embodiments, other circuit structures can also be used to replace the second transistor T2 and / or the third transistor T3.

[0038] Specifically, the gate of the first transistor T1 is connected with the first control signal A, one of the source and the drain is connected with the controlled end Q_N of the Nth driving module, and the other of the source and the drain is connected with the controlled end Q_N+M of the N+Mth driving module. In the embodiment, the first control signal A is controlled by the second transistor T2 and the third transistor T3.

[0039] The gate of the second transistor T2 is connected with the output end Gout_N+2M of the N+2Mth gate driving unit, the source is connected with the first voltage signal VGH, and the drain is connected with the gate of the first transistor T1, so as to control the first transistor T1 to be turned on by the first voltage signal VGH when scanning the N+2Mth gate driving unit, thereby connecting the controlled end Q_N of the Nth driving module with the controlled end Q_N+M of the N+Mth driving module, at this time, the Nth gate driving unit and the N+Mth gate driving unit both end the scanning. In the embodiment, the output end of the N+2Mth gate driving unit is used to control the Nth gate driving unit and the N+Mth gate driving unit to be connected in the low potential voltage, thereby improving the stability of the Nth gate driving unit and the N+Mth gate driving unit in the low potential voltage.

[0040] The gate of the third transistor T3 is connected with the output end Gout_N-2M of the N-2Mth gate driving unit, the source is connected with the second voltage signal VGL, and the drain is connected with the gate of the first transistor T1, so as to control the first transistor T1 to be turned off by the second voltage VGL when scanning the N-2Mth gate driving unit, thereby avoiding the controlled end Q_N of the Nth driving module and the controlled end Q_N+M of the N+Mth driving module from being connected in advance.

[0041] In the embodiment, the gate driving circuit can further include a reset unit, which can be a reset thin film transistor or other structures, and the reset unit is connected with the gate of the first transistor T1, specifically, the reset unit can be connected with the first transistor T1 of each stage, that is, the reset unit is connected with the plurality of first transistors T1 in the gate driving circuit. The voltage of the gate of the first transistor T1 is reset before driving the gate driving circuit, so as to ensure that the first transistor T1 is in the off state, and further ensure the stable output of the driving module in the gate driving unit of the previous stage (such as the gate driving unit of the first stage to the Mth stage). In other embodiments, the gate of the first transistor T1 can be directly connected with a reset signal line, which is not limited herein.

[0042] In the embodiment, each gate driving unit further includes a control module, and the control module is used to control the driving signal Gout output by the driving module. The control module includes a first control module and a second control module. For details, please refer to Figure 3 , Figure 3A structural schematic diagram of a gate drive unit in an embodiment of the present application.

[0043] Specifically, the Nth first control module N1 is connected with the driving signal Gout_N-H output by the Nth-Hth driving module, and the input end is connected with the first control signal VDS, for inputting the first control signal to the controlled end Q_N of the Nth driving module. The Nth second control module N2 is connected with the driving signal Gout_N+L output by the N+Lth gate drive unit, and the input end is connected with the second control signal VSD, for inputting the second control signal to the controlled end Q_N of the Nth driving module. Specifically, the first control signal VDS inputs a high voltage to the controlled end G_N of the driving module, for controlling the driving module to turn on; the second control signal VSD inputs a low voltage to the controlled end of the driving module, for controlling the driving module to turn off. In other embodiments, the driving module can also be controlled to turn on by the second control signal VSD, and the driving module can be controlled to turn off by the first control signal VDS, which is not limited herein.

[0044] In the embodiment, the first control module N1, the second control module N2 and the driving module each at least include a thin film transistor. In other embodiments, other circuit structures can also be used, which is not limited herein.

[0045] In the first embodiment, the gate drive circuit includes first and second clock signals CLK1 and CLK2 with opposite phases. Specifically, the signals of the first and second clock signals CLK1 and CLK2 are as shown in the following table. Figure 4 Figure 4 A first timing diagram of the gate drive circuit is shown in the following table. The input end of the Nth driving module is connected with the first clock signal CLK1, for outputting the Nth driving signal G_N. The input end of the N+1th driving module is connected with the second clock signal CLK2, for outputting the N+1th driving signal G_N+1. The input end of the N+2th driving module is connected with the first clock signal CLK1, for outputting the N+2th driving signal G_N+2. The input end of the N+3th driving module is connected with the second clock signal CLK2, for outputting the N+3th driving signal G_N+3. The above is sequentially repeated. At this time, M=1. Specifically, the input end of the driving module of the Nth gate drive unit corresponds to the driving signal of the first clock signal CLK1; the input end of the driving module of the N+1th gate drive unit corresponds to the driving signal of the second clock signal CLK2. After the scanning of the Nth gate drive unit is completed, the N+1th gate drive unit starts to scan, and the scanning of each row is sequentially realized.

[0046] ​In the first embodiment, the first control module N1 of the Nth gate drive unit is connected with the output end of the drive module of the N-1th gate drive unit, that is, H=1, the N-1th gate drive unit outputs the drive signal to control the drive module of the Nth gate drive unit to be turned on, at this time, the second timing signal CLK2 is at low level, the Nth gate drive unit outputs low level signal, that is, it does not work; when the second timing signal CLK2 outputs high level, the Nth gate drive unit works, outputs the drive signal G_N, and realizes the signal scanning of the Nth row. At this time, the drive signal G_N also controls the drive module of the N+1th gate drive unit to be turned on, and controls the drive module of the N-1th gate drive unit to be turned off. Thus, the scanning of each row is realized in turn. At this time, H=1, L=1. In other embodiments, H can be equal to 2, and L can also be equal to 2, which is not limited here.

[0047] Meanwhile, in the first embodiment, M=1, when the N-2th gate drive circuit of the control unit starts scanning, the Nth and N+1th gate drive units are in the non-working state, that is, the Q point is at low voltage state, the third transistor T3 is turned on by the drive signal Gout_N-2 output by the N-2th gate drive unit, so that the A point is at the second level voltage VGL, and the third transistor T3 is not turned on. When the Nth and N+1th gate drive units complete scanning, the drive signal Gout_N+2 output by the N+2th gate drive unit controls the second transistor T2 to be turned on, so that the A point is at the first level voltage VGH, and then controls the first transistor T1 to be turned on, realizes the interconnection of the controlled ends of the drive modules of the Nth and N+1th gate drive units, that is, realizes the interconnection of Q_N and Q_N+1, thereby increasing the capacitance connected to Q_N and Q_N+1, and improving the noise immunity of Q_N and Q_N+1. Wherein, N is a positive integer, and the interconnection of each gate drive unit is realized in turn, thereby improving the noise immunity of the whole gate drive circuit.

[0048] The application also provides a second gate drive circuit and a driving method thereof. Please refer to Figure 5 , Figure 5 The second timing diagram of the gate drive circuit is shown in FIG. 2. As Figure 5As shown, the gate drive circuit includes 8 clock signals, not specifically drawn here, the phase of the first clock signal CLK1 and the fifth clock signal CLK5 is exactly opposite. Among them, the driving module of the Nth gate drive unit is connected with the first clock signal CLK1, and outputs the driving signal Gout_N corresponding to one time sequence of the first clock signal CLK1; the driving module of the N+1th gate drive unit is connected with the second clock signal CLK2, and outputs the driving signal Gout_N+1 corresponding to one time sequence of the second clock signal CLK2; the driving module of the N+2th gate drive unit is connected with the second clock signal CLK3, and outputs the driving signal Gout_N+2 corresponding to one time sequence of the third clock signal CLK3; the driving module of the N+3th gate drive unit is connected with the second clock signal CLK4, and outputs the driving signal Gout_N+4 corresponding to one time sequence of the fourth clock signal CLK4; the driving module of the N+4th gate drive unit is connected with the fifth clock signal CLK5, and outputs the driving signal Gout_N+5 corresponding to one time sequence of the fifth clock signal CLK5; the driving module of the N+2Mth gate drive unit is connected with the first clock signal CLK1, and the like. Wherein, M=4.

[0049] In general, the gate drive circuit can include 2M clock signals.

[0050] Wherein, when M≥1, the first control module of the Nth gate drive unit can be connected with the output end of the driving module of the N-1th gate drive unit; the second control module of the Nth gate drive unit can be connected with the output end of the driving module of the N+2Mth gate drive unit. Wherein, when the N-1th gate drive unit scans to 1 / M time sequence, the Nth gate drive unit starts to scan, when the N+Mth gate drive unit starts to scan, the Nth gate drive unit scans to complete, at this time, the controlled end of the Nth driving module and the controlled end of the N+Mth driving module do not form a connection, when the N+2Mth gate drive unit starts to scan, the Nth and N+Mth both scan to complete, the Q point should be in low voltage state. At this time, connecting the controlled end of the Nth driving module with the controlled end of the N+Mth driving module can improve the capacitance connected on the controlled end of the Nth driving module and the controlled end of the N+Mth driving module, thereby improving the anti-noise ability of the Nth gate drive unit and the N+Mth gate drive unit, at the same time, because CLK1 and CLK1+M are opposite in phase, the controlled end of the Nth driving module and the controlled end of the N+Mth driving module are coupled by the effect of CLK signal and mutually offset (at this time, the controlled end of the Nth driving module is coupled by the rising edge of CLK1, and the controlled end of the N+Mth driving module is coupled by the falling edge of CLK1+M), which reduces the coupling effect on the Q point, and further improves the stability of the panel display.

[0051] Specifically, the drive signal Gout_N+2M outputted by the output terminal of the N+2Mth drive module controls the first transistor T1 to be turned on, thereby connecting the Q_N point, which should be at a low voltage, with the Q_N+M point, and improving the noise immunity of the Q_N and Q_N+M points.

[0052] In the embodiment, H≥1, H≤M, M≤L≤2M. That is, when the N-Mth gate drive unit starts scanning, the drive module of the Nth gate drive unit is controlled to be turned on. At this time, the drive signal Gout_N-M of the N-Mth gate drive unit is exactly opposite to the phase of the Gout_N, so even if the Nth drive module is turned on, the Nth gate drive unit does not scan because CLK1 is at a low level. Until CLK1 is at a high level, the Nth drive module outputs a high-level drive signal Gout_N to realize the scanning drive of the Nth row. H can also be greater than 1, that is, the Nth drive module can be controlled to start scanning when the N-1th drive module has not completed scanning. H can be any value from 1 to M.

[0053] Similarly, when L=M, the N+Mth gate drive unit starts scanning, and the drive module of the N+Mth gate drive unit starts scanning, the Nth gate drive unit exactly completes one timing scan, and the Nth drive module can be controlled to be turned off by the N+Mth gate drive unit. When L=2M, when the N+2Mth drive unit starts scanning, the first clock signal CLK1 connected to the input terminal of the Nth drive module enters the second timing stage (high-level voltage). At this time, the Nth drive module needs to be turned off to avoid the Nth drive module outputting multiple high-level drive signals, which leads to repeated scanning of the Nth row. Therefore, L cannot be greater than 2M. L can be any value from M to 2M.

[0054] The embodiment has the following beneficial effects: by connecting the controlled terminal of the Nth drive module and the controlled terminal of the N+Mth drive module through the control unit, and connecting the clock signal at the input terminal of the Nth drive module and the clock signal at the input terminal of the N+Mth drive module in opposite phases, the capacitance connected to the controlled terminal of the drive module is increased, the noise immunity of the drive module is improved, and the clock signal coupling effect on the controlled terminal of the drive module is reduced, thereby improving the stability of the gate drive circuit and the panel display.

[0055] The application also provides a display device, which will be described in detail below. Figure 6 , Figure 6 is an embodiment of the display device of the application. As shown in Figure 6As shown, the display device includes a display area 61 and a non-display area 62, and the non-display area 62 is provided with a gate drive circuit; the gate drive circuit is used to provide a row scanning drive signal for the display area. Wherein, the gate drive circuit can be arranged on one side of the non-display area 62, which is not limited herein. In the embodiment, the structure of the gate drive circuit can refer to the above-mentioned embodiments, which will not be described herein again.

[0056] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate driving circuit, comprising a plurality of cascaded gate driving units, each gate driving unit comprising at least a driving module, wherein the input terminal of the driving module is connected to a clock signal, and is used to output a driving signal corresponding to the clock signal according to a control signal received by the controlled terminal of the driving module, characterized in that, The gate driving circuit further includes a control unit, one end of which is connected to the controlled terminal of the driving module of the Nth stage gate driving unit, and the other end is connected to the controlled terminal of the driving module of the N+Mth stage gate driving unit. The control unit is used to control the controlled terminals of the Nth stage driving module and the N+Mth stage driving module to be connected at a low potential voltage. The clock signal connected to the input terminal of the Nth stage driving module is out of phase with the clock signal connected to the input terminal of the N+Mth stage driving module. The control unit includes at least a first transistor and a second transistor. The gate of the first transistor is connected to a first control signal. One of the source and drain of the first transistor is connected to the controlled terminal of the driving module of the Nth-level gate driving unit, and the other is connected to the controlled terminal of the driving module of the N+Mth-level gate driving unit. The gate of the second transistor is connected to the output terminal of the N+2Mth-level gate driving unit. The source of the second transistor is connected to a first voltage signal, and the drain of the second transistor is connected to the gate of the first transistor, so that when the N+2Mth-level gate driving unit is scanned, the first transistor is controlled to turn on by the first voltage signal. Where N and M are positive integers.

2. The gate driving circuit according to claim 1, characterized in that, The control unit further includes a third transistor, the gate of which is connected to the output terminal of the gate driving unit of the N-2Mth stage, the source of which is connected to a second voltage signal, and the drain of which is connected to the gate of the first transistor, so that when the gate driving unit of the N-2Mth stage is scanned, the first transistor is controlled to turn off by the second voltage signal.

3. The gate driving circuit according to claim 1, characterized in that, Each stage of the gate driving unit further includes a first control module and a second control module. The first control module of the Nth stage is connected to the drive signal output by the drive module of the NHth stage, and is used to input the first control signal to the controlled end of the drive module of the Nth stage. The second control module at level N is connected to the drive signal output by the drive module at level N+L, and is used to input a second control signal to the controlled terminal of the drive module at level N. The controlled terminal of the Nth-level drive module is connected to the first control module and the second control module of the Nth level, respectively. The input terminal of the Nth-level drive module is connected to the clock signal and is used to output the drive signal according to the clock signal; where L and H are positive integers.

4. The gate driving circuit according to claim 3, characterized in that, M≥H≥1, 2M≥L≥M.

5. The gate driving circuit according to claim 1, characterized in that, The gate driving circuit further includes a reset unit connected to the gate of the first transistor, which resets the voltage of the gate of the first transistor before driving the gate driving circuit.

6. The gate driving circuit according to claim 1, characterized in that, The time cycle from the gate driving unit of the Nth stage to the gate driving unit of the N+2M-1th stage is one timing cycle.

7. A display device comprising a display area and a non-display area, characterized in that, The non-display area is provided with a gate driving circuit as described in any one of claims 1-6; the gate driving circuit is used to provide a row scanning driving signal for the display area.

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