Fin field effect transistor and method of making the same

Abstract

The application discloses a fin field effect transistor and a preparation method thereof. The preparation method comprises the following steps: forming a first oxide layer by thermal oxidation of a surface layer of a first wafer, forming a second oxide layer by thermal oxidation of a surface layer of a second wafer, and combining the first oxide layer and the second oxide layer to form an SOI structure; removing the second wafer, the second oxide layer and the first oxide layer except for selected regions on the surface of the SOI structure, thereby forming a protruding fin structure, and the first oxide layer and the second oxide layer remaining between the fin structure and the first wafer form a buried oxide layer; manufacturing a gate electrode, and making the gate electrode cover at least the top and two sidewalls of the fin structure; patterning to define source and drain regions, doping the source and drain regions, and annealing to form a source electrode and a drain electrode. The preparation method provided by the application prevents current discharge paths, reduces static power consumption, and reduces parasitic capacitance.

Description

Technical Field

[0001] This invention relates in particular to a fin field-effect transistor and its fabrication method, belonging to the field of semiconductor technology. Background Technology

[0002] The integrated circuit industry has continuously developed in the 21st century, with device feature sizes shrinking according to Moore's Law, leading to a gradual reduction in the area of ​​field-effect transistors (FETs). This has effectively increased the performance of integrated circuits and the efficiency of silicon wafer utilization. However, with the breakthrough of the 1μm barrier and the arrival of nanometer-level feature sizes, traditional silicon devices suffer from severe short-channel effects. This results in reduced gate control over the channel, and the channel mobility degrades as the channel shortens. Therefore, solving these problems has become a key issue for the development of the semiconductor integrated circuit industry. The introduction of the FinFET effectively alleviates the short-channel effect and, due to its unique multi-gate structure, achieves higher on-state current and better gate control capabilities than planar gate FETs.

[0003] However, for traditional bulk silicon FinFET structures, the presence of a bottom current discharge channel results in high leakage current and high static power consumption. The introduction of silicon-on-insulator (SOI) structures has reduced the leakage current of FinFETs, but the severe self-heating effect of the buried oxide layer in silicon (two orders of magnitude lower than silicon) hinders the commercialization of SOI FinFETs. Existing bulk-on-insulator (BOI) structures have reduced the self-heating effect of SOI FinFETs to some extent, but the introduction of localized buried oxide can cause substrate thermal oxidation, leading to deteriorated device thermal performance, while the thermal conductivity of the silicon substrate is insufficient. Summary of the Invention

[0004] To address the severe heat dissipation problem of SOI FinFETs, the main objective of this invention is to provide a fin field-effect transistor and its fabrication method. This fin field-effect transistor uses SiC as a semiconductor substrate, effectively reducing the self-heating effect of SOI FinFETs and blocking the current leakage path at the bottom of bulk silicon FinFETs, thereby overcoming the shortcomings of the prior art.

[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0006] This invention provides a method for fabricating a fin field-effect transistor, comprising:

[0007] The SiC on the surface of the first wafer is thermally oxidized to form a first oxide layer, and the silicon on the surface of the second wafer is thermally oxidized to form a second oxide layer. The first oxide layer and the second oxide layer are then combined to form an SOI structure.

[0008] Remove the second wafer, the second oxide layer, and the first oxide layer from the selected area on the surface of the SOI structure until the first wafer is exposed, so that the remaining second wafer in the selected area forms a raised fin structure, and the remaining first oxide layer and second oxide layer between the fin structure and the first wafer form a buried oxide layer.

[0009] Fabricate a gate such that the gate at least covers the top and two sidewalls of the fin structure.

[0010] The source and drain regions are graphically defined, and the source and drain regions are doped and annealed to form the source and drain electrodes.

[0011] This invention also provides a fin field-effect transistor prepared by the aforementioned preparation method.

[0012] Compared with the prior art, the advantages of the present invention include:

[0013] 1) The method for fabricating a finned field-effect transistor provided in this embodiment of the invention uses SiC as a semiconductor substrate, which has better heat dissipation performance than traditional Si-based materials;

[0014] 2) The embodiment of the present invention provides a method for fabricating a fin field-effect transistor, which forms a raised fin structure by etching the top silicon and oxide layer to the silicon carbide substrate. The deposited gate electrode is in direct contact with the silicon carbide substrate. The heat generated when the device is working is conducted through the gate oxide layer, which is beneficial for heat conduction.

[0015] 3) The method for fabricating a fin field-effect transistor provided in this embodiment of the invention, compared with the traditional fin field-effect transistor, the buried oxide layer under the fin structure of the present invention prevents the current discharge path, reduces static power consumption, and the silicon oxide has a relatively low dielectric constant, which reduces parasitic capacitance.

[0016] 4) The method for fabricating a fin field-effect transistor provided in this embodiment of the invention forms a buried oxide layer before the fin structure etching step. Therefore, after etching to form the fin structure, the exposed part of the silicon carbide substrate surface is free of silicon oxide layer. Compared with the buried oxide layer formed by traditional thermal oxidation, this method prevents the substrate oxide layer introduced during thermal oxidation and enhances the heat dissipation performance of the device. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the cross-sectional structure of a fin field-effect transistor provided in a typical embodiment of the present invention;

[0018] Figure 2 This is a top view of a fin field-effect transistor provided in a typical embodiment of the present invention;

[0019] Figures 3a-3e This is a schematic diagram of the device structure formed by each step in the fabrication method of a fin field-effect transistor provided in a typical embodiment of the present invention. Detailed Implementation

[0020] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0021] This invention provides a method for fabricating a fin field-effect transistor, comprising:

[0022] The SiC on the surface of the first wafer is thermally oxidized to form a first oxide layer, and the silicon on the surface of the second wafer is thermally oxidized to form a second oxide layer. The first oxide layer and the second oxide layer are then combined to form an SOI structure.

[0023] Remove the second wafer, the second oxide layer, and the first oxide layer from the selected area on the surface of the SOI structure until the first wafer is exposed, so that the remaining second wafer in the selected area forms a raised fin structure, and the remaining first oxide layer and second oxide layer between the fin structure and the first wafer form a buried oxide layer.

[0024] Fabricate a gate such that the gate at least covers the top and two sidewalls of the fin structure.

[0025] The source and drain regions are graphically defined, and the source and drain regions are doped and annealed to form the source and drain electrodes.

[0026] In some specific implementations, the thickness of the first oxide layer is greater than 0 and less than 20 angstroms, the thickness of the second oxide layer is 20-2000 angstroms, and the thickness of the buried oxide layer is 20-2000 angstroms.

[0027] In some specific implementation examples, the preparation method includes: bonding the first oxide layer and the second oxide layer together to form the buried oxide layer.

[0028] In some specific implementation examples, the preparation method further includes: after combining the first oxide layer and the second oxide layer, heat-treating the SOI structure at a temperature of 200-400℃ for a time of 10-10000s.

[0029] In some specific implementation cases, the first wafer is a silicon carbide wafer, the second wafer is a silicon wafer, and both the first oxide layer and the second oxide layer are silicon oxide layers.

[0030] In some specific implementations, the fabrication method includes: setting a plurality of spaced masks in a selected area on the surface of the second wafer, and etching the area not covered by the masks until the first wafer is exposed, thereby forming a plurality of spaced fin structures in the selected area covered by the masks.

[0031] In some specific implementations, the angle between the sidewall of the fin structure and the surface of the first wafer or the top surface of the fin structure is 60°-90°.

[0032] In some specific implementations, the width of the buried oxide layer is greater than the width of the fin structure.

[0033] In some specific implementation cases, the width of the fin structure is 5-100 nm, and the width of the buried oxide layer is 5-1000 nm.

[0034] In some specific implementations, the fabrication method includes: first forming a gate oxide layer on the top and two sidewall surfaces of the fin structure, and then fabricating the gate.

[0035] This invention also provides a fin field-effect transistor prepared by the aforementioned preparation method.

[0036] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the semiconductor structure layer fabrication, thermal oxidation, bonding, annealing and other processes used in the embodiments of the present invention can be implemented by equipment and methods known to those skilled in the art, and will not be specifically limited or described here.

[0037] Example 1

[0038] Please see Figure 1 and Figure 2 A fin field-effect transistor includes a silicon carbide substrate 100, a buried oxide layer 110 formed on the silicon carbide substrate, a fin structure 120 formed on the buried oxide layer 110, and a source 121, a drain 122, and a gate 211 cooperating with the fin structure 120. The gate 211 is disposed along a first direction on the top surface of the fin structure 120 and two opposite sidewall surfaces of the fin structure 120. The fin structure 120 in contact with the gate 211 serves as a channel region. The source 121 and the drain 122 are disposed on both sides of the channel region along a second direction.

[0039] In this embodiment, the sidewall of the fin structure 120 is inclined, and the angle between the sidewall of the fin structure 120 and the top surface of the fin structure is 60°-90°. The width of the buried oxide layer 110 is greater than the width of the fin structure 120. The width of the fin structure is 5-100nm, and the width of the buried oxide layer is 5-1000nm.

[0040] In this embodiment, the fin structure 120 is made of silicon, the buried oxide layer 110 is made of silicon oxide, and the thickness of the buried oxide layer 110 is 20-2000 angstroms.

[0041] In this embodiment, the gate 211 is in direct contact with the silicon carbide substrate 100 or is in auxiliary contact with the silicon carbide substrate 100 through other conductive materials.

[0042] In this embodiment, a gate oxide layer 210 is also provided between the gate 211 and the fin structure 120.

[0043] Please see Figures 3a-3e A method for fabricating a fin field-effect transistor may include the following steps:

[0044] Step 1): Thermally oxidize the silicon carbide on the surface of the silicon carbide substrate 100 to form a first silicon dioxide layer 101, the thickness of the first silicon dioxide layer 101 being 0-20 angstroms; thermally oxidize the silicon on the surface of the silicon wafer 103 to form a second silicon dioxide layer 104, the thickness of the second silicon dioxide layer 101 being 20-2000 angstroms.

[0045] The first silicon dioxide layer 101 on the surface of the silicon carbide substrate 100 is bonded to the second silicon dioxide layer 104 on the surface of the silicon wafer 103, and the SOI structure formed after bonding is heat-treated at a temperature below 400°C, so that the silicon carbide substrate 100 and the silicon wafer 103 are integrated into one, and the thickness of the bonded silicon dioxide layer is 20-2000 angstroms.

[0046] In this embodiment, the method for forming a first silicon oxide layer by thermal oxidation of SiC on the surface of the first wafer may include:

[0047] The SiC wafer is placed in the reaction chamber;

[0048] A protective gas supply mechanism is used to introduce a protective gas into the reaction chamber to isolate oxygen and water vapor. While maintaining a positive atmospheric pressure relative to the environment, the pressure inside the reaction chamber is kept above 1.05 atm. A heating mechanism is used to raise the temperature inside the reaction chamber to 1200-1400°C at a heating rate of 10-50°C / s. Then, an oxygen source gas supply mechanism is used to introduce oxygen source gas preheated to 1200-1400°C into the reaction chamber to carry out the thermal oxidation reaction.

[0049] After the thermal oxidation reaction is completed, while keeping the temperature inside the reaction chamber constant, stop feeding oxygen into the reaction chamber, and at the same time feed protective gas preheated to 1200-1400°C into the reaction chamber through the protective gas supply mechanism to purge oxygen from the reaction chamber.

[0050] Heating of the reaction chamber is stopped, and a protective gas at room temperature is introduced into the reaction chamber through a protective gas supply mechanism. Under vacuum conditions, the SiC wafer is rapidly cooled to below 300°C at a cooling rate of 100-400°C / s. The protective gas includes nitrogen and / or inert gases, but is not limited to these.

[0051] The method for thermally oxidizing the SiC surface layer of the first wafer to form the first oxide silicon may also include:

[0052] The SiC wafer is placed in the reaction chamber;

[0053] The reaction chamber is evacuated using a vacuum generator to remove the air from it;

[0054] The SiC wafer is heated in a vacuum environment to rapidly raise its temperature to 1000-1400°C at a heating rate of 10-50°C / s. Then, oxygen source gas preheated to 1000-1400°C is introduced into the reaction chamber by an oxygen source supply mechanism to carry out the thermal oxidation reaction.

[0055] After the thermal oxidation reaction is completed, while keeping the temperature inside the reaction chamber constant, stop feeding oxygen gas into the reaction chamber, and at the same time use a vacuum generator to evacuate the reaction chamber again.

[0056] Heating of the reaction chamber is stopped, and a cooling medium gas is introduced into the reaction chamber through a cooling medium supply mechanism. Under vacuum conditions, the SiC wafer is rapidly cooled to below 300°C at a cooling rate of 100-400°C / s. The cooling medium gas is a gas at room temperature and includes any one or a combination of two or more of nitric oxide, nitrogen, and inert gases, but is not limited to these.

[0057] The inventors of this case discovered that when the surface layer of a silicon carbide substrate is oxidized using thermal oxidation, and the thickness of the resulting silicon dioxide layer is less than 20 angstroms, airflow and impurities below the silicon dioxide layer can easily diffuse through it. Byproducts generated during the thermal oxidation process are less likely to remain within the silicon dioxide layer or at the silicon dioxide / silicon carbide interface, resulting in a very clean silicon dioxide layer and silicon dioxide / silicon carbide interface, with a defect density that can be controlled to within 102. 11 cm- 2 Below this, carrier mobility can reach 300 cm⁻¹.2 / Vs, or even higher.

[0058] In this embodiment, the oxidation of the wafer can be achieved in a manner known to those skilled in the art.

[0059] Optionally, after bonding the silicon carbide substrate to the silicon wafer, a portion of the top silicon layer is etched away until the silicon wafer portion is processed to the required thickness.

[0060] Step 2): On the SOI structure including silicon carbide substrate, insulating oxide layer and top silicon structure (i.e. the remaining silicon wafer portion, the same below), multiple hard mask layers 220 arranged in alternating phases as channels are fabricated. The material, thickness, width and other properties of the mask layers 220 can be adjusted according to specific needs, and no specific limitation is made here.

[0061] Step 3): Using the hard mask layer 220 as a mask, etch the portion not covered by the hard mask layer 220 until the silicon carbide substrate is exposed, thereby forming a plurality of fin structures 120 in the area covered by the hard mask layer 220. The silicon oxide layer below the fin structure 120 forms a buried oxide layer 110, and the sidewalls of the fin structure 120 and the top surface of the fin structure form an angle of 60°-90°. The width of the buried oxide layer 110 is greater than or equal to the width of the fin structure 120.

[0062] Step 4): A gate 211 is formed on the top surface and two opposite sidewall surfaces of the fin structure 120, and the gate 211 is made to directly contact the silicon carbide substrate 100 or to make auxiliary contact with the silicon carbide substrate 100 through other conductive materials.

[0063] Step 5): Graphically define the source and drain regions, dope and anneal to form source 121 and drain 122.

[0064] Comparative Example 1

[0065] The fabrication method of a fin field-effect transistor in Comparative Example 1 is basically the same as that in Example 1, except that:

[0066] Step 1): The silicon carbide on the surface of the silicon carbide substrate 100 is thermally oxidized to form a silicon dioxide layer, and then a top silicon layer is transferred on the silicon dioxide layer.

[0067] Comparative Example 2

[0068] The fabrication method of a fin field-effect transistor in Comparative Example 2 is basically the same as that in Example 1, except that:

[0069] Step 1): Provide a silicon carbide substrate 100, and sequentially transfer and form a silicon oxide layer and a top silicon layer on the surface of the silicon carbide substrate 100, and bond them together to form an integral whole.

[0070] This invention provides a method for fabricating a FinFET, addressing the issues of high bottom leakage current leading to large static power consumption in traditional bulk silicon FinFETs and severe self-heating effects in FinFETs on silicon-on-insulator (SOI) structures. The invention employs an SOI structure on silicon carbide, patterning and etching the top silicon and oxide layers onto the silicon carbide substrate to form Fin stripes on the substrate and a local buried oxide structure (i.e., buried oxide layer) beneath the Fin stripes. Since silicon carbide has an order of magnitude higher thermal conductivity than silicon, the device achieves excellent heat dissipation while simultaneously blocking the bottom leakage path of the FinFET, thus reducing static power consumption.

[0071] The present invention provides a method for fabricating a fin field-effect transistor, which employs an SOI structure on a silicon carbide substrate. This avoids the substrate oxidation problem caused by the thermal oxidation of the fin strips (i.e., the fin structure) after etching to form the fin structure, thus achieving better heat dissipation performance. Furthermore, the method for fabricating a fin field-effect transistor using the SOI structure on silicon carbide is formed by thermally oxidizing oxide layers on both the silicon carbide substrate and the silicon wafer, and then bonding the oxide layers on the silicon carbide substrate and the silicon wafer. This method results in an SOI structure on silicon carbide with good oxide layer quality, reducing the bottom leakage problem of the fin field-effect transistor.

[0072] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method of fabricating a fin field effect transistor, comprising: The method comprises the following steps: ​ forming a first oxide layer by thermal oxidation of a surface layer of a first wafer and a second oxide layer by thermal oxidation of a surface layer of a second wafer, and combining the first oxide layer and the second oxide layer to form an SOI structure, wherein the first wafer is a silicon carbide wafer, the second wafer is a silicon wafer, and the first oxide layer and the second oxide layer are both silicon oxide layers; removing the second wafer, the second oxide layer and the first oxide layer from a selected region on a surface of the SOI structure to expose the first wafer, so that the second wafer remaining in the selected region forms a protruding fin structure, and the first oxide layer and the second oxide layer remaining between the fin structure and the first wafer form a buried oxide layer; forming a gate electrode covering at least the top and two sidewalls of the fin structure, patterning source and drain regions, doping the source and drain regions and annealing to form source and drain electrodes.

2. The method of claim 1, wherein: The thickness of the first oxide layer is greater than 0 and less than 20 angstroms, the thickness of the second oxide layer is 20-2000 angstroms, and the thickness of the buried oxide layer is 20-2000 angstroms.

3. The production method according to claim 1, characterized by, The method comprises the following steps: combining the first oxide layer and the second oxide layer to form the buried oxide layer by bonding.

4. The production method according to claim 3, characterized by, The method further comprises the following steps: after combining the first oxide layer and the second oxide layer, heat treating the SOI structure at a temperature of 200-400 DEG C for a time period of 10-10000 seconds.

5. The production method according to claim 1, characterized by, The method comprises the following steps: forming a plurality of spaced-apart fin structures in selected regions of the surface of the second wafer by etching regions not covered by a plurality of spaced-apart masks arranged in the selected regions to expose the first wafer.

6. The method of claim 1, wherein: The angle between the sidewall of the fin structure and the surface of the first wafer or the top surface of the fin structure is 60-90 DEG.

7. The method of claim 1, wherein: The width of the buried oxide layer is greater than the width of the fin structure.

8. The method of claim 1 or 7, wherein: The width of the fin structure is 5-100 nm, and the width of the buried oxide layer is 5-1000 nm.

9. The method of claim 1, wherein, The method comprises the following steps: forming a gate oxide layer on the top and two sidewalls of the fin structure before forming the gate electrode.

10. A fin field effect transistor obtained by the method of any one of claims 1-9.

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