An optoelectronic adaptive time synchronization circuit and method

Abstract

The present invention discloses an optoelectronic adaptive time synchronization circuit, comprising: an adaptive control signal generation circuit, an optoelectronic adaptive selection circuit, and an output selection circuit; the adaptive control signal generation circuit includes a monostable flip-flop; the optical time synchronization signal input terminal is connected to an input pin of the monostable flip-flop; an output pin of the monostable flip-flop outputs an optical enable signal, and another output pin of the monostable flip-flop outputs an electrical enable signal; the optoelectronic adaptive selection circuit includes a first AND gate, a second AND gate, and an OR gate; an input pin of the first AND gate is connected to an output pin of the monostable flip-flop, and another input pin of the first AND gate is connected to the optical time synchronization signal input terminal; an input pin of the second AND gate is connected to another output pin of the monostable flip-flop, and another input pin of the second AND gate is connected to the electrical signal input terminal; the output pin of the first AND gate is connected to an input pin of the OR gate; the output pin of the second AND gate is connected to another input pin of the OR gate.

Description

Technical Field

[0001] The present invention belongs to the technical field of power system automation, and particularly relates to an optoelectronic adaptive time synchronization circuit and method applicable to secondary equipment of a substation. Background Technique

[0002] The accuracy and uniformity of time are the most basic requirements for a substation automation system. All kinds of automation devices in modern power systems, such as electronic current transformers, merging units, switches, protection and measurement control devices, etc., must operate based on a unified time reference to meet the requirements of sequence of events recording (SOE), fault recording, and real-time data acquisition time consistency, and ensure the accuracy of line fault location, phasor and attack angle dynamic monitoring, and unit and power grid parameter verification. In case of an accident, the cause and process of the accident can be accurately analyzed based on the fault recording data and the sequence and accurate time of the actions of each switch and circuit breaker.

[0003] To achieve the unification of the clock time reference for the entire power grid, a time synchronization system capable of timing all secondary equipment and devices at different locations and substations across the network is necessary. The emergence of global satellite systems (GPS and Beidou) makes it possible to meet these requirements. There are five time synchronization methods based on GPS and Beidou: (1) Pulse time synchronization method; (2) Serial port time synchronization method; (3) IRIG-B time code time synchronization method; (4) NTP / SNTP network time synchronization method; (5) 1588PTP precise time method.

[0004] Pulse time synchronization and serial port time synchronization each have their own advantages and disadvantages. The former has high precision but cannot directly provide time information, while the latter has relatively low time synchronization precision. IRIG-B code time synchronization is an international standard specifically formulated for clock serial transmission synchronization. It uses pulse width modulation and combines the advantages of pulse time synchronization and serial port time synchronization. It is a time synchronization method with very high precision (microsecond level) and containing absolute accurate time information. When using IRIG-B code time synchronization, there is no need for time synchronization through the communication message of the field bus, nor for the GPS to output a large number of pulse node signals.

[0005] The invention patent with the publication number of CN 110224702 B discloses a time code IRIG-B adaptive decoding device and decoding method, which provides two optoelectronic interfaces, and no matter which signal is input, the program can adaptively identify it, improving the compatibility of the device. However, this invention patent has the following disadvantages:

[0006] (1) The adaptive recognition of the two optoelectronic input signals is completed through a program in the MCU, which requires additional space, time, and resources, and the discrimination speed is slow.

[0007] (2) When two physical interfaces are simultaneously connected to valid signals, the signal that is connected first is adopted by default. That is, there is no priority between the two input signals, and it is not possible to preferentially adopt the optical signal with low transmission loss and strong anti-electromagnetic interference ability. Summary of the Invention

[0008] Object of the Invention: To solve the problems that the adaptive recognition of existing optical and electrical input signals requires additional space, time, and resources and has a slow discrimination speed, and to solve the problem that there is no priority between the two input signals and it is not possible to preferentially adopt the optical signal with low transmission loss and strong anti-electromagnetic interference ability, the present invention discloses an optical and electrical adaptive time synchronization circuit and method; the fast recognition of optical and electrical time synchronization signals is realized through a hardware circuit, without occupying additional system resources or consuming additional calculation time, and when optical and electrical time synchronization signals are simultaneously connected, the optical time synchronization signal with higher transmission quality and less susceptibility to interference is preferentially adopted, and the time synchronization accuracy is higher.

[0009] Technical Solution: An optical and electrical adaptive time synchronization circuit includes:

[0010] An adaptive control signal generation circuit for generating an adaptive control signal according to the presence or absence of an optical time synchronization signal input;

[0011] An optical and electrical adaptive selection circuit for selecting a signal source according to the adaptive control signal;

[0012] An output selection circuit for outputting the signal source selected by the optical and electrical adaptive selection circuit;

[0013] Among them, the adaptive control signal generation circuit includes a monostable flip-flop; the optical time synchronization signal input terminal is connected to an input pin of the monostable flip-flop; an output pin of the monostable flip-flop outputs an optical enable signal, and another output pin of the monostable flip-flop outputs an electrical enable signal. When there is a time synchronization signal at the optical time synchronization signal input terminal, the optical enable signal is valid and the electrical enable signal is invalid; when there is no time synchronization signal at the optical time synchronization signal input terminal, the optical enable signal is invalid and the electrical enable signal is valid;

[0014] Among them, the optical and electrical adaptive selection circuit includes a first AND gate, a second AND gate, and an OR gate; one input pin of the first AND gate is connected to an output pin of the monostable flip-flop, and the other input pin of the first AND gate is connected to the optical time synchronization signal input terminal; one input pin of the second AND gate is connected to another output pin of the monostable flip-flop, and the other input pin of the second AND gate is connected to the electrical signal input terminal; the output pin of the first AND gate is connected to one input pin of the OR gate; the output pin of the second AND gate is connected to the other input pin of the OR gate, and the output pin of the OR gate outputs the selected signal source.

[0015] Further, the adaptive control signal generation circuit further includes: a first resistor and a first capacitor; one end of the first resistor is connected to the power supply, and the other end thereof is connected to the pin Rcext of the monostable flip-flop; one end of the first capacitor is connected to the pin Rcext of the monostable flip-flop, and the other end thereof is connected to the pin Cext of the monostable flip-flop; by adjusting the magnitudes of the first resistor and the first capacitor, the time for optical pulse detection is adjusted.

[0016] Further, the adaptive control signal generation circuit further includes a second resistor, a third resistor and a second capacitor; one end of the second resistor is connected to the power supply, and the other end thereof is connected to the pin B of the monostable flip-flop, for providing a definite high level to the pin B of the monostable flip-flop; one end of the third resistor is connected to the power supply, and the other end thereof is connected to the pin CLR of the monostable flip-flop; one end of the second capacitor C2 is connected to the pin CLR of the monostable flip-flop, and the other end thereof is grounded, and the third resistor and the second capacitor form a power-on reset circuit, generating a reset signal with a certain rise time when power is on.

[0017] Further, the adaptive control signal generation circuit further includes a third capacitor, one end of the third capacitor is connected to the pin VCC of the monostable flip-flop, and the other end thereof is connected to the pin GND of the monostable flip-flop; the pin VCC of the monostable flip-flop is connected to the power supply; the pin GND of the monostable flip-flop is grounded.

[0018] Further, the photoelectric adaptive selection circuit further includes a fourth resistor and a fourth capacitor; one end of the fourth resistor is connected to the power supply, and the other end thereof is connected to the pin B2 of the first AND gate, for providing a definite high level to the pin B2 of the first AND gate when a high impedance is output from an output pin of the monostable flip-flop; one end of the fourth capacitor is connected to the power supply pin of the first AND gate, and the other end thereof is grounded;

[0019] The photoelectric adaptive selection circuit further includes a fifth resistor and a fifth capacitor; one end of the fifth resistor is connected to the power supply, and the other end thereof is connected to the pin B3 of the second AND gate; one end of the fifth capacitor is connected to the power supply pin of the second AND gate, and the other end thereof is grounded;

[0020] The photoelectric adaptive selection circuit further includes a sixth capacitor; one end of the sixth capacitor is connected to the power supply pin of the OR gate, and the other end thereof is grounded;

[0021] The power supply pin of the first AND gate is connected to the power supply, and the ground pin of the first AND gate is grounded;

[0022] The power supply pin of the second AND gate is connected to the power supply, and the ground pin of the second AND gate is grounded;

[0023] The power supply pin of the OR gate is connected to the power supply, and the ground pin of the OR gate is grounded;

[0024] Further, the output selection circuit includes a sixth resistor. One end of the sixth resistor is connected to the output pin of the OR gate, and the other end is connected to the signal output terminal, for outputting the signal source selected by the optoelectronic adaptive selection circuit.

[0025] Further, the output selection circuit further includes an optical timing signal output circuit. The optical timing signal output circuit includes a seventh resistor. One end of the seventh resistor is connected to the optical timing signal input terminal, and the other end is connected to the signal output terminal, for outputting the optical timing signal.

[0026] Further, the output selection circuit further includes an electrical timing signal output circuit. The electrical timing signal output circuit includes an eighth resistor. One end of the eighth resistor is connected to the electrical timing signal input terminal, and the other end is connected to the signal output terminal, for outputting the electrical timing signal.

[0027] The present invention also discloses an optoelectronic adaptive timing method, including the following steps:

[0028] Step 1: According to the presence or absence of an optical timing signal input, an adaptive control signal is generated by the adaptive control signal generation circuit;

[0029] Step 2: According to the adaptive control signal, the selected signal source is output by the optoelectronic adaptive selection circuit;

[0030] Step 3: Build an output selection circuit to output the selected signal source;

[0031] Step 4: Perform timing based on the output signal source;

[0032] Wherein, the adaptive control signal generation circuit includes a monostable flip-flop; the optical timing signal input terminal is connected to an input pin of the monostable flip-flop; an output pin of the monostable flip-flop outputs an optical enable signal, and another output pin of the monostable flip-flop outputs an electrical enable signal. When there is a timing signal at the optical timing signal input terminal, the optical enable signal is valid and the electrical enable signal is invalid; when there is no timing signal at the optical timing signal input terminal, the optical enable signal is invalid and the electrical enable signal is valid;

[0033] Among them, the photoelectric adaptive selection circuit includes a first AND gate, a second AND gate, and an OR gate; one input pin of the first AND gate is connected to an output pin of the monostable flip-flop, and the other input pin of the first AND gate is connected to the optical timing signal input terminal; one input pin of the second AND gate is connected to the other output pin of the monostable flip-flop, and the other input pin of the second AND gate is connected to the electrical signal input terminal; the output pin of the first AND gate is connected to one input pin of the OR gate; the output pin of the second AND gate is connected to the other input pin of the OR gate, and the output pin of the OR gate outputs the selected signal source.

[0034] Furthermore, the adaptive control signal generation circuit further includes: a first resistor and a first capacitor; one end of the first resistor is connected to the power supply, and the other end is connected to the pin Rcext of the monostable flip-flop; one end of the first capacitor is connected to the pin Rcext of the monostable flip-flop, and the other end is connected to the pin Cext of the monostable flip-flop; by adjusting the sizes of the first resistor and the first capacitor, the time for optical pulse detection is adjusted.

[0035] The adaptive control signal generation circuit further includes a second resistor, a third resistor, and a second capacitor; one end of the second resistor is connected to the power supply, and the other end is connected to the pin B of the monostable flip-flop, for providing a definite high level to the pin B of the monostable flip-flop; one end of the third resistor is connected to the power supply, and the other end is connected to the pin CLR of the monostable flip-flop; one end of the second capacitor C2 is connected to the pin CLR of the monostable flip-flop, and the other end is grounded. The third resistor and the second capacitor form a power-on reset circuit, generating a reset signal with a certain rising time when powered on.

[0036] The adaptive control signal generation circuit further includes a third capacitor. One end of the third capacitor is connected to the pin VCC of the monostable flip-flop, and the other end is connected to the pin GND of the monostable flip-flop; the pin VCC of the monostable flip-flop is connected to the power supply; the pin GND of the monostable flip-flop is grounded.

[0037] The photoelectric adaptive selection circuit further includes a fourth resistor and a fourth capacitor; one end of the fourth resistor is connected to the power supply, and the other end is connected to the pin B2 of the first AND gate, for providing a definite high level to the pin B2 of the first AND gate when a high impedance is output from an output pin of the monostable flip-flop; one end of the fourth capacitor is connected to the power supply pin of the first AND gate, and the other end is grounded.

[0038] The photoelectric adaptive selection circuit further includes a fifth resistor and a fifth capacitor; one end of the fifth resistor is connected to the power supply, and the other end is connected to the pin B3 of the second AND gate; one end of the fifth capacitor is connected to the power supply pin of the second AND gate, and the other end is grounded.

[0039] The photoelectric adaptive selection circuit further includes a sixth capacitor; one end of the sixth capacitor is connected to the power supply pin of the OR gate, and the other end is grounded;

[0040] The power supply pin of the first AND gate is connected to the power supply, and the grounding pin of the first AND gate is grounded;

[0041] The power supply pin of the second AND gate is connected to the power supply, and the grounding pin of the second AND gate is grounded;

[0042] The power supply pin of the OR gate is connected to the power supply, and the grounding pin of the OR gate is grounded;

[0043] The output selection circuit includes a sixth resistor. One end of the sixth resistor is connected to the output pin of the OR gate, and the other end is connected to the signal output terminal, for outputting the signal source selected by the photoelectric adaptive selection circuit;

[0044] The output selection circuit further includes an optical time synchronization signal output circuit. The optical time synchronization signal output circuit includes a seventh resistor. One end of the seventh resistor is connected to the optical time synchronization signal input terminal, and the other end is connected to the signal output terminal, for outputting the optical time synchronization signal;

[0045] The output selection circuit further includes an electrical time synchronization signal output circuit. The electrical time synchronization signal output circuit includes an eighth resistor. One end of the eighth resistor is connected to the electrical time synchronization signal input terminal, and the other end is connected to the signal output terminal, for outputting the electrical time synchronization signal.

[0046] Advantageous effects: Compared with the prior art, the present invention has the following advantages:

[0047] (1) The present invention realizes the adaptive recognition of the photoelectric time synchronization signal, improves the compatibility of secondary power equipment, and enables the equipment to flexibly adapt to different application requirements. Moreover, the generation of the adaptive control signal and the adaptive selection of the photoelectric signal are all completed by the hardware circuit, without occupying additional system resources or consuming additional computing time, and the recognition of the photoelectric time synchronization signal is faster;

[0048] (2) Whether the photoelectric adaptive selection circuit outputs an optical signal or an electrical signal first depends on whether there is a signal at the optical signal input terminal, that is, the priority of the optical signal is higher than that of the electrical signal. When the optical and electrical input signals are connected simultaneously, the photoelectric adaptive selection circuit can preferentially adopt the optical time synchronization signal with higher transmission quality and less susceptible to interference, effectively guaranteeing the time synchronization accuracy;

[0049] (3) The IRIG serial time code format applicable to the present invention is not unique. When the photoelectric adaptive circuit operates in the mode where the optical signal is valid, by adjusting the sizes of the first resistor and the first capacitor, the time for detecting the optical pulse can be adjusted to achieve compatibility with various formats of IRIG serial time codes. Description of the Drawings

[0050] Figure 1 It is a schematic diagram of an optoelectronic adaptive time synchronization circuit. Specific implementation manners

[0051] The technical solution of the present invention will be further elaborated below in conjunction with the accompanying drawings and embodiments.

[0052] As Figure 1 shown, this embodiment discloses an optoelectronic adaptive time synchronization circuit, which mainly includes: an adaptive control signal generation circuit, an optoelectronic adaptive selection circuit, and an output selection circuit.

[0053] Among them, the adaptive control signal generation circuit is used to generate an adaptive control signal according to the presence or absence of an optical signal input, and transmit it to the optoelectronic adaptive selection circuit.

[0054] The adaptive control signal generation circuit of this embodiment mainly includes: chip U1. Among them, the optical signal input terminal is connected to

[0055] the input pin A of chip U1; the output pin of chip U1 outputs an optical enable signal, and the output pin Q of chip U1 outputs an electrical enable signal, and the optical enable signal and the electrical enable signal are always opposite. When there is a signal at the optical signal input terminal,

[0056] the optical enable signal is valid, that is, the electrical enable signal is invalid, that is, Q = 1; when there is no signal at the optical signal input terminal, the optical

[0057] enable signal is invalid, that is, the electrical enable signal is valid, that is, Q = 0. In some embodiments, chip U1 can be a monostable flip-flop, with the model number 74HC123D.

[0058] The adaptive control signal generation circuit of this embodiment further includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is connected to the power supply, and the other end is connected to the pin Rcext of chip U1; one end of the first capacitor C1 is connected to the pin RCext of chip U1, and the other end is connected to the pin Cext of chip U1. By adjusting the sizes of the first resistor R1 and the first capacitor C1, the detection time of the optical pulse can be adjusted to achieve compatibility with various formats of IRIG serial time codes.

[0059] The IRIG serial time code format applicable to this embodiment is not unique. When the optoelectronic adaptive circuit operates in the mode where the optical signal is valid, by adjusting the magnitudes of the first resistor R1 and the first capacitor C1, the time for detecting the optical pulse can be adjusted, achieving compatibility with various formats of IRIG serial time codes in Table 1. The time constant t = 0.45 * R1 * C1. When t > 0.1 mS, it can be compatible with the IRIG-G format serial code. When t > 10 mS, it can be compatible with both the IRIG-G and IRIG-B format serial codes. When t > 1 S, it can be compatible with the IRIG-G, IRIG-B, and IRIG-H format serial codes.

[0060] Table 1 Main parameters of six IRIG serial time code formats

[0061]

[0062] The adaptive control signal generation circuit of this embodiment further includes a second resistor R2, a third resistor R3, and a second capacitor C2. One end of the second resistor R2 is connected to the power supply, and the other end is connected to pin B of the chip U1. One end of the third resistor R3 is connected to the power supply, and the other end is connected to pin CLR of the chip U1. One end of the second capacitor C2 is connected to pin CLR of the chip U1, and the other end is grounded. The second resistor R2 is a pull-up resistor, providing a definite high level for the B channel of the chip U1. The third resistor R3 and the second capacitor C2 form a power-on reset circuit, generating a reset signal with a certain rising time during power-on, and the time constant t = R3 * C2.

[0063] The adaptive control signal generation circuit of this embodiment further includes a third capacitor C3. One end of the third capacitor C3 is connected to pin VCC of the chip U1, and the other end is connected to pin GND of the chip U1. Pin VCC of the chip U1 is connected to the power supply. Pin GND of the chip U1 is grounded. The third capacitor C3 is a power supply filtering capacitor for the chip U1, used to provide a relatively stable power supply for U1 and at the same time reduce the noise coupled from the U1 chip to the power supply terminal.

[0064] Among them, the optoelectronic adaptive selection circuit is used to select a signal source according to the adaptive control signal and transmit the selected signal source to the output selection circuit.

[0065] The optoelectronic adaptive selection circuit of this embodiment includes a first AND gate U2, a second AND gate U3, and an OR gate U4. The

[0066] input pin B2 of the first AND gate U2 is connected to the output pin of the chip U1 The input pin B3 of the second AND gate U3 is connected to the output pin Q of the chip U1. The input pin A2 of the first AND gate U2 is connected to the optical signal input terminal; the input pin A3 of the second AND gate U3 is connected to the electrical signal input terminal. The output pin F2 of the first AND gate U2 is connected to the input pin B4 of the OR gate U4; the output pin F3 of the second AND gate U3 is connected to the input pin A4 of the OR gate U4, and the output pin F4 of the OR gate U4 outputs the selected signal source.

[0067] When the optical enable signal is valid and the electrical enable signal is invalid (i.e., Q = 1), the output pin F2 of the first AND gate U2 outputs an optical signal, the output pin F3 of the second AND gate U3 outputs a high level, and the output pin F4 of the OR gate U4 outputs an optical signal; when the optical enable signal is invalid and the electrical enable signal is valid (i.e.,

[0068] Q = 0), the output pin F2 of the first AND gate U2 outputs a high level, the output pin F3 of the second AND gate U3 outputs an electrical signal, and the output pin F4 of the OR gate U4 outputs an electrical signal. Q = 0), the output pin F2 of the first AND gate U2 outputs a high level, the output pin F3 of the second AND gate U3 outputs an electrical signal, and the output pin F4 of the OR gate U4 outputs an electrical signal.

[0069] The optoelectronic adaptive selection circuit of this embodiment further includes a fourth resistor R4 and a fourth capacitor C4. One end of the fourth resistor R4 is connected to the power supply, and the other end is connected to the pin B2 of the first AND gate U2; the power supply pin (+) of the first AND gate U2 is connected to the power supply; one end of the fourth capacitor C4 is connected to the power supply pin + of the first AND gate U2, and the other

[0070] end is grounded; the ground pin (-) of the first AND gate U2 is grounded. The fourth resistor R4 is a pull-up resistor, and when the pin output of U1 is high impedance, it provides a definite high level for the B channel of the first AND gate U2. The fourth capacitor C4 is a decoupling capacitor for the first AND gate U2, provides a relatively stable power supply for the first AND gate U2, and at the same time reduces the noise coupled by the first AND gate U2 to the power supply terminal. The optoelectronic adaptive selection circuit of this embodiment further includes a fifth resistor R5 and a fifth capacitor C5. One end of the fifth resistor R5 is connected to the power supply, and the other end is connected to the pin B3 of the second AND gate U3; the pin + of the second AND gate U3 is connected to the power supply; one end of the fifth capacitor C5 is connected to the power supply pin (+) of the second AND gate U3, and the other end is grounded; the ground pin (-) of the second AND gate U3 is grounded. The fifth resistor R5 is a pull-up resistor, and when the Q pin of U1 outputs high impedance, it provides a definite high level for the B channel of the second AND gate U3. The fifth capacitor C5 is a decoupling capacitor for the second AND gate U3, provides a relatively stable power supply for the second AND gate U3, and at the same time reduces the noise coupled by the second AND gate U3 to the power supply terminal.

[0071] The optoelectronic adaptive selection circuit of this embodiment further includes a fifth resistor R5 and a fifth capacitor C5. One end of the fifth resistor R5 is connected to the power supply, and the other end is connected to the pin B3 of the second AND gate U3; the pin + of the second AND gate U3 is connected to the power supply; one end of the fifth capacitor C5 is connected to the power supply pin (+) of the second AND gate U3, and the other end is grounded; the ground pin (-) of the second AND gate U3 is grounded. The fifth resistor R5 is a pull-up resistor, and when the Q pin of U1 outputs high impedance, it provides a definite high level for the B channel of the second AND gate U3. The fifth capacitor C5 is a decoupling capacitor for the second AND gate U3, provides a relatively stable power supply for the second AND gate U3, and at the same time reduces the noise coupled by the second AND gate U3 to the power supply terminal.

[0072] The photoelectric adaptive selection circuit of this embodiment further includes a sixth capacitor C6. The power supply pin (+) of the OR gate U4 is connected to the power supply; one end of the sixth capacitor C6 is connected to the power supply pin (+) of the OR gate U4, and the other end is grounded; the ground pin (-) of the OR gate U4 is grounded. The sixth capacitor C6 is a decoupling capacitor for the OR gate U4, providing a relatively stable power supply for the OR gate U4 and reducing the noise coupled by the OR gate U4 to the power supply terminal.

[0073] Whether the photoelectric adaptive selection circuit of this embodiment outputs an optical signal or an electrical signal depends first on whether there is a signal at the optical signal input terminal, that is, the priority of the optical signal is higher than that of the electrical signal. When the optical and electrical input signals are connected simultaneously, the photoelectric adaptive selection circuit can preferentially adopt the optical time synchronization signal with higher transmission quality and less susceptible to interference, effectively guaranteeing the time synchronization accuracy.

[0074] Among them, the output selection circuit is used to selectively weld resistors according to actual needs and output one of the photoelectric adaptive selection signal, optical signal, and electrical signal.

[0075] The output selection circuit of this embodiment includes a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. One end of the sixth resistor R6 is connected to the output pin F4 of the OR gate U4, and the other end is connected to the signal output terminal; one end of the seventh resistor R7 is connected to the optical signal input terminal, and the other end is connected to the signal output terminal; one end of the eighth resistor R8 is connected to the electrical signal input terminal, and the other end is connected to the signal output terminal.

[0076] When the sixth resistor R6 is welded and the seventh resistor R7 and the eighth resistor R8 are not welded, the signal output terminal outputs the photoelectric adaptive selection signal; when the seventh resistor R7 is welded and the sixth resistor R6 and the eighth resistor R8 are not welded, the signal output terminal outputs the optical signal; when the eighth resistor R8 is welded and the sixth resistor R6 and the seventh resistor R7 are not welded, the signal output terminal outputs the electrical signal.

[0077] This embodiment realizes the adaptive recognition of the photoelectric time synchronization signal, improves the compatibility of the secondary power equipment, and enables the equipment to flexibly adapt to different application requirements. Moreover, the generation of the adaptive control signal and the adaptive selection of the photoelectric signal are all completed by the hardware circuit, without occupying additional system resources or consuming additional calculation time, and the recognition of the photoelectric time synchronization signal is faster.

Claims

1. An optoelectronic adaptive time synchronization circuit, characterized in that: Comprising: An adaptive control signal generation circuit, configured to generate an adaptive control signal according to the presence or absence of an optical time alignment signal input; An optoelectronic adaptive selection circuit, configured to select a signal source according to the adaptive control signal; An output selection circuit, configured to output the signal source selected by the optoelectronic adaptive selection circuit; Wherein, the adaptive control signal generation circuit includes a monostable flip-flop; an optical time alignment signal input terminal is connected to an input pin of the monostable flip-flop; an output pin of the monostable flip-flop outputs an optical enable signal, and another output pin of the monostable flip-flop outputs an electrical enable signal. When there is a time alignment signal at the optical time alignment signal input terminal, the optical enable signal is valid and the electrical enable signal is invalid; when there is no time alignment signal at the optical time alignment signal input terminal, the optical enable signal is invalid and the electrical enable signal is valid; Wherein, the optoelectronic adaptive selection circuit includes a first AND gate, a second AND gate, and an OR gate; an input pin of the first AND gate is connected to an output pin of the monostable flip-flop, and another input pin of the first AND gate is connected to the optical time alignment signal input terminal; an input pin of the second AND gate is connected to another output pin of the monostable flip-flop, and another input pin of the second AND gate is connected to an electrical signal input terminal; an output pin of the first AND gate is connected to an input pin of the OR gate; an output pin of the second AND gate is connected to another input pin of the OR gate, and an output pin of the OR gate outputs the selected signal source.

2. The photoelectric self-adaptive time synchronization circuit according to claim 1, wherein: The adaptive control signal generation circuit further includes: a first resistor and a first capacitor; one end of the first resistor is connected to a power supply, and the other end thereof is connected to the Rcext pin of the monostable flip-flop; one end of the first capacitor is connected to the Rcext pin of the monostable flip-flop, and the other end thereof is connected to the Cext pin of the monostable flip-flop; by adjusting the magnitudes of the first resistor and the first capacitor, the time for optical pulse detection is adjusted.

3. The optoelectronic adaptive time synchronization circuit according to claim 1, characterized in that: The adaptive control signal generation circuit further includes a second resistor, a third resistor, and a second capacitor; one end of the second resistor is connected to a power supply, and the other end thereof is connected to the B pin of the monostable flip-flop, for providing a definite high level to the B pin of the monostable flip-flop; one end of the third resistor is connected to a power supply, and the other end thereof is connected to the CLR pin of the monostable flip-flop; one end of the second capacitor C2 is connected to the CLR pin of the monostable flip-flop, and the other end thereof is grounded. The third resistor and the second capacitor form a power-on reset circuit, which generates a reset signal with a certain rising time during power-on.

4. The optoelectronic adaptive time alignment circuit according to claim 1, characterized in that: The adaptive control signal generation circuit further includes a third capacitor, one end of the third capacitor is connected to the VCC pin of the monostable flip-flop, and the other end thereof is connected to the GND pin of the monostable flip-flop; the VCC pin of the monostable flip-flop is connected to a power supply; the GND pin of the monostable flip-flop is grounded.

5. The photoelectric self-adaptive time alignment circuit according to claim 1, wherein: The optoelectronic adaptive selection circuit further includes a fourth resistor and a fourth capacitor; one end of the fourth resistor is connected to a power supply, and the other end thereof is connected to the B2 pin of the first AND gate, for providing a definite high level to the B2 pin of the first AND gate when a high impedance is output from an output pin of the monostable flip-flop; one end of the fourth capacitor is connected to the power supply pin of the first AND gate, and the other end thereof is grounded; The photoelectric adaptive selection circuit further includes a fifth resistor and a fifth capacitor; one end of the fifth resistor is connected to the power supply, and the other end is connected to pin B3 of the second AND gate; one end of the fifth capacitor is connected to the power supply pin of the second AND gate, and the other end is grounded; The photoelectric adaptive selection circuit further includes a sixth capacitor; one end of the sixth capacitor is connected to the power supply pin of the OR gate, and the other end is grounded; The power supply pin of the first AND gate is connected to the power supply, and the grounding pin of the first AND gate is grounded; The power supply pin of the second AND gate is connected to the power supply, and the grounding pin of the second AND gate is grounded; The power supply pin of the OR gate is connected to the power supply, and the grounding pin of the OR gate is grounded.

6. The photoelectric self-adaptive time synchronization circuit according to claim 1, wherein: The output selection circuit includes a sixth resistor, one end of the sixth resistor is connected to the output pin of the OR gate, and the other end is connected to the signal output terminal, for outputting the signal source selected by the photoelectric adaptive selection circuit.

7. An optoelectronic adaptive time alignment circuit according to claim 6, characterized in that: The output selection circuit further includes an optical timing signal output circuit, the optical timing signal output circuit includes a seventh resistor, one end of the seventh resistor is connected to the optical timing signal input terminal, and the other end is connected to the signal output terminal, for outputting an optical timing signal.

8. The optoelectronic self-adaptive time synchronization circuit according to claim 6, wherein: The output selection circuit further includes an electrical timing signal output circuit, the electrical timing signal output circuit includes an eighth resistor, one end of the eighth resistor is connected to the electrical timing signal input terminal, and the other end is connected to the signal output terminal, for outputting an electrical timing signal.

9. An optoelectronic adaptive time synchronization method, characterized in that: Including the following steps: Step 1: According to whether there is an optical timing signal input, an adaptive control signal is generated by the adaptive control signal generation circuit; Step 2: According to the adaptive control signal, the selected signal source is output by the photoelectric adaptive selection circuit; Step 3: Build an output selection circuit to output the selected signal source; Step 4: Perform timing based on the output signal source; Wherein, the adaptive control signal generation circuit includes a monostable flip-flop; the optical timing signal input terminal is connected to an input pin of the monostable flip-flop; an output pin of the monostable flip-flop outputs an optical enable signal, and another output pin of the monostable flip-flop outputs an electrical enable signal. When there is a timing signal at the optical timing signal input terminal, the optical enable signal is valid and the electrical enable signal is invalid; when there is no timing signal at the optical timing signal input terminal, the optical enable signal is invalid and the electrical enable signal is valid; Wherein, the photoelectric adaptive selection circuit includes a first AND gate, a second AND gate and an OR gate; an input pin of the first AND gate is connected to an output pin of the monostable flip-flop, and another input pin of the first AND gate is connected to the optical timing signal input terminal; an input pin of the second AND gate is connected to another output pin of the monostable flip-flop, and another input pin of the second AND gate is connected to the electrical signal input terminal; the output pin of the first AND gate is connected to an input pin of the OR gate; the output pin of the second AND gate is connected to another input pin of the OR gate, and the output pin of the OR gate outputs the selected signal source.

10. A photoelectric adaptive time alignment method according to claim 9, characterized in that: The adaptive control signal generation circuit further includes: a first resistor and a first capacitor; one end of the first resistor is connected to the power supply, and the other end thereof is connected to the pin Rcext of the monostable flip-flop; one end of the first capacitor is connected to the pin Rcext of the monostable flip-flop, and the other end thereof is connected to the pin Cext of the monostable flip-flop; by adjusting the magnitudes of the first resistor and the first capacitor, the time for optical pulse detection is adjusted. The adaptive control signal generation circuit further includes a second resistor, a third resistor and a second capacitor; one end of the second resistor is connected to the power supply, and the other end thereof is connected to the pin B of the monostable flip-flop, for providing a definite high level to the pin B of the monostable flip-flop; one end of the third resistor is connected to the power supply, and the other end thereof is connected to the pin CLR of the monostable flip-flop; one end of the second capacitor C2 is connected to the pin CLR of the monostable flip-flop, and the other end thereof is grounded, and the third resistor and the second capacitor form a power-on reset circuit, generating a reset signal with a certain rise time during power-on. The adaptive control signal generation circuit further includes a third capacitor, one end of the third capacitor is connected to the pin VCC of the monostable flip-flop, and the other end thereof is connected to the pin GND of the monostable flip-flop; the pin VCC of the monostable flip-flop is connected to the power supply; the pin GND of the monostable flip-flop is grounded. The photoelectric adaptive selection circuit further includes a fourth resistor and a fourth capacitor; one end of the fourth resistor is connected to the power supply, and the other end thereof is connected to the pin B2 of the first AND gate, for providing a definite high level to the pin B2 of the first AND gate when a high impedance is output from an output pin of the monostable flip-flop; one end of the fourth capacitor is connected to the power supply pin of the first AND gate, and the other end thereof is grounded. The photoelectric adaptive selection circuit further includes a fifth resistor and a fifth capacitor; one end of the fifth resistor is connected to the power supply, and the other end thereof is connected to the pin B3 of the second AND gate; one end of the fifth capacitor is connected to the power supply pin of the second AND gate, and the other end thereof is grounded. The photoelectric adaptive selection circuit further includes a sixth capacitor; one end of the sixth capacitor is connected to the power supply pin of the OR gate, and the other end thereof is grounded. The power supply pin of the first AND gate is connected to the power supply, and the ground pin of the first AND gate is grounded. The power supply pin of the second AND gate is connected to the power supply, and the ground pin of the second AND gate is grounded. The power supply pin of the OR gate is connected to the power supply, and the ground pin of the OR gate is grounded. The output selection circuit includes a sixth resistor, one end of the sixth resistor is connected to the output pin of the OR gate, and the other end thereof is connected to the signal output end, for outputting the signal source selected by the photoelectric adaptive selection circuit. The output selection circuit further includes an optical timing signal output circuit, the optical timing signal output circuit includes a seventh resistor, one end of the seventh resistor is connected to the optical timing signal input end, and the other end thereof is connected to the signal output end, for outputting an optical timing signal. The output selection circuit further includes an electrical pair timing signal output circuit, and the electrical pair timing signal output circuit includes an eighth resistor. One end of the eighth resistor is connected to the electrical pair timing signal input terminal, and the other end thereof is connected to the signal output terminal for outputting an electrical pair timing signal.

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