A device and method for implementing on-chip learnable physical RC networks

Abstract

This invention discloses an on-chip learning device and method for implementing a physical RC network, belonging to the field of memristor neuromorphic computing systems. This invention is based on a next-generation RC network and implements it in hardware, solving the problem of low parallelism in traditional RC networks. The all-hardware RC network of this invention does not simply perform weight mapping followed by data classification; it also allows for in-situ training. This improves the network's tolerance to noise caused by device nonlinearity and enables it to adaptively adapt to changes in the external environment.

Description

Technical Field

[0001] This invention relates to the field of memristor neuromorphic computing systems, and more specifically to an apparatus and method for implementing an on-chip learnable physical RC network. Background Technology

[0002] Reservoir computing (RC) is a simplified form of RNN. The concept of RC was initially proposed to simulate the process by which the corticostriate system, with its numerous recurrent connections, processes visual spatial sequence information in the biological brain. Subsequently, a unified RC computing framework was constructed based on the RNN framework. The core of RC is a recurrent neural network hidden layer called a "reservoir." This network can transform temporal input signals into a high-dimensional space. After this high-dimensional transformation, the features of the input signal can be more easily and effectively read out using simple linear regression methods.

[0003] Memristors are a type of memory-enabled device that has garnered significant attention in recent years. Cross arrays composed of memristor devices can perform matrix-vector multiplication operations in-situ, in parallel, and physically using Ohm's law and Kirchhoff's laws, effectively reducing data movement during computation and thus offering advantages such as low power consumption and high speed. This invention uses a memristor array as the weights for the final layer. Due to its non-ideal characteristics, a constant pulse update method is employed. The result is a next-generation RC network entirely constructed from hardware circuitry and supporting in-situ training.

[0004] Because memristors have non-ideal characteristics, updating weights using fixed pulses is the most stable method. SBP-moment is an on-chip learning method, but it requires saving the error value obtained from the previous layer each time, necessitating a large number of registers to store floating-point data. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a method and apparatus for implementing on-chip learnable physical RC networks.

[0006] The objective of this invention can be achieved through the following technical methods:

[0007] An implementation device for an on-chip learnable physical RC network, comprising:

[0008] The signal input circuit is configured to receive input signals.

[0009] The storage pool circuit includes a storage pool module comprising storage pool units. Each storage pool unit is configured to receive the input signal and pass the input signal through an analog multiplier to obtain the product between the inputs. The analog multipliers are arranged into a matrix shape, with the same input signal used on the top and left sides of each analog multiplier. The result is taken from the upper triangular part of each multiplier matrix to obtain a first processing result. The first processing result and the input signal are then concatenated by a vector operation to obtain a second processing result. The second processing result is then multiplied by a constant memristor array to perform a dimension reduction operation, resulting in a third processing result.

[0010] The output layer unit is configured to multiply the multiple third processing results of the multiple reserve pool units with the weight matrix to obtain a fourth processing result, and output the fourth processing result.

[0011] In some disclosures, the output layer unit includes a weight matrix, a backpropagation circuit, a cross-entropy circuit, and a storage logic circuit. Multiple third processing results are passed through the weight matrix, and the class probability is output through the softmax circuit. The cross-entropy circuit calculates the error of the input probability to obtain the updated sign of the weight. If the sign is positive, a positive pulse is applied to the device, and the weight decreases; if the sign is negative, a negative pulse is applied to the device, and the weight increases.

[0012] In some disclosures, the cross-entropy circuit calculates the error of the input probability, and the cross-entropy formula is shown in formulas (1) and (2).

[0013]

[0014]

[0015] Formula (2) is the softmax calculation formula; the cross-entropy circuit calculates the logarithm by adopting the principle of equivalent substitution; firstly, the logarithm lnx is Taylor-spread at x=1, as shown in formula (3);

[0016]

[0017] Ignoring higher-order terms, we take the first term. Then, the output error voltage is compared with a given threshold voltage by a comparator. If it is smaller than the threshold voltage, the output is low. Finally, a counter is used to determine whether the training has converged. If it has converged, the training stops.

[0018] In some disclosures, the backpropagation circuit is described as follows: the update direction of the weight matrix depends on the sign of the backpropagation gradient. First, during forward propagation, the input data is the second processing result, the weight matrix is ​​G, and the output voltage vector obtained by Kirchhoff's laws is the third processing result. Then, through formula 2, the final output probability is obtained. The output probability is then processed by the cross-entropy calculation circuit to obtain the error value. Therefore, the sign of the derivative of backpropagation depends on the derivative of the error value with respect to each weight.

[0019] The principle is shown in formula (4).

[0020]

[0021] Where L is the error obtained after cross-entropy. C is the output of the Softmax circuit, which is the input of the Softmax circuit, i.e., the output after passing through the weight matrix. W is the weight matrix G, and X is the data of the input weight matrix, which is the second processing result. Finally, the sign of each direction propagation depends on the input voltage. The second processing result is the update matrix obtained by the logic circuit between the softmax output Y and the target label.

[0022] In some publications, the cross-entropy backpropagation circuit calculates the error for each category by adding a threshold to accelerate the convergence of the algorithm; that is, updates are only performed when the error exceeds this threshold. Therefore, formula (4) needs to be modified to some extent. Formula 5 is obtained.

[0023]

[0024] Where B is The difference is compared with a threshold to determine the error update status: 1 indicates an update, and 0 indicates no update.

[0025] In some disclosures, the purpose of the storage logic circuit is to store the previous update state, by using two memristors to store the update state of a weight.

[0026] A method for implementing an on-chip learnable physical RC network, used in the aforementioned implementation apparatus for an on-chip learnable physical RC network, includes the following steps: performing inference computation operations using the implementation apparatus for an on-chip learnable physical RC network; or performing training computation operations using the implementation apparatus for an on-chip learnable physical RC network.

[0027] The inference calculation operation includes: receiving an input signal for the inference calculation operation through the signal input circuit; multiplying the input signal with the product obtained by passing the input signal through an analog multiplier through the reservoir circuit, arranging the analog multipliers into a matrix shape, using the same input signal on the top and left sides of the analog multipliers, taking the upper triangular part of each multiplier matrix to obtain a first processing result, combining the first processing result and the input signal to form a second processing result, and then performing matrix multiplication of the second processing result with a constant memristor array to perform a dimensionality reduction operation to obtain a third processing result;

[0028] The output layer unit multiplies the multiple third processing results with the weight matrix to obtain the fourth processing result, and then outputs the fourth processing result.

[0029] The training computation operations include:

[0030] The signal input circuit receives the input signal for the training calculation operation and the label value for the input signal.

[0031] The input signal is multiplied by the input signal obtained by passing the input signal through an analog multiplier. The analog multipliers are arranged into a matrix shape. The same input signal is used on the top and left sides of the analog multipliers. The result is taken from the upper triangular part of each multiplier matrix to obtain the first processing result. The first processing result and the input signal are combined to form the second processing result. Then, the second processing result is multiplied by the constant memristor array to perform a dimension reduction operation and obtain the third processing result.

[0032] The output layer unit multiplies the multiple third processing results with the weight matrix to obtain the fourth processing result, and then outputs the fourth processing result.

[0033] The error of the weight matrix is ​​calculated based on the multiple fourth processing results and the label value of the training input signal to update the weight matrix; the updated weight matrix is ​​then written into the output layer unit.

[0034] The beneficial effects of this invention: Currently, RC networks primarily process data through physical storage layers before training, resulting in data processing and training occurring at different times and requiring numerous registers to store historical states. To address this issue, this invention proposes an implementation device for RC networks based on next-generation RC networks, implementing it in hardware and solving the problem of low computational parallelism in traditional RC networks. This invention's all-hardware RC network does not simply involve weight mapping followed by data classification; it also allows for in-situ training. This improves the network's tolerance to noise caused by device nonlinearity and enables adaptive changes to external environmental conditions. Attached Figure Description

[0035] The invention will now be further described with reference to the accompanying drawings.

[0036] Figure 1 This is a system architecture diagram of this application;

[0037] Figure 2 This is the Softmax circuit of this application;

[0038] Figure 3 This is the cross-entropy calculation circuit of this application;

[0039] Figure 4 This is the cross-entropy backpropagation circuit of this application;

[0040] Figure 5 This is the storage logic diagram of this application;

[0041] Figure 6 This is the update logic diagram for this application;

[0042] Figure 7 This is a comparison chart of the results of this application; Detailed Implementation

[0043] The technical methods of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] An apparatus and method for implementing an on-chip learnable physical RC network, comprising:

[0045] The signal input circuit is configured to receive input signals.

[0046] The storage pool circuit includes storage pool units. Each storage pool unit is configured to receive the input signal and multiply the input signal using an analog multiplier to obtain the product between the inputs. The analog multipliers are arranged into a matrix shape, with the same input signal used on the top and left sides of each multiplier. The result is taken from the upper triangular part of each multiplier matrix to obtain a first processing result. The first processing result and the input signal are then concatenated by a vector operation to obtain a second processing result. The second processing result is then multiplied by a constant memristor array to perform dimensionality reduction, resulting in a third processing result. This array mainly utilizes the randomness of memristors. By writing the same weights into the memristors, due to the variability between memristors, a normally distributed weight array is obtained. The dimensionality reduction operation here mainly utilizes the random projection theorem. Generally, data is collected, representing some features over a time period. Through a delay circuit, feature points at different time periods are obtained, and through a signal encoding circuit, the Vn signal is obtained.

[0047] The output layer unit is configured to multiply the multiple third processing results of the multiple reserve pool units with the weight matrix to obtain a fourth processing result, and output the fourth processing result.

[0048] A method for implementing an on-chip learnable physical RC network, used in the aforementioned implementation apparatus for an on-chip learnable physical RC network, includes the following steps: performing inference computation operations using the implementation apparatus for an on-chip learnable physical RC network; or performing training computation operations using the implementation apparatus for an on-chip learnable physical RC network.

[0049] The inference calculation operation includes: receiving an input signal for the inference calculation operation through the signal input circuit; multiplying the input signal with the product obtained by passing the input signal through an analog multiplier through the reservoir circuit, arranging the analog multipliers into a matrix shape, using the same input signal on the top and left sides of the analog multipliers, taking the upper triangular part of each multiplier matrix to obtain a first processing result, combining the first processing result and the input signal to form a second processing result, and then performing matrix multiplication of the second processing result with a constant memristor array to perform a dimensionality reduction operation to obtain a third processing result;

[0050] The output layer unit multiplies the multiple third processing results with the weight matrix to obtain the fourth processing result, and then outputs the fourth processing result.

[0051] The training computation operations include:

[0052] The signal input circuit receives the input signal for the training calculation operation and the label value for the input signal.

[0053] The input signal is multiplied by the input signal obtained by passing the input signal through an analog multiplier. The analog multipliers are arranged into a matrix shape. The same input signal is used on the top and left sides of the analog multipliers. The result is taken from the upper triangular part of each multiplier matrix to obtain the first processing result. The first processing result and the input signal are combined to form the second processing result. Then, the second processing result is multiplied by the constant memristor array to perform a dimension reduction operation and obtain the third processing result.

[0054] The output layer unit multiplies the multiple third processing results with the weight matrix to obtain the fourth processing result, and then outputs the fourth processing result.

[0055] The error of the weight matrix is ​​calculated based on the multiple fourth processing results and the label value of the training input signal to update the weight matrix; the updated weight matrix is ​​then written into the output layer unit.

[0056] Hardware components, such as Figure 1 As shown in the figure, this is a block diagram of the entire system. The system acquires the analog voltage signal V from the sensor. linear First, we obtain the product between inputs using simulated multipliers (e.g., x1, x2 => x1*x2, x1*x1, x2*x2). Here, we arrange the simulated multipliers into a matrix shape, using the same inputs on the top and left sides. The result is taken from the upper triangular part of each multiplier matrix, resulting in V. nonlinear Then V linear With V nonlinear The vector concatenation operation yields a new voltage vector V. t1 Then V t1 Performing matrix multiplication with a constant memristor array to reduce its dimension yields V. t2 The constant array utilizes the randomness of memristors, whose conductance follows a normal distribution.

[0057] Finally, the training part mainly consists of four components: the weight matrix, the backpropagation circuit, the cross-entropy circuit, and the storage logic circuit. This is achieved by obtaining the voltage vector V from the previous layer. t2 After passing through the weight matrix, the softmax circuit outputs the class probabilities, and the cross-entropy circuit calculates the error of the input probabilities to obtain the sign of the updated weights. A positive sign applies a positive pulse (Set) to the device, decreasing the weights; a negative sign applies a negative pulse (ReSet), increasing the weights. The storage logic circuit stores the previously updated state.

[0058] 2. In-situ training section

[0059] The cross-entropy circuit, the cross-entropy formula is shown in formulas (1) and (2).

[0060]

[0061]

[0062] Formula (2) is the softmax calculation formula. The circuit can be obtained based on this formula. Figure 2 , Figure 3 . Figure 2 Equation 2 shows that by passing the input data through an exponential circuit to obtain the exponential output, denoted as the first output Vi, we obtain the numerator of Equation 2. This numerator is then passed through a non-inverting adder composed of an integrated operational amplifier to obtain Vsum, denoted as the second output, which is the denominator. Finally, the first and second outputs are divided sequentially to obtain the softmax output. The exponential part is a commonly used circuit for suppressing temperature drift and generating an exponential signal output, primarily utilizing the exponential relationship between the base current and collector current of the transistor.

[0063] Figure 3 The logarithm of the cross-entropy circuit is calculated using the principle of equivalent substitution. It is mainly obtained through formula (1). First, formula (2) is substituted into formula (1) for simplification. Considering that y is composed of one-hot encoding and can only take values ​​of 0 and 1, the final simplified result is...

[0064]

[0065] because The output of Vsum from circuit 2 can be used to perform a Taylor expansion of lnx using formula (3), so the final simplified result is:

[0066]

[0067] The adder circuit consisting of the first operational amplifier yields 1 + x. i One of them is used as the reference current Vref as input.

[0068] The second operational amplifier is used as a subtractor to ultimately obtain the error L, and the voltage comparator is used to determine whether the algorithm has converged.

[0069] First, the logarithm lnx is Taylor-spanned at x=1, as shown in formula (3).

[0070]

[0071] We ignore higher-order terms and take the first term. The output error voltage is then compared to a given threshold voltage by a comparator; if it's smaller, a low level is output. Finally, a counter determines whether training has converged; if convergence is achieved, training stops.

[0072] Backpropagation circuit: The update direction of the weight matrix depends on the sign of the backpropagation gradient. First, during forward propagation, the input data is V. t2 The weight matrix is ​​G, and the output voltage vector is V obtained from Kirchhoff's laws. t3 Then, according to Formula 2, Figure 2 The circuit shown yields the final output probability. Then, the output probability is processed... Figure 3 The circuit shown yields the error value, therefore the sign of the derivative of the backpropagation depends on the derivative of the error value with respect to each weight.

[0073] The principle is shown in formula (4).

[0074]

[0075] Where L is the error obtained after cross-entropy. The output of the Softmax circuit is represented by C, which is the input of the Softmax circuit (i.e., the output after passing through the weight matrix). W is the weight matrix G, and X is the data input to the weight matrix, which is V. t2 Ultimately, the sign of the propagation in each direction depends on the input voltage V. t2 The update matrix is ​​obtained by logic circuitry from the difference between the softmax output Y and the target label. For example... Figure 4 As shown, Vo is the voltage signal output by softmax, and Vc is a one-hot encoded input vector with only 0 and 1. The 1 index represents the label size. The actual loss of the target label is filtered out by the select target part. The loss of other labels is the actual output probability, which is obtained by controlling the Vc signal. The input of each data is processed by the network to obtain the final label loss. In order to accelerate the convergence of network training, a threshold voltage is used to determine whether the loss needs to be updated. When calculating the error of each category, a threshold is added to speed up the convergence of the algorithm. That is, updates are only performed when the error is higher than this threshold. Therefore, formula (4) needs to be modified. Formula 5 is obtained.

[0076]

[0077] Where B is The difference is compared with a threshold to determine the error update status: 1 indicates an update, and 0 indicates no update.

[0078] Storage logic circuit: The purpose of this circuit is to store the previous update state. Here, two memristors are used to store the update state of a weight, such as... Figure 5 As shown, two memristors are used to store historical states. By inputting voltages of opposite signs at the same time, the circuit outputs 0 if both memristors are simultaneously in a high-resistance state, based on the voltage divider principle of series resistors. The output voltages will tend towards negative or positive depending on the high / low state of the two memristors. A voltage comparator is used to obtain 1-0 and 0-1 outputs respectively. If R1 and R2 are simultaneously in high and low resistance states, the output is stored as Set; if R1 and R2 are simultaneously in low and high resistance states, the output is stored as ReSet; if R1 and R2 are simultaneously in high and high resistance states, the output is stored without updating. V+ and V- are the logic voltages obtained through the positive and negative voltage comparator, which are then processed by the logic circuit to obtain the stored information.

[0079] Figure 6 For the update logic circuit obtained based on Equation 5, Vi is the voltage symbol input to the weight array, X is the input signal (positive represents 1, negative represents 0), and Ve is the error symbol. The sign of the interpolation, Vec, is determined by the voltage threshold and the output sign. B determines whether an update is performed. Vhset and Vhreset are... Figure 5 The final Vset and Vreset are obtained by reading the historical state, which is the logic signal obtained from the storage logic circuit, and are determined by Set and Reset respectively.

[0080]

[0081]

[0082] Table 1. Update Logic Table

[0083] The table above shows the update state table, where 1 represents Set, -1 represents ReSet, 0 represents no update, History is an update state stored on the memristor array, Current is the current update state calculated according to formula (5), and the Update column represents the final update state.

[0084] This invention mainly provides an RC network implementation device for next-generation RC networks, which mainly includes two aspects: hardware implementation method and in-situ training method. The hardware implementation method reduces power consumption and improves computing speed compared to software. The in-situ training method is adopted in hardware, and improvements are made to the original in-situ training method, and specific circuit implementation is given.

[0085] This patent provides a hardware implementation method based on next-generation RC networks. To demonstrate the feasibility and practicality of this method, we tested it on the MNIST handwritten digit recognition task. Simulation results show that the system using this method achieves an accuracy of 93.1% after four training iterations. Compared to existing methods, simulation verification shows a 10% improvement in test accuracy after training. The final results are compared with the SBP-moment algorithm, as shown below. Figure 7 As shown in the figure, this figure mainly compares the SBP-moment algorithm in terms of hardware design, comparing the original hardware design with this design, the number of training data, and the final test accuracy.

[0086] In the description of this invention, it should be understood that the terms "opening", "upper", "lower", "thickness", "top", "middle", "length", "inner", "around", etc., which indicate orientation or positional relationship, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this invention.

[0087] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0088] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A device for implementing an on-chip learnable physical RC network, characterized in that, include: The signal input circuit is configured to receive input signals. A reservoir circuit includes reservoir units, each reservoir unit being configured to receive the input signal and pass the input signal through an analog multiplier to obtain the product between the inputs. The analog multipliers are arranged into a matrix shape, with the same input signal used on the top and left sides of the analog multipliers. The result is taken from the upper triangular part of each multiplier matrix to obtain a first processing result. The first processing result and the input signal are then concatenated by a vector operation to obtain a second processing result. The second processing result is then multiplied by a constant memristor array to perform a dimension reduction operation, resulting in a third processing result. The output layer unit is configured to multiply multiple third processing results from multiple reserve pool units with a weight matrix to obtain a fourth processing result, and then output the fourth processing result. The output layer unit includes a weight matrix, a backpropagation circuit, a cross-entropy circuit, and a storage logic circuit. Multiple third-processing results are processed through the weight matrix, and the class probability is output through the softmax circuit. The cross-entropy circuit calculates the error of the input probability to obtain the updated sign of the weight. If the sign is positive, a positive pulse is applied to the device, and the weight decreases; if the sign is negative, a negative pulse is applied to the device, and the weight increases.

2. The apparatus for implementing an on-chip learnable physical RC network according to claim 1, characterized in that, The cross-entropy circuit calculates the error of the input probability, and the cross-entropy formula is shown in formulas (1) and (2): Formula (2) is the softmax calculation formula, where L is the final error value and y is the target label value. The output of formula (2) is given; the cross-entropy circuit calculates the logarithm by adopting the principle of equivalent substitution; firstly, the logarithm lnx is expanded by Taylor at x=1, as shown in formula (3); x is actually the output of formula (2), but this formula only represents the Taylor expansion of the logarithm and does not belong to the system formula; ignore the higher-order terms and take the first term; then the output error voltage is compared with the given threshold voltage by the comparator. If it is smaller than the threshold voltage, the output is low level; finally, the counter is used to determine whether the training has converged. If it has converged, the training is stopped.

3. The apparatus for implementing an on-chip learnable physical RC network according to claim 1, characterized in that, The backpropagation circuit includes: the update direction of the weight matrix depends on the sign of the backpropagation gradient. First, during forward propagation, the input data is the second processing result, the weight matrix is ​​G, and the output voltage vector obtained by Kirchhoff's law is the third processing result. Then, through formula (2), the final output probability is obtained. Then, the output probability is processed by the cross-entropy calculation circuit to obtain the error value. Therefore, the sign of the derivative of backpropagation depends on the derivative of the error value with respect to each weight. The principle is shown in formula (4): （4） Where L is the error obtained after cross-entropy. C is the output of the Softmax circuit, which is the input of the Softmax circuit, i.e., the output after passing through the weight matrix. W is the weight matrix G, X is the data of the input weight matrix, which is the second processing result, and Y is the tag value. All the variable data in this formula are in matrix form. Finally, the sign of propagation in each direction depends on the input voltage. The second processing result is the update matrix obtained by the logic circuit between the softmax output Y and the target tag.

4. The apparatus for implementing an on-chip learnable physical RC network according to claim 3, characterized in that, When the backpropagation circuit calculates the error for each category, a threshold is added to speed up the convergence of the algorithm; that is, updates are only performed when the error exceeds this threshold. Therefore, formula (4) needs to be modified to obtain formula (5): Where B is The obtained difference is mainly composed of 0-1, and all variables in the formula are matrices; after threshold comparison, the error update status is obtained, 1 means update, and 0 means no update.

5. The apparatus for implementing an on-chip learnable physical RC network according to claim 1, characterized in that, The purpose of the storage logic circuit is to store the previous update state, which is achieved by using two memristors to store the update state of a weight.

6. A method for implementing an on-chip learnable physical RC network, characterized in that, An apparatus for implementing an on-chip learnable physical RC network according to any one of claims 1-5 includes the following steps: performing inference computation operations using the apparatus for implementing the on-chip learnable physical RC network; or performing training computation operations using the apparatus for implementing the on-chip learnable physical RC network.

7. The method for implementing an on-chip learnable physical RC network according to claim 6, characterized in that, The inference calculation operation includes: receiving an input signal for the inference calculation operation through the signal input circuit; multiplying the input signal with the product obtained by passing the input signal through an analog multiplier through the reservoir circuit, arranging the analog multipliers into a matrix shape, using the same input signal on the top and left sides of the analog multipliers, taking the upper triangular part of each multiplier matrix to obtain a first processing result, combining the first processing result and the input signal to form a second processing result, and then performing matrix multiplication of the second processing result with a constant memristor array to perform a dimensionality reduction operation to obtain a third processing result; The output layer unit multiplies multiple third processing results with the weight matrix to obtain the fourth processing result, and then outputs the fourth processing result.

8. The method for implementing an on-chip learnable physical RC network according to claim 6, characterized in that, The training computation operations include: The signal input circuit receives the input signal for the training calculation operation and the label value for the input signal. The input signal is multiplied by the input signal obtained by passing the input signal through an analog multiplier. The analog multipliers are arranged into a matrix shape. The same input signal is used on the top and left sides of the analog multipliers. The result is taken from the upper triangular part of each multiplier matrix to obtain the first processing result. The first processing result and the input signal are combined to form the second processing result. Then, the second processing result is multiplied by the constant memristor array to perform a dimension reduction operation and obtain the third processing result. The output layer unit multiplies multiple third processing results with the weight matrix to obtain the fourth processing result, and then outputs the fourth processing result. The error of the weight matrix is ​​calculated based on multiple fourth processing results and the label values ​​of the training input signal to update the weight matrix; the updated weight matrix is ​​then written into the output layer unit.

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