A timing diagram verification method based on graph theory algorithm

Abstract

The present invention relates to the technical field of timing diagram processing, and discloses a timing diagram verification method based on a graph theory algorithm, the method comprising the following steps: step S1. obtaining a process set of a process flow; step S2. obtaining a process set of a timing diagram; step S3. using a set difference operation to verify whether the timing diagram has free nodes; step S4. converting the timing diagram into a directed graph data structure; step S5. using a directed graph depth-first traversal algorithm to verify whether the timing diagram has multiple entrances and multiple exits; step S6. using a directed graph topological sorting to calculate the timing diagram and verify whether the timing diagram has a loop; step S7. if steps S3, S5, and S6 all pass the verification, it indicates that there is no problem with the timing diagram; otherwise, there is a problem with the timing diagram. The method completes the rationality verification of the timing diagram during the AO and FO compilation process, avoiding the discovery of problems during the assembly and manufacturing process, and avoiding the need to spend a lot of time on coordination, modification, and problem handling.

Description

Technical Field

[0001] The present invention relates to the technical field of timing diagram processing, and in particular to a timing diagram verification method based on a graph theory algorithm. Background Art

[0002] In the manufacturing industry, due to the complexities of part manufacturing and assembly, a manufacturing outline (FO) and assembly outline (AO) are required to guide the processing and assembly of parts. The manufacturing and assembly processes are executed based on the timing diagrams of the AO and FO. Currently, during the AO and FO preparation phase, the timing diagrams are not verified for irrationality. Most issues with the timing diagrams are discovered during execution, and then process personnel propose on-site changes, freezing the executing AO and FO. After completing the modifications to the AO and FO timing diagrams, the review process must be re-entered. Only after the process review is complete can the manufacturing and assembly of parts continue.

[0003] Therefore, since the rationality of the timing diagram is not verified during the current AO and FO preparation stages, if problems are found during the parts manufacturing and assembly process, it will take a lot of time to coordinate, modify and deal with the problems, which will seriously affect the manufacturing and assembly efficiency of the product and even affect the quality of the product. Summary of the Invention

[0004] In order to solve the problems and shortcomings in the above-mentioned prior art, the present invention provides a timing diagram verification method based on graph theory algorithm. This method completes the rationality verification of the timing diagram during the AO and FO compilation process, thereby improving the manufacturing and assembly efficiency of the product.

[0005] In order to achieve the above-mentioned object of the invention, the technical solution of the present invention is as follows:

[0006] A timing diagram verification method based on a graph theory algorithm specifically includes the following steps:

[0007] Step S1. Obtain a process set of the process flow;

[0008] Step S2. Obtain a process set of the timing diagram;

[0009] Step S3. Use set difference operation to check whether there are free nodes in the timing diagram;

[0010] Step S4. Converting the sequence diagram into a directed graph data structure;

[0011] Step S5. Use the directed graph depth-first traversal algorithm to check whether the timing graph has multiple entries and exits;

[0012] Step S6. Calculate the timing graph using directed graph topology sorting to check whether there is a loop in the timing graph;

[0013] Step S7. If step S3, step S5 and step S6 all pass the verification, it means that there is no problem with the timing diagram; otherwise, there is a problem with the timing diagram.

[0014] Preferably, the step S1 includes: traversing the process steps to obtain a process set A, a set

[0015] Preferably, the step S2 includes: traversing the time sequence graph, and then obtaining a non-empty vertex set V(T) of the time sequence graph, a non-empty edge set E(T) and a time sequence graph correlation function A collection of processes including .

[0016] Preferably, in step S3, the calculation expression of the set difference operation is as follows:

[0017] B = V(T) - A;

[0018] If the collection This means that there are no free nodes in the timing diagram being verified, and the verification is passed;

[0019] If the collection This means that there are free nodes in the timing diagram being verified at this time, and the verification fails.

[0020] Preferably, the step S4 includes: constructing a sequence diagram set The time sequence graph is converted into a directed graph data structure through this set, where V(T) is the non-empty vertex set of the time sequence graph, and E(T) is the non-empty edge set of the time sequence graph. is the correlation function of the timing diagram;

[0021]

[0022] further, It can be abbreviated as e=uv.

[0023] Preferably, step S5 includes:

[0024] For the starting node V(T s ),like This means that there are multiple entries in the timing diagram and the verification fails. Indicates in-degree;

[0025] For the terminal node V(T e ),like This means that there are multiple exits in the timing diagram and the verification fails. Indicates degree.

[0026] Preferably, step S6 includes:

[0027] For the time sequence graph set T, the depth-first traversal algorithm is used to traverse the time sequence graph set T and calculate the in-degree of each point in the set. Let this point be vertex v i , delete the vertex and its corresponding edge in the time series graph set T, the operation is recorded as D(Tv i ) and D(Te i );

[0028] Recalculate the fixed point v i The in-degree of the adjacent vertex is denoted by in, Represents vertex v i The in-degree of adjacent vertices;

[0029] Repeat the above steps until all points in the set are traversed. This means that there is a loop in the timing diagram and the verification fails.

[0030] Preferably, the method of the present invention further comprises the following steps:

[0031] Step S8. Constructing process flow features based on the process set obtained in step S1;

[0032] Step S9. Complete the process feature coding;

[0033] Step S10: Implementing the recommendation of the time series diagram based on the KNN algorithm.

[0034] Preferably, step S8 includes: constructing a process flow feature based on the process set obtained in step S1, denoted as H(c), and the data structure of H(c) is as follows:

[0035] H(c) = {"Prepare","Drill","Install","Inspect","Cleaning","..."};

[0036] The data structure of H(c) is converted into decimal code. Each process name corresponds to only one decimal code. The process flow characteristics after conversion are recorded as H(c)'.

[0037] Preferably, the step S9 includes: performing binary encoding on H(c)' using a radix remainder method to complete feature encoding, which is recorded as H(en).

[0038] Preferably, the step S10 includes:

[0039] The zero-filling method is used to fill in the features of H(en) to make the data dimension consistent, which is recorded as x;

[0040] Using Euclidean calculations It is the historical data of process flow;

[0041] like Recommend x i Corresponding timing diagram.

[0042] Beneficial effects of the present invention:

[0043] This invention addresses the current situation in which timing diagrams are not verified for rationality during the AO and FO compilation stages. Instead, it proposes a timing diagram verification method based on graph theory algorithms. Based on graph traversal and directed graph topological sorting algorithms, combined with set operations and the machine learning KNN algorithm, this invention constructs a set of verification and recommendation methods suitable for timing diagrams. This method verifies the rationality of timing diagrams during the AO and FO compilation process, avoiding the discovery of problems during assembly and manufacturing, which would otherwise require significant time for coordination, modification, and resolution. Therefore, the method improves product manufacturing and assembly efficiency, while also enhancing product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The foregoing and following detailed description of the present invention will become more apparent when read in conjunction with the following drawings, in which:

[0045] Figure 1 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the following will further illustrate the technical solutions for achieving the purpose of the present invention through several specific embodiments. It should be noted that the technical solutions claimed for protection by the present invention include but are not limited to the following embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] In the manufacturing industry, due to the complexities of part manufacturing and assembly, a manufacturing outline (FO) and assembly outline (AO) are required to guide the processing and assembly of parts. The manufacturing and assembly processes are executed based on the timing diagrams of the AO and FO. Currently, during the AO and FO preparation phase, the timing diagrams are not verified for irrationality. Most issues with the timing diagrams are discovered during execution, and then process personnel propose on-site changes, freezing the executing AO and FO. After completing the modifications to the AO and FO timing diagrams, the review process must be re-entered. Only after the process review is complete can the manufacturing and assembly of parts continue.

[0048] Therefore, since the rationality of the timing diagram is not verified during the current AO and FO preparation stages, if problems are found during the parts manufacturing and assembly process, it will take a lot of time to coordinate, modify and deal with the problems, which will seriously affect the manufacturing and assembly efficiency of the product and even affect the quality of the product.

[0049] Based on this, an embodiment of the present invention provides a timing diagram verification method based on a graph theory algorithm. This method completes the rationality verification of the timing diagram during the AO and FO compilation process, avoiding problems found during the assembly and manufacturing process, and spending a lot of time on coordination, modification and processing of problems.

[0050] First, it should be noted that the manufacturing outline (FO) and assembly outline (AO) are collectively referred to as process specifications, and both include their own process flows and timing diagrams. The method of the present invention is applicable to both the timing diagrams of the assembly outline (i.e., the AO timing diagram) and the timing diagrams of the manufacturing outline (i.e., the FO timing diagram). In other words, both the AO timing diagram and the FO timing diagram can be verified using the verification method of the present invention to determine if they are qualified. The verification method for both timing diagrams is the same.

[0051] It should also be noted that the method of the present invention verifies the timing diagrams on a per-timing basis. If multiple AO or FO timing diagrams need to be verified, the method of the present invention must be executed multiple times to verify each timing diagram.

[0052] The embodiment of the present invention discloses a timing diagram verification method based on graph theory algorithm. Figure 1 As shown, the details are as follows.

[0053] Step S1. Obtain the process set of the process flow

[0054] In this embodiment, the processes included in the process flow are traversed by the traversal method, and the processes are put into a set to obtain a corresponding process set, which is recorded as set A.

[0055] Step S2. Get the process set of the timing diagram

[0056] In this embodiment, the timing graph to be verified is traversed to obtain a non-empty vertex set V(T) of the timing graph, a non-empty edge set E(T) and a timing graph correlation function A collection of processes including .

[0057] Step S3. Use set difference operation to check whether there are free nodes in the timing diagram

[0058] In this embodiment, the set difference operation is performed using the following calculation expression:

[0059] B = V(T) - A;

[0060] If the collection This means that there are no free nodes in the timing diagram being verified, and the verification is passed;

[0061] If the collection This means that there are free nodes in the timing diagram being verified at this time, and the verification fails.

[0062] Step S4. Convert the sequence diagram into a directed graph data structure

[0063] In this embodiment, by constructing a sequence diagram set The timing graph to be verified is converted into a directed graph data structure, where V(T) is the non-empty vertex set of the timing graph, and E(T) is the non-empty edge set of the timing graph. is the correlation function of the timing diagram;

[0064] Furthermore, e∈E(T), (u,v)∈V(T)×V(T), |E(T)|<+∞, |V(T)|<+∞;

[0065] So, It can be abbreviated as e=uv.

[0066] Step S5. Use the directed graph depth-first traversal algorithm to check whether there are multiple entrances and exits in the timing diagram

[0067] In this embodiment, the constructed time sequence graph set T is subjected to out-degree and in-degree operations to verify whether the time sequence graph is qualified, as follows.

[0068] For the starting node V(T s ),like This means that there are multiple entries in the timing diagram and the verification fails. Indicates in-degree;

[0069] For the terminal node V(T e ),like This means that there are multiple exits in the timing diagram and the verification fails. Indicates degree.

[0070] Step S6. Use directed graph topology sorting to calculate the timing graph and check whether there is a loop in the timing graph.

[0071] In this embodiment, for the constructed time sequence graph set T, the time sequence graph set T is traversed by the depth-first traversal algorithm, and the in-degree of each point in the set is calculated. Let this point be vertex v i , and delete the vertex and its corresponding edge in the time series graph set T at the same time. The operation is recorded as D(Tv i ) and D(Te i ); where D(Tv i ) means deleting vertex v from the time series graph set T i, D(Te i ) means deleting vertex v from the time series graph set T i corresponding edges;

[0072] Recalculate the fixed point v by the following calculation expression i In-degree of adjacent vertices:

[0073]

[0074] in, Represents vertex v i The in-degree of adjacent vertices; Represents vertex v i The in-degree of

[0075] Repeat the above steps until all points in the set are traversed. This means that there is a loop in the timing diagram and the verification fails.

[0076] Step S7. By executing the above verification steps, if steps S3, S5 and S6 all pass the verification, it means that there is no problem with the timing diagram and the timing diagram verification is qualified; otherwise, it means that there is a problem with the timing diagram and the verification fails.

[0077] Furthermore, to address the problem of unqualified timing diagram verification, this embodiment also provides a timing diagram recommendation method based on the KNN algorithm, including the following steps:

[0078] Step S8. Based on the process flow process set obtained in step S1, the process flow characteristics are constructed. The process flow characteristics are recorded as H(c). The data structure of H(c) is as follows:

[0079] H(c) = {"Prepare","Drill","Install","Inspect","Cleaning","..."};

[0080] Convert the data structure of H(c) into decimal code. Each process name corresponds to only one decimal code. The converted timing diagram feature is recorded as H(c)'. The data structure is as follows

[0081] H(c)′={1,2,3,4,5...}.

[0082] Step S9. Complete process feature coding

[0083] The converted H(c)' is binary-encoded using the radix remainder method to complete the feature encoding, which is recorded as H(en). The encoding of H(en) is as follows

[0084] H(en)={"00000001","00000010","00000011","00000100","..."}.

[0085] Step S10: Recommendation of time series diagram based on KNN algorithm

[0086] The zero-filling method is used to fill in the features of H(en) after feature encoding to make the data dimension consistent, which is recorded as x;

[0087] x={"00000001","00000010","00000011","00000000","..."};

[0088] The Euclidean algorithm is used to calculate the similarity of the process flow. The calculation expression is as follows:

[0089]

[0090] in, i is the historical data set of process flow; x is the current process flow;

[0091] In some calculation results, if Recommend x i Corresponding timing diagram.

[0092] In this embodiment, the KNN algorithm in step S10 may also be replaced by a BP neural network to achieve the recommendation of the time sequence diagram, as follows:

[0093] For historical process x i , complete the labeling process to form a new training data set. The data structure is as follows:

[0094] x'={x i ,l i}, i = 0, 1, 2…n;

[0095] Among them, l i is x i The label of the corresponding timing diagram;

[0096] The BP neural network is used to train x' to obtain the model m = f(n). After x is brought into the model, a time series diagram of the category l' = f(x) is recommended.

[0097] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification or equivalent change made to the above embodiment based on the technical essence of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A timing diagram verification method based on graph theory algorithm, characterized in that: The specific steps include: Step S1. Obtain a process set of the process flow; Step S2. Obtain a process set of the timing diagram; Step S3. Use set difference operation to check whether there are free nodes in the timing diagram; Step S4. Converting the sequence diagram into a directed graph data structure; Step S5. Use the directed graph depth-first traversal algorithm to check whether the timing graph has multiple entries and exits; Step S6. Calculate the timing graph using directed graph topology sorting to check whether there is a loop in the timing graph; Step S7. If steps S3, S5, and S6 all pass the verification, it means that there is no problem with the timing diagram; otherwise, there is a problem with the timing diagram; The step S3 includes: the calculation expression of the set difference operation is as follows ； in, A set of steps that represent a process flow; Represents a non-empty vertex set of a timing graph; If the collection , it means that there is no free node in the timing diagram and the verification passes; If the collection , it means that there are free nodes in the timing diagram and the verification fails; The step S4 includes: constructing a timing diagram set , through which the sequence graph is converted into a directed graph data structure; is a non-empty vertex set of the timing graph, is the set of non-empty edges of the time series graph, is the correlation function of the timing diagram, ,further, Can be abbreviated as ; The step S5 comprises: For a collection of sequence diagrams The starting node ,like , it means that there are multiple entries in the timing diagram and the verification fails; among them, Indicates in-degree; For a collection of sequence diagrams The terminal node ,like , it means that there are multiple exits in the timing diagram and the verification fails; Indicates degree; The step S6 includes: for the timing diagram set , use the depth-first traversal algorithm to traverse the timing graph set , calculate the in-degree of each point in the set, if , mark this point as the vertex , delete the sequence diagram collection The vertex and its corresponding edge in the operation are recorded as and ; Recalculate vertices The in-degree of the adjacent vertex is denoted by ,in, Represents a vertex The in-degree of the adjacent vertex; repeat the above steps until all the points in the set are traversed. , it means that there is a loop in the timing diagram and the verification fails.

2. The timing diagram verification method based on graph theory algorithm according to claim 1, characterized in that: The following steps are also included: Step S8, constructing a process flow feature according to the process set obtained in step S1; Step S9. Complete the process feature coding; Step S10: Implementing the recommendation of the time series diagram based on the KNN algorithm.

3. The timing diagram verification method based on graph theory algorithm according to claim 1, characterized in that: The step S1 includes: traversing the process steps to obtain a process set ,gather .

4. The timing diagram verification method based on graph theory algorithm according to claim 1, characterized in that: The step S2 includes: traversing the timing graph, and then obtaining a non-empty vertex set of the timing graph , a non-empty edge set And the timing diagram correlation function A collection of processes including .

5. The timing diagram verification method based on graph theory algorithm according to claim 2, characterized in that: The step S8 comprises: constructing a process flow feature according to the process set obtained in step S1, which is recorded as , The data structure is as follows ； Will The data structure is converted into decimal code. Each process name corresponds to only one decimal code. The characteristics of the converted timing diagram are recorded as .

6. The timing diagram verification method based on graph theory algorithm according to claim 5, characterized in that: The step S9 comprises: Use the base division remainder method to perform binary coding and complete the feature coding, which is recorded as .

7. The timing diagram verification method based on graph theory algorithm according to claim 6, characterized in that: The step S10 includes: using the zero-filling method to Completing features makes the data dimension consistent, recorded as ; Using Euclidean calculation , is the historical data of the process flow; if , then recommended Corresponding timing diagram.

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