Memory system and method of operating a memory array

Abstract

Methods of operating memory systems and memory arrays are provided. A memory system for performing in-memory compute (CiM) operations includes a memory array and a processing circuit. The memory array includes a plurality of memory cells. The processing circuit is coupled to the memory array and includes a programming circuit and a control circuit. The programming circuit is coupled to the memory array and is configured to perform write operations for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and is configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operations performed by the programming circuit to program the electrical characteristics of the memory cells in a sequence order of the weight values.

Description

Technical Field

[0001] Embodiments of this application relate to methods of operating memory systems and memory arrays. Background Technology

[0002] Implementing high-performance computing (HPC), such as artificial intelligence (AI), deep learning (DL), machine learning (ML), and reinforcement learning, typically involves a large number of matrix multiplications. The speed of matrix multiplication is limited by memory access speed, also known as the von Neumann bottleneck. Given this speed limitation, compute-in-memory (CiM) architecture has attracted attention because it has the potential to overcome the von Neumann bottleneck in current computing architectures. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a memory system for performing memory computing (CiM) operations is provided. The memory system includes a memory array and processing circuitry. The memory array includes a plurality of memory cells. The processing circuitry is coupled to the memory array. The processing circuitry includes programming circuitry and control circuitry. The programming circuitry is coupled to the memory array and configured to perform write operations for programming the electrical characteristics of the memory cells. The control circuitry is coupled to the programming circuitry and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operations performed by the programming circuitry to program the electrical characteristics of the memory cells in a sequential order of the weight values.

[0004] According to another aspect of an embodiment of this application, a memory system for performing memory computing (CiM) operations is provided. The memory system includes a memory array and processing circuitry. The memory array includes a plurality of memory cells, each storing a plurality of weight data corresponding to a plurality of weight values. The plurality of weight data are signed numbers. The memory cells are coupled to bit lines and are each controlled by a plurality of word lines. The processing circuitry is coupled to the memory array. The processing circuitry includes control circuitry, readout circuitry, and shift converter. The control circuitry is coupled to programming circuitry and configured to: receive a plurality of input data corresponding to a plurality of input values; and control voltages on word lines according to the plurality of input data, thereby controlling each memory cell to be enabled or disabled. The readout circuitry is coupled to a bit line and configured to perform a read operation to read the electrical characteristics of the enabled memory cell and generate a first summation result, wherein the first summation result is based on unsigned data. The shift converter is coupled to the readout circuitry and configured to generate a signed summation result by encoding the first summation result using two's complement representation.

[0005] According to one aspect of an embodiment of this application, an operation method for operating a memory array is provided. The memory array includes a plurality of memory cells, each storing a plurality of weight data corresponding to a plurality of weight values. The memory cells are coupled to bit lines and are each controlled by a plurality of word lines. The operation method includes: controlling the voltage on the word lines according to the plurality of input data, thereby controlling each memory cell to be enabled or disabled; performing a read operation to read the electrical characteristics of the enabled memory cells and generating a first summation result, wherein the first summation result is unsigned data; and encoding the first summation result using two's complement representation to generate a signed summation result. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic block diagram of a memory system according to some embodiments is shown.

[0008] Figure 2A A table showing programming operations for the multi-level cell (MLC) according to some embodiments is provided, when the weight data are unsigned and signed numbers respectively.

[0009] Figure 2B A table showing the programming operations for a third-order cell (TLC) according to some embodiments is provided, when the weight data are unsigned and signed numbers, respectively.

[0010] Figure 3A A table showing read operations performed on an MLC according to some embodiments when the weight data are unsigned and signed numbers, respectively.

[0011] Figure 3B The data transformation performed by the readout circuitry when a read operation is performed on an MLC storing weight data of signed numbers, according to some embodiments, is illustrated.

[0012] Figure 3C A table is shown that, according to some embodiments, read operations are performed on a TLC when the weight data are unsigned numbers and signed numbers, respectively.

[0013] Figure 3D The data conversion performed by the readout circuitry when a read operation is performed on a TLC storing weight data of signed numbers, according to some embodiments, is illustrated.

[0014] Figure 4A A memory system according to some embodiments is shown.

[0015] Figure 4B The diagram illustrates a read operation performed by a readout circuit when the weight data is a signed number, according to some embodiments.

[0016] Figure 5A A flowchart of an operation method according to some embodiments is shown.

[0017] Figure 5B A flowchart of another method of operation according to some embodiments is shown. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0020] Figure 1 A schematic block diagram of a memory system 1 according to some embodiments is shown. The memory system 1 can be used to perform in-memory computation (CiM) operations. The memory system 1 includes a memory array 10 and processing circuitry (also referred to as a controller) 12 coupled to the memory array 10. The processing circuitry 12 is configured to control operations in the memory array 10. The processing circuitry 12 is configured to perform at least one write operation (also referred to as a programming operation) or read operation on the memory array 10. In some embodiments, the memory system 1 is integrated as a system-on-a-chip (SoC) and arranged on a single chip. In some embodiments, the memory system 1 is part of a larger IC device that includes circuitry for other functions besides the memory system. In some embodiments, the memory system 1 is disposed on at least one chip.

[0021] exist Figure 1 In an exemplary configuration of the memory system 1, although not shown, the memory array 10 includes a plurality of memory cells arranged in columns and rows. Each memory cell may include at least one memory element. The electrical characteristics (e.g., resistance or threshold voltage, or other suitable electrical characteristics) of each memory element can be programmed at different levels. Thus, a memory cell can store data by programming the electrical characteristics of the memory element at the corresponding level. In some embodiments, each memory cell in the memory array 10 is a multi-level cell (MLC), a third-level cell (TLC), a fourth-level cell (QLC), etc. In some embodiments, the memory system 1 comprising a plurality of memory cells is configured as one of an MLC, TLC, or QLC memory for storing data. In one or more embodiments, the MLC, TLC, or QLC memory is further configured to perform CiM operations. In at least one embodiment, one or more advantages can be achieved, including but not limited to a larger memory window (margin for reading data from memory), better computational performance, etc.

[0022] The memory array 10 also includes a plurality of word lines, a plurality of source lines, and at least one bit line. Each memory cell is coupled to the processing circuitry 12 via a corresponding bit line and a corresponding word line. The word lines are configured to transmit addresses of memory cells or memory elements, etc., to be read from and / or written to in the memory cell. Word lines are sometimes referred to as “address lines.” At least one bit line and / or source line is configured to transmit data, etc., to be written to and / or read from memory cells or memory elements, indicated by addresses on the corresponding word lines. At least one bit line and / or source line is sometimes referred to as a “data line.” The various numbers of word lines, bit lines, and / or source lines in the memory array 10 are within the scope of various embodiments.

[0023] Examples of programmable memory elements, to have different electrical characteristic values, include, but are not limited to, resistive random access memory (ReRAM or RRAM), magnetic RAM (MRAM), phase-change memory (PCM), flash memory containing charge storage material or floating gates, etc. In one or more embodiments, both NOR and NAND gate flash memory are suitable for implementing memory cells in memory elements. RRAM, MRAM, or PCM memory elements include access transistors electrically coupled in series with a memory layer. The memory layer is programmable to have two or more states corresponding to two or more resistance values ​​of the memory element. The gate of the access transistor of the RRAM, MRAM, or PCM memory element corresponds to a control terminal of the memory element and is electrically coupled to a corresponding word line. Flash memory elements include transistors with floating gates or charge storage layers. The floating gate or charge storage layer is programmable to store two or more orders of charge corresponding to two or more resistance values ​​of the memory element. The gate of the transistor of the flash memory element corresponds to a control terminal of the memory element and is electrically coupled to a corresponding word line. Other types or configurations of memory elements are also within the scope of various embodiments.

[0024] The processing circuit 12 includes a programming circuit 120, a control circuit 122, and a readout circuit 124. In at least one embodiment, the processing circuit 12 further includes one or more clock generators for providing clock signals to various components of the memory system 1, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations in the memory system 1.

[0025] Programming circuitry 120 is coupled to a memory cell of memory array 10 via at least one bit line and a source line to perform a write operation on at least one memory cell in memory array 10. In at least one embodiment, processing circuitry 120 further includes a word line driver (also referred to as a "word line decoder") coupled to memory array 10 via a word line. The word line driver is configured to decode the row address of a selected memory cell, which is chosen to be accessed in a read or write operation. In at least one embodiment, the programming circuitry 120 performs a write operation on the selected memory cell by controlling the voltage on the corresponding source line, thereby adjusting the electrical characteristics of the selected memory cell to a level corresponding to the applied voltage.

[0026] The readout circuit 124 is coupled to a memory cell of the memory array 10 via at least one bit line to perform a read operation on at least one memory cell of the memory array 10. In at least one embodiment, the readout circuit 124 further includes a sense amplifier coupled to the memory array 10 via at least one bit line. The sense amplifier is configured to read the electrical characteristics of the memory cell from at least one bit line during a read operation.

[0027] Control circuitry 122 is coupled to programming circuitry 120 and readout circuitry 124 to control write and / or read operations performed on memory array 10. In at least one embodiment, control circuitry 122 is configured to receive multiple weight data corresponding to multiple weight values, and to control programming circuitry 120 to perform write operations on memory cells, thereby allowing the electrical characteristics of the memory cells to be programmed in order of weight values. In at least one embodiment, the electrical characteristics of the corresponding memory cells are programmed in sequence according to the weight values. As the weight values ​​increase or decrease, the electrical characteristics of each memory cell continuously increase or decrease. Examples of control circuitry 122 include, but are not limited to, circuit implementations of a central processing unit (CPU), memory controller, microprocessor control unit (MCU), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or circuit implementations according to a hardware description language (e.g., Verilog, VHDL). Other types or configurations of control circuitry 122 are also within the scope of various embodiments.

[0028] For example, in a write operation, the selected memory cell is configured to have a write voltage supplied through its corresponding word line. Furthermore, the programming circuit 120 also supplies a low voltage to the selected memory cell through its corresponding bit line and / or corresponding source line. Therefore, a sufficiently large voltage difference is provided to the selected memory cell to perform the write operation. For unselected memory cells, a high voltage is supplied to the corresponding bit line of the unselected memory cell. Therefore, insufficient voltage is provided to those unselected memory cells.

[0029] More specifically, for signed and unsigned numbers, the order of the weight data differs relative to the weight values. Table 1 below shows examples of the weight data and weight values ​​for two-bit signed and unsigned numbers arranged in bit order. For example, in the order 00, 01, 10, 11, the bit order of the weight data increases as the binary value of the weight data increases. As shown in Table 1, the weight data for signed and unsigned numbers is listed in bit order. For unsigned numbers, the weight value monotonically increases according to the bit order of the weight data. However, for signed numbers, the weight value does not monotonically increase or decrease as the bit order of the weight data increases. When the sign bit of a signed number remains constant, the weight value of the signed number increases with the bit order of the weight data. However, when the sign bit of a signed number changes (e.g., weight data from 01 to 10), the weight value of the signed number decreases, but the bit order of the weight data increases. In other words, the bit order of the weight data and the sequence order of the weight values ​​are the same for unsigned numbers, but the order is different for signed numbers. This difference between the bit order of the weight data and the sequence order of the weight values ​​necessitates additional conversion by the control circuit 122 when performing a signed number write operation, so that the electrical characteristics of the memory cells can be programmed according to the sequence order of the corresponding weight values. In other words, the electrical characteristics of the memory cells are programmed according to the order of the weight values, not according to the bit order of the weight data received by the control circuit 122. In this example, although the weight values ​​are encoded as weight data using two's complement representation, it should be noted that other suitable encoding mechanisms for signed numbers (such as one's complement) are also within the scope of various embodiments.

[0030]

[0031] In at least one embodiment, the processing circuit 12 further includes a register coupled to the control circuit 122. The register is configured to store a table of recorded programming parameters corresponding to all weighted data for both signed and unsigned numbers. The programming parameters may be, for example, but not limited to, write voltages to be applied to corresponding source lines and / or corresponding bit lines. Therefore, the control circuit 122 can identify whether the received weighted data is signed or unsigned, and based on the identification result and the received weighted data, obtain appropriate programming parameters from the stored table, thus allowing the electrical characteristics of selected memory cells to be programmed in sequence according to the corresponding weight values.

[0032] Optionally, in addition to including registers, processing circuitry 12 may also include conversion logic coupled to control circuitry 122 for data conversion. For example, the conversion logic may be configured to perform data conversion on weighted data of signed numbers. When the weighted data is determined to be unsigned, the conversion logic may be disabled, so that the unsigned weighted data can be directly provided to programming circuitry 120 during a write operation. When the weighted data is determined to be signed, the conversion logic may be enabled to convert the weighted data into weight values, thus enabling programming circuitry 120 to program the electrical characteristics of memory cells according to the sequence of weight values ​​during a write operation.

[0033] Figure 2A Tables 200a and 200b illustrate programming operations for an MLC according to some embodiments when the weight data are unsigned and signed digits. Table 200a shows the weight data of the unsigned digit to be programmed, the corresponding weight values, and the electrical characteristics (including cell resistance and conductivity) used to program the MLC. In Table 200a, the weight values ​​are arranged sequentially in the second column, the corresponding weight data to be programmed is located in the first column, and the corresponding electrical characteristics of the MLC are located in the third and fourth columns. It can be observed that as the weight value of the unsigned digit increases, the cell resistance and conductivity of the MLC decrease and increase, respectively. Furthermore, the bit order of the weight data is consistent with the sequence order of the weight values.

[0034] Table 200b displays the weight data for the signed numbers to be programmed, the corresponding weight values, and the electrical characteristics (including cell resistance and conductivity) used to program the MLC. In Table 200b, the weight values ​​are arranged sequentially in the second column, the corresponding weight data to be programmed is in the first column, and the corresponding electrical characteristics of the MLC are in the third and fourth columns. Similarly, as the weight value increases, the cell resistance of the MLC decreases, and the conductivity of the memory cell increases. Therefore, in Tables 200a and 200b, the order of electrical characteristics (both cell resistance and conductivity) is programmed according to the sequence order of the weight values, so the order of electrical characteristics is the same relative to the sequence order of the weight values ​​when programming with signed and unsigned numbers.

[0035] Figure 2BTables 200c and 200d illustrate programming operations for a TLC according to some embodiments when the weight data are unsigned and signed digits. Table 200c shows the weight data of the unsigned digits to be programmed, the corresponding weight values, and the electrical characteristics (including cell resistance and conductivity) used to program the TLC. In Table 200c, the weight values ​​are arranged sequentially in the second column, the corresponding weight data to be programmed is located in the first column, and the corresponding electrical characteristics of the TLC are programmed in the third and fourth columns. It can be observed that as the weight value of the unsigned digit increases, the cell resistance and conductivity of the TLC decrease and increase, respectively. Furthermore, the bit order of the weight data is consistent with the sequence order of the weight values.

[0036] Table 200d shows the weight data for the signed numbers to be programmed, the corresponding weight values, and the electrical characteristics (including cell resistance and conductivity) used to program the TLC. In Table 200d, the weight values ​​are arranged sequentially in the second column, the corresponding weight data to be programmed is in the first column, and the corresponding electrical characteristics of the TLC are in the third and fourth columns. Similarly, as the weight value increases, the cell resistance of the TLC decreases, and the conductivity of the memory cell increases. Therefore, in Tables 200c and 200d, the order of electrical characteristics (both cell resistance and conductivity) is programmed according to the sequence order of the weight values, so the order of electrical characteristics is the same relative to the sequence order of the weight values ​​when programming with signed and unsigned numbers.

[0037] Furthermore, for the electrical characteristics of unsigned numbers (whether two or three digits), the unit resistance is inversely proportional to the weight value, while the conductivity is directly proportional to the weight value. More specifically, the programmed conductivity is linearly related to the weight value, which further facilitates CiM operation of MLCs. CiM operation will be discussed in detail below.

[0038] For example, in a read operation, the selected memory cell is configured to be supplied with a read voltage through the corresponding word line to fully enable the selected memory cell. Furthermore, a read current is supplied to the selected memory cell through the corresponding source line. Therefore, the selected memory cell is enabled to perform a read operation, and the current flowing through the memory cell is determined by the electrical characteristics of the memory storage elements within the memory cell (which is programmed at an order corresponding to the weighted data) and supplied to the corresponding bit line. A sense amplifier is configured to receive the current and compare it with at least one current threshold to determine the level of the received current. Therefore, the data stored in the selected memory cell can be obtained from the comparison result generated by the sense amplifier.

[0039] Figure 3ATables 300a and 300b illustrate read operations performed on an MLC according to some embodiments when the weight data is unsigned and signed digits. Table 300a shows the weight data of the stored unsigned digits, the weight values ​​corresponding to the weight data, and the electrical characteristics of the MLC to be read (including cell resistance and conductivity). In Table 300a, the sequence order of the weight values ​​is the same as the bit order of the weight data; therefore, the order in which the electrical characteristics (especially conductivity) are read from the MLC also follows the bit order of the weight data.

[0040] Table 300b shows the stored signed numerical weight data, the corresponding weight values, and the electrical characteristics of the MLC to be read (including unit resistance and conductivity). In Table 300b, the sequence order of the weight values ​​is different from the bit order of the weight data, which makes the order of the electrical characteristics (especially conductivity) read from the MLC inconsistent with the bit order of the weight data.

[0041] In at least one embodiment, a read operation is performed by sensing the current level flowing through the memory cell using the readout circuit 124. One advantage of programming the electrical characteristics to follow a sequence order of weight values ​​is that when performing a read operation on an MLC storing unsigned weight data, the sequence order of the electrical characteristics specified by the readout circuit 124 can be readily used as the weight data for the unsigned numbers, because the order of the electrical characteristics (resistance or conductivity) read from the MLC is consistent with the bit order of the weight data. Therefore, when performing a read operation on an MLC storing unsigned weight data, simple data conversion is required or no data conversion is needed. In at least one embodiment, when performing a read operation on an MLC storing signed weight data, the readout circuit 124 requires additional data conversion because the comparison result from the sensing amplifier specifies the electrical characteristics of the MLC as unsigned numbers.

[0042] Figure 3B The data conversion performed by the readout circuit 124 when a read operation is performed on an MLC storing weight data of signed numbers, according to some embodiments, is illustrated. Figure 3B The diagram shows two lines, L1 and L2, which correspond to the relationship between conductivity and the weighted values ​​of unsigned and signed numbers, respectively. In at least one embodiment, the readout circuit 124 reads the conductivity from the MLC and generates first readout data of unsigned data. The first readout data corresponds to... Figure 3A The data listed in the second column of Table 300b, as shown, also covers... Figure 3B The middle line L1 represents the weight value range from 0 to 3. To convert the first read data from unsigned to signed, line L1 needs to be shifted left by 2. n-1Move to line L2, where n is the number of bits carried by each weight data point, which is 2 in this embodiment. Sometimes, n is also referred to as the number of bits in the weight data. Shift line L1 left by 2. n-1 The operation corresponds to subtracting 2 from the first read data. n-1 Data conversion. For example, referring to the first row of Table 300b, where the first read data is 11, by subtracting the binary value corresponding to 2. 2-1 From data 10, the signed readout data 01 corresponding to the weight data programmed into the MLC is calculated. Therefore, during the readout operation of the signed digit weight data from the MLC, the value 2 can be subtracted from the comparison result generated by the sense amplifier. 2-1 The data is transformed to obtain weighted data of signed numbers.

[0043] Figure 3C Tables 300c and 300d are shown according to some embodiments, illustrating read operations performed on a TLC when the weight data are unsigned and signed numbers, respectively. Table 300c displays the weight data for the stored unsigned numbers, the corresponding weight values, and the electrical characteristics (including cell resistance and conductivity) used for programming the TLC. Table 300d displays the weight data for the stored signed numbers, the corresponding weight values, and the electrical characteristics (including cell resistance and conductivity) used for programming the TLC. Similar to Tables 300a and 300b discussed above, Table 300c shows that the sequence order of the weight values ​​is the same as the bit order of the weight data, therefore the order of electrical characteristics (especially conductivity) read from the TLC also follows the bit order of the weight data. Table 300d shows that the sequence order of the weight values ​​is different from the bit order of the weight data, which makes the order of electrical characteristics (especially conductivity) read from the TLC inconsistent with the bit order of the weight data.

[0044] Figure 3D The data conversion performed by the readout circuit 124 when a read operation is performed on a TLC storing weight data of signed numbers, according to some embodiments, is illustrated. Figure 3D The diagram shows two lines, L3 and L4, which correspond to the relationship between conductivity and the weighted values ​​of unsigned and signed numbers, respectively. In at least one embodiment, the readout circuit 124 reads the conductivity of the TLC and generates first readout data of unsigned data. The first readout data corresponds to... Figure 3C The data listed in the second column of Table 300d, and also covering... Figure 3D The middle line L3 represents the weight value range from 0 to 7. To convert the first read data from unsigned to signed, line L3 needs to be shifted left by 2. n-1 Move to line L4, where n is the number of bits carried by each weight data, which is 3 in this embodiment. Shift line L3 left by 2. n-1The operation corresponds to subtracting 2 from the first read data. n-1 Data conversion. For example, referring to the fifth row of Table 300d, where the read data is 011, by subtracting the corresponding binary value 2. 3-1 From data 100, signed readout data 111 corresponding to the weight data programmed to the TLC is calculated. Therefore, during the readout operation of the signed digit weight data from the TLC, the value 2 can be subtracted from the comparison result generated by the sense amplifier. 3-1 The data is transformed to obtain weighted data of signed numbers.

[0045] Figure 4A A memory system 4 according to some embodiments is shown. The memory system 4 can be used to perform in-memory computation (CiM) operations. The memory system 4 includes a memory array 40 and processing circuitry 42 coupled to the memory array 40. The processing circuitry 42 is configured to control the operation of the memory array 40. The processing circuitry 42 is configured to perform at least one of a write operation and / or a read operation on the memory array 40.

[0046] The memory array 40 includes a plurality of memory cells MC1 MCn, each coupled to word lines WL1-WLn. Each memory cell MC1-MCn has one terminal coupled to a source line SL and another terminal coupled to a bit line BL, and the control terminal of each memory cell is controlled by one of the corresponding word lines. In at least one embodiment, each memory cell includes a memory element and a selector coupled in series between the source line SL and the bit line BL. The control terminal of the selector is coupled to a corresponding word line, so the memory cell is controlled to be enabled or disabled by a voltage provided on the word line. The electrical characteristics (e.g., resistance or threshold voltage or other suitable electrical characteristics) of each memory element can be programmed at different levels. Therefore, the memory cell is able to store data by programming the electrical characteristics of the memory element at the corresponding level. Although Figure 4A Only one source line and one bit line are shown in the diagram, but the number of word lines and / or bit lines and / or source lines in the memory array 40 is within the range of various embodiments.

[0047] The processing circuitry 42 includes a programming circuitry 420, a control circuitry 422, a readout circuitry 424, and a shift converter 426. In at least one embodiment, the processing circuitry 42 further includes one or more clock generators for providing clock signals to various components of the memory system 4, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations of the memory system 4.

[0048] Programming circuitry 420 is coupled to memory cells MC1-MCn of memory array 40 via bit line BL and source line SL to perform write operations on memory cells MC1-MCn in memory array 40. In at least one embodiment, processing circuitry 42 further includes a word line driver (also referred to as a "word line decoder") coupled to memory array 40 via word lines. The word line driver is configured to decode the row address of a selected memory cell chosen to be accessed in a read or write operation. Furthermore, the above references... Figure 2A , Figure 2B The details of the write operation described are not repeated here.

[0049] The readout circuit 424 is coupled via bit line BL to memory cells MC1-MCn of memory array 40 to perform a read operation on at least one memory cell in memory array 40. In at least one embodiment, the readout circuit 424 further includes a sense amplifier coupled via bit line BL to memory array 40. The sense amplifier is configured to read the level of the equivalent electrical characteristics of the enabled memory cells MC1-MCn from bit line BL during a read operation. Furthermore, the readout circuit 424 generates a summation result SR1, which is linearly correlated with the equivalent electrical characteristics received from bit line BL.

[0050] Control circuitry 422 is coupled to programming circuitry 420 and readout circuitry 424 to control write and / or read operations performed on memory array 40. In at least one embodiment, control circuitry 422 is configured to receive multiple weight data corresponding to multiple weight values ​​and to control programming circuitry 420 to perform write operations on memory cells, thereby allowing the electrical characteristics of the memory cells to be programmed in order of weight values. In at least one embodiment, the electrical characteristics of the memory cells are programmed in sequence order of weight values. Examples of control circuitry 422 include, but are not limited to, circuit implementations of a central processing unit (CPU), memory controller, microprocessor control unit (MCU), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or circuit implementations according to a hardware description language (e.g., Verilog, VHDL). Other types or configurations of control circuitry 422 are also within the scope of various embodiments.

[0051] Figure 4BTable 400a is shown, which illustrates the weight values ​​and memory cell resistance values ​​for a read operation performed by the readout circuit 424 when the weight data is a signed number, according to some embodiments. In this embodiment, four memory cells MC1-MC4 are arranged in parallel between the source line SL and the bit line BL in the memory array 40, and all memory cells MC1-MC4 are controlled to be enabled by word lines WL1-WL4. Furthermore, each memory cell MC1-MC4 is an MLC capable of storing two bits of weight data.

[0052] Table 400a shows the weight values ​​stored in memory cells MC1-MC4, the cell resistances of memory cells MC1-MC4, and the equivalent resistance Req and conductivity 1 / Req of the parallel-arranged memory cells MCI-MC4. More specifically, Table 400a shows the read operations performed on memory cells MC1-MC4 storing negative weight values. In this example, the electrical characteristics of each memory cell are programmed according to the sequential order of the weight values, rather than the bit order of the weight data. More specifically, the cell resistance of each memory cell is programmed to be inversely proportional to the weight value, while the conductivity is directly proportional to the weight value. Therefore, the conductivity of each memory cell is linearly related to the corresponding weight value.

[0053] As shown in Table 400a, the total conductivity 1 / Req of memory cells MC1-MC4 is also proportional to the sum of the weight values ​​programmed in memory cells MC1-MC4. In other words, when the weight data is a signed number, the linear relationship between the programmed conductivity of each memory cell and the stored weight value remains unchanged in memory cells on the same bit line. This linear relationship allows the read circuit 424 to obtain the summation result SR1 through the total current on bit line BL, and the summation result SR1 is linearly related to the summation of the weight values. As a result, the read circuit 424 can program and obtain the summation of the weight values ​​on the same bit line by receiving the total current of the memory cells on the same bit line without the need for additional circuitry to convert between signed and unsigned numbers before addition. Therefore, the read circuit 424 can perform a read operation to sum the signed and / or unsigned numbers stored in the memory cells coupled to the same bit line. In at least one embodiment, the summation result SR1 generated by the readout circuit 424 is unsigned data, therefore the summation result SR1 is linearly related to the weight value, as described above. Figures 3A-3D The subject of discussion.

[0054] In at least one embodiment, the memory system 4 performs a CiM operation to calculate the sum of products (SOP) result. In at least one embodiment, input data In1-Inn are received by control circuitry 422 to control the voltage on word lines WL1-WLn respectively, thus enabling or disabling each memory cell MC1-MCn accordingly. For example, when input data with an input value of 1 is received, the address decoder can provide a read voltage to the corresponding word line to enable the selected memory cell. Otherwise, when input data with an input value of 0 is received, the corresponding memory cell is disabled. Therefore, each memory cell is enabled or disabled according to the corresponding input data, and a total current corresponding to the sum of the conductivities of the enabled memory cells is provided to bit line BL. The total current flowing through bit line BL is equal to the SOP result of input data In1-Inn multiplied by the weight data stored in memory cells MC1-MCn respectively. In other words, when a read operation is performed on memory cells MC1-MCn, the SOP result of input data In1-Inn is multiplied by the weight data stored in memory cells MC1-MCn respectively, thereby realizing the CiM operation.

[0055] However, since the summation result SR1 generated by the readout circuit 424 is unsigned data, additional data conversion is required when the weight data stored in the memory cell is signed. In at least one embodiment, a shift converter 426 is coupled to the readout circuit 424 and configured to generate a signed summation result SSR based on the summation result SR1 from the readout circuit 424. Specifically, as described above regarding... Figures 3A-3D The summation result SR1 discussed here is unsigned data following the sequence order of the weight values, which differs from the bit order of signed weighted data. Therefore, a shift converter 426 is disposed in the processing circuit 42. The shift converter 426 is coupled to the readout circuit 424 and is configured to generate a signed summation result SSR by converting the summation result SR1 into signed data using two's complement representation.

[0056] In at least one embodiment, the shift converter 426 includes an accumulator 428 and a subtractor 430. The accumulator 428 is configured to receive input data In1-Inn, sum the input data In1-Inn, and then multiply the sum of the input data In1-Inn by 2. n-1 The summation result SR2 is generated. The subtractor 430 is coupled to the accumulator 428 and is configured to subtract the summation result SR2 from the summation result SR1 to generate the signed summation result SSR.

[0057] Specifically, the multiplication and accumulation results between the input data In1-Inn and the weight data stored in the memory units MC1-MCn can be derived as follows:

[0058]

[0059]

[0060]

[0061]

[0062] ,

[0063] Among them, W s1 To W sn W represents the weight data to be stored in memory cells MC1-MCn. u1 To W un These represent the unsigned weight data read from the corresponding memory cells. (As mentioned above...) Figures 3A-3D As described, by subtracting 2 n-1 Each signed weight data point is equivalent to its corresponding unsigned data point. Therefore, in the above derivation, each signed weight data point W... sn It can be derived from the corresponding unsigned weight data W un Subtract 2 from it n-1 Instead, the input data In1-Inn are multiplied by the signed weight data W respectively. s1 -W sn The SOP result can be organized as the sum of two parts. The first part equals the input data In1-Inn multiplied by the unsigned weight data W. u1 -W un The sum of the products corresponds to the summation result SR1. The second part is equal to the input data In1-Inn multiplied by (-2). n-1 The summation of ) corresponds to the negative value of the summation result SR2. Therefore, according to the above derivation, the input data In1-Inn are multiplied by the signed weight data W respectively. s1 -W sn The SOP result can be obtained by subtracting the summation result SR2 from the summation result SR1. Therefore, when the weight data is a signed number, a signed summation result SSR can be generated through the operation of accumulator 428 and subtractor 430. In some embodiments, shift converter 426 is enabled when the weight data is a signed number. Otherwise, when the weight data is an unsigned number, shift converter 426 is disabled, and the summation result SR1 can provide the SOP result for the input data and weight values.

[0064] Figure 5A A flowchart of an operation method 500 according to some embodiments is shown. The operation method 500 can be performed by, for example... Figure 1 and Figure 4AThe memory systems 1 and 4 shown are implemented and executed. Operation method 500 includes steps S50 and S51.

[0065] although Figure 4A The memory array 40 in the diagram is a NAND flash memory array, but other types of memory arrays, such as NOR flash memory arrays, are also applicable. For example, memory cells in a NOR flash memory array can be coupled in series, and calculation results can be obtained by measuring the voltage or equivalent resistance of the series-coupled memory cells. Furthermore, Figures 2A-2B , Figures 3A-3D , Figure 4B For illustrative purposes only. Those skilled in the art can modify the electrical values ​​of the memory cells to adapt the memory system to various design concepts and system requirements.

[0066] In step S50, multiple weight data corresponding to multiple weight values ​​are received. In step S51, a write operation is performed on the memory cell, thereby programming the electrical characteristics of the memory cell according to the sequence of weight values.

[0067] More specifically, the received weight data can be signed or unsigned numbers. Since the bit order of the weight data for unsigned numbers is the same as the sequence order of the weight values, but different for signed numbers, control circuit 122 or control circuit 422 needs to perform additional conversions when performing a write operation on signed numbers. Therefore, the electrical characteristics of the memory cells can be programmed according to the sequence order of the corresponding weight values. In at least one embodiment, the programming operation can be performed by accessing programming parameters through registers, based not only on the received data but also on the identification result of whether the weight data is signed or unsigned.

[0068] Figure 5B A flowchart of another operation method 502 according to some embodiments is shown. Operation method 502 includes steps S52-S54. This can be achieved through methods such as... Figure 1 and Figure 4A The memory systems 1 and 4 shown are used to implement and execute operation method 502. Operation method 502 includes steps S52-S54.

[0069] In step S52, the voltage on the word lines is controlled according to multiple input data, thus controlling each memory cell storing signed numbers to be enabled or disabled. In step S53, a read operation is performed to read the electrical characteristics of the enabled memory cells and generate a first summation result, wherein the first summation result is based on unsigned data. In step S54, a signed summation result is generated by encoding the first summation result using two's complement representation.

[0070] More specifically, the electrical characteristics of each memory cell are programmed to store weighted data of signed numbers. The electrical characteristics are programmed to follow a sequence order corresponding to the weight values ​​of the weighted data. More specifically, the electrical characteristics are programmed to be linearly related to the weight values, so a first summation of the weight values ​​can be obtained by reading the equivalent electrical characteristics of the memory cell in step S53. However, since the electrical characteristics are linearly related to the weight values, the first summation obtained from the electrical characteristics of the memory cell corresponds to unsigned data. Therefore, a data conversion from the unsigned first summation to the signed summation result is required in step S54.

[0071] In at least one embodiment, a memory system for performing memory computing (CiM) operations includes a memory array and processing circuitry. The memory array includes a plurality of memory cells. The processing circuitry is coupled to the memory array. The processing circuitry includes programming circuitry and control circuitry. The programming circuitry is coupled to the memory array and configured to perform write operations for programming the electrical characteristics of the memory cells. The control circuitry is coupled to the programming circuitry and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operations performed by the programming circuitry to program the electrical characteristics of the memory cells in a sequential order of the weight values.

[0072] In the aforementioned memory system, multiple weight data are signed numbers encoded using two's complement representation.

[0073] In the aforementioned memory system, the electrical characteristics of the memory cells are programmed so that the electrical characteristics increase as the corresponding weight values ​​increase.

[0074] In the memory system described above, the electrical characteristics of each memory cell are programmed to be proportional to the corresponding weight value.

[0075] In the aforementioned memory system, memory cells are coupled to bit lines and controlled by multiple word lines. The memory system includes: a readout circuit coupled to bit lines and configured to perform a read operation on the memory cells for reading the electrical characteristics of the memory cells to generate a first summation result, which corresponds to the sum of the products of multiple input values ​​multiplied by weight values.

[0076] In the aforementioned memory system, the control circuit is further configured to: receive multiple input data corresponding to multiple input values; and control the voltage on the word lines according to the multiple input data respectively, so as to control each memory cell to be enabled or disabled.

[0077] In the aforementioned memory system, the readout circuit is further configured to read the total current generated by the enabled memory cells coupled to the bitline to generate a first summation result.

[0078] In the aforementioned memory system, the first summation result is linearly related to the equivalent electrical characteristics of the memory cell.

[0079] In the memory system described above, the first summation result is based on unsigned data.

[0080] The memory system described above also includes a shift converter coupled to the readout circuit and configured to generate a signed summation result by encoding the first summation result using two's complement representation.

[0081] In the aforementioned memory system, the shift converter includes: an accumulator configured to receive multiple input data, sum the multiple input data, and multiply the sum of the input data by 2. n-1 To generate a second summation result, where n is the number of bits in the weight data; and a subtractor, configured to subtract the second summation result from the first summation result to generate a signed summation result.

[0082] In the aforementioned memory system, when multiple weighted data are signed numbers, a shift converter is enabled.

[0083] In at least one embodiment, a memory system for performing memory computation (CiM) operations includes a memory array and processing circuitry. The memory array includes a plurality of memory cells, each storing a plurality of weight data corresponding to a plurality of weight values. The plurality of weight data are signed numbers. Each memory cell is coupled to a bit line and is controlled by a plurality of word lines. The processing circuitry is coupled to the memory array. The processing circuitry includes control circuitry, readout circuitry, and a shift converter. The control circuitry is coupled to the programming circuitry and configured to: receive a plurality of input data corresponding to a plurality of input values; and control voltages on the word lines according to the plurality of input data, thereby controlling each memory cell to be enabled or disabled. The readout circuitry is coupled to a bit line and configured to perform a read operation to read the electrical characteristics of the enabled memory cell and generate a first summation result, wherein the first summation result is based on unsigned data. The shift converter is coupled to the readout circuitry and configured to generate a signed summation result by encoding the first summation result using two's complement representation.

[0084] In the aforementioned memory system, the readout circuit is configured to read the total current generated by the enabled memory cells from the bit lines to generate a first summation result.

[0085] In the aforementioned memory system, the first summation result corresponds to the sum of the products of the input values ​​multiplied by the weight values.

[0086] In the aforementioned memory system, the first summation result is linearly related to the equivalent electrical characteristics of the enabled memory cell.

[0087] In the aforementioned memory system, the shift converter includes: an accumulator configured to receive multiple input data, sum the multiple input data, and multiply the sum of the input data by 2. n-1 To generate a second summation result, where n is the number of bits in the weight data; and a subtractor, configured to subtract the second summation result from the first summation result to generate a signed summation result.

[0088] In at least one embodiment, the memory array includes a plurality of memory cells, each storing weighted data corresponding to a plurality of weight values. The memory cells are coupled to bit lines and controlled by a plurality of word lines. An operation method for operating the memory array includes: controlling voltages on word lines according to a plurality of input data, thereby controlling each memory cell to be enabled or disabled; performing a read operation to read the electrical characteristics of the enabled memory cells and generating a first summation result, wherein the first summation result is unsigned data; and encoding the first summation result using two's complement representation to generate a signed summation result.

[0089] In the above operation method, the step of generating a signed summation result by encoding the first summation result using two's complement includes: receiving multiple input data and summing the multiple input data, and multiplying the sum of the input data by 2. n-1 To generate a second summation result, where n is the number of bits in the weight data; and to subtract the second summation result from the first summation result to generate a signed summation result.

[0090] In the above operation method, the first summation result is linearly related to the equivalent electrical characteristics of the enabled memory cell.

[0091] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory system for performing computational operations in memory, the memory system comprising: A memory array comprising multiple memory cells, each memory cell being coupled to a bit line and controlled by multiple word lines; Processing circuitry, coupled to the memory array, the processing circuitry comprising: A programming circuit, coupled to the memory array, is configured to perform a write operation for programming the electrical characteristics of the memory cells; and The control circuit, coupled to the programming circuit, is configured to: Receive multiple weight data corresponding to multiple weight values; and The write operation performed by the programming circuit is controlled to program the electrical characteristics of the memory cell in sequence according to the weight values. A readout circuit, coupled to the bit line and configured to perform a read operation on the memory cell, for reading the electrical characteristics of the memory cell to generate a first summation result corresponding to the sum of products of multiple input values ​​multiplied by the weight values; and A shift converter, coupled to the readout circuit, is configured to generate a signed summation result by encoding the first summation result using two's complement representation.

2. The memory system according to claim 1, wherein, The weighted data are signed numbers encoded using two's complement representation.

3. The memory system according to claim 1, wherein, The electrical characteristics of the memory cell are programmed so that the electrical characteristics increase as the corresponding weight value increases.

4. The memory system according to claim 1, wherein, The electrical characteristics of each memory cell are programmed to be proportional to the corresponding weight value.

5. The memory system according to claim 1, wherein, The processing circuitry includes at least one clock generator.

6. The memory system according to claim 1, wherein, The control circuit is further configured to: Receive multiple input data corresponding to the multiple input values; and The voltage on the word lines is controlled according to the multiple input data to enable or disable each memory cell.

7. The memory system according to claim 6, wherein, The readout circuit is further configured to read the total current generated by the enabled memory cells coupled to the bit line to generate the first summation result.

8. The memory system according to claim 1, wherein, The first summation result is linearly related to the equivalent electrical characteristics of the memory cell.

9. The memory system according to claim 1, wherein, The first summation result is based on unsigned data.

10. The memory system according to claim 1, wherein, The electrical characteristic is resistance or threshold voltage.

11. The memory system according to claim 6, wherein, The shift converter includes: An accumulator is configured to receive the plurality of input data, sum the plurality of input data, and multiply the sum of the input data by 2. n-1 To generate a second summation result, where n is the number of bits in the weight data; and The subtractor is configured to subtract the second sum from the first sum to generate the signed sum.

12. The memory system according to claim 1, wherein, The shift converter is enabled when the multiple weight data are signed numbers.

13. A memory system for performing computational operations in memory, the memory system comprising: A memory array includes multiple memory cells, each memory cell storing multiple weight data corresponding to multiple weight values, the multiple weight data being signed numbers, and each memory cell being coupled to a bit line and controlled by multiple word lines. as well as Processing circuitry, coupled to the memory array, the processing circuitry comprising: Programming circuitry, coupled to the memory array; The control circuit, coupled to the programming circuit, is configured to: Receive multiple input data corresponding to multiple input values; and The voltage on the word lines is controlled according to the multiple input data, thereby controlling whether each memory cell is enabled or disabled; A readout circuit, coupled to the bit line, is configured to perform a read operation to read the electrical characteristics of the enabled memory cell and generate a first summation result, wherein the first summation result is based on unsigned data and corresponds to the sum of products of multiple input values ​​multiplied by the weight values; and A shift converter, coupled to the readout circuit, is configured to generate a signed summation result by encoding the first summation result using two's complement representation.

14. The memory system according to claim 13, wherein, The readout circuit is configured to read the total current generated by the enabled memory cell from the bit line to generate the first summation result.

15. The memory system according to claim 13, wherein, The electrical characteristic is resistance or threshold voltage.

16. The memory system according to claim 13, wherein, The first summation result is linearly related to the equivalent electrical characteristics of the enabled memory cell.

17. The memory system according to claim 13, wherein, The shift converter includes: An accumulator is configured to receive the plurality of input data, sum the plurality of input data, and multiply the sum of the input data by 2. n-1 To generate a second summation result, where n is the number of bits in the weight data; and The subtractor is configured to subtract the second sum from the first sum to generate a signed sum.

18. A method of operating a memory array, the memory array comprising a plurality of memory cells, the plurality of memory cells respectively storing a plurality of weight data corresponding to a plurality of weight values, the plurality of weight data being signed numbers, the memory cells being coupled to bit lines and respectively controlled by a plurality of word lines, the method comprising: The voltage on the word lines is controlled according to multiple input data, thereby controlling whether each memory cell is enabled or disabled; Perform a read operation to read the electrical characteristics of the enabled memory cell and generate a first summation result, wherein the first summation result is unsigned data and corresponds to the sum of products of multiple input values ​​multiplied by the weight values; as well as A signed summation result is generated by encoding the first summation result using two's complement representation.

19. The operating method according to claim 18, wherein, The step of generating the signed summation result by encoding the first summation result using two's complement includes: Receive the plurality of input data and sum the plurality of input data, then multiply the sum of the input data by 2. n-1 To generate a second summation result, where n is the number of bits in the weight data; and The signed sum is generated by subtracting the second sum from the first sum.

20. The operating method according to claim 18, wherein, The first summation result is linearly related to the equivalent electrical characteristics of the enabled memory cell.

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