BCD device
By creating and filling through-holes with conductive material and setting a metal silicide layer in the BCD device, the problem of low surface utilization of the BCD device was solved, resulting in higher electrical performance and lower fabrication cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU WATECH ELECTRONICS CO LTD
- Filing Date
- 2022-08-30
- Publication Date
- 2026-06-26
AI Technical Summary
BCD devices have low surface utilization, and traditional connection methods increase interconnect resistance and device area, resulting in a reduction in the number of devices per unit area.
A first via is formed between adjacent DMOS device cells and filled with conductive material to change the direction of electron flow, reduce lateral diffusion, increase breakdown voltage, and a metal silicide layer is formed on the inner wall of the via to reduce contact resistance.
This improves the surface utilization of BCD devices, reduces total resistance and manufacturing costs, and enhances voltage withstand capability and device stability.
Smart Images
Figure CN116525613B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a BCD device. Background Technology
[0002] BCD (bipolar CMOS DMOS) devices are semiconductor devices that integrate bipolar transistors, CMOS devices, and DMOS devices onto a single chip. They combine the advantages of high transconductance and strong load driving capability of bipolar devices, the high integration and low power consumption of CMOS devices, and the high voltage and high current driving capabilities of DMOS devices.
[0003] Traditional DMOS devices typically achieve electron conduction by connecting the substrate and surface metal layers through heavy doping. The resistance of a DMOS device mainly consists of drift region resistance and interconnect resistance. For low-voltage devices, the drift region is thinner, reducing drift region resistance, while the interconnect resistance increases significantly and cannot be ignored in practical products. For high-voltage devices, the drift region is thicker, increasing drift region resistance, and the interconnect thickness also increases accordingly. Ion implantation is difficult to achieve deep doping, further increasing interconnect resistance. A common solution to this problem is to increase the ion implantation depth during ultra-high temperature thermal processes. However, as the ion implantation depth increases, lateral ion diffusion also increases, increasing the interconnect area and the surface area of the DMOS device. Consequently, the number of devices per unit area on the surface of a BCD device decreases accordingly.
[0004] Therefore, the surface utilization rate of current BCD devices is low. Summary of the Invention
[0005] To address the aforementioned technical problems, this application provides a BCD device.
[0006] A first aspect of this application provides a BCD device, comprising at least, in sequence, a substrate region, a second concentration-doped buried region, a plurality of DMOS device units, and a dielectric layer, wherein each DMOS device unit comprises at least, a first concentration-doped drift region with a concentration less than that of the second concentration-doped buried region, and a double-diffused metal-oxide-semiconductor field-effect transistor (DMOS) device, characterized in that a first via is formed between two adjacent DMOS device units, the first via penetrating the dielectric layer and extending to the second concentration-doped buried region, and the first via being filled with at least a conductive material; a metal silicide layer is disposed between the inner wall of the first via and the filler composed of the conductive material.
[0007] In one optional embodiment of this application, the metal silicide layer is a titanium silicide layer.
[0008] In one optional embodiment of this application, the conductive material is tungsten.
[0009] In one optional embodiment of this application, the depth of the first via in the second concentration-doped buried region is not less than the thickness of the epitaxial layer where the DMOS device unit is located.
[0010] In one optional embodiment of this application, the number of the first vias is positively correlated with the number of DMOS device cells.
[0011] In one optional embodiment of this application, the depth of the first via is positively correlated with the number of DMOS device cells.
[0012] In one optional embodiment of this application, the depth of the first via is positively correlated with the number of DMOS device cells by a coefficient of 5% to 10%.
[0013] In one optional embodiment of this application, the substrate region is a P-type substrate, and the depth of the first via in the second concentration-doped buried region is no greater than 95% of the thickness of the second concentration-doped buried region.
[0014] In one optional embodiment of this application, the substrate region is an N-type substrate, and the depth of the first via in the second concentration-doped buried region is not greater than the thickness of the second concentration-doped buried region.
[0015] In one optional embodiment of this application, a second through hole is formed in a ring shape on the outer edge of the BCD device, wherein the first end of the second through hole penetrates the surface of the BCD device, and the second end of the second through hole extends to the substrate region of the BCD device; the second through hole is filled with a metal material.
[0016] The aforementioned BCD device has a first via between two adjacent DMOS device cells, and the first via is filled with at least conductive material. Electrons in the first concentration doped drift region and the second concentration doped buried region can be introduced into the semiconductor surface through the first via and the conductive material in the first via, thereby completing the interconnection of the entire DMOS device cell.
[0017] In the first aspect, the embodiments of this disclosure provide a first through hole and fill the first through hole with conductive material. The interconnection of DMOS device units is achieved through the first through hole and the conductive material in the first through hole, that is, the drain in the DMOS device is guided to the surface to facilitate connection with other circuits or devices. No additional packaging is required, and the cost is lower.
[0018] Secondly, the electron flow direction of the DMOS device cell provided in this application embodiment is sequentially along the first concentration doped drift region, the second concentration doped buried region, and the first via. Compared with the traditional path, there is less lateral diffusion in the epitaxial region, that is, the first concentration doped drift region and the second concentration doped buried region, thereby reducing the drift region resistance and reducing the total resistance while ensuring the performance of the BCD device. At the same time, there are no excessive constraints on the thickness of the semiconductor epitaxial layer, that is, the first concentration doped drift region and the second concentration doped buried region in this application embodiment. It can be specifically set according to actual needs, which is more flexible, has lower requirements for fabrication precision, and thus reduces costs.
[0019] Thirdly, since the breakdown voltage is mainly affected by the distance between the device unit and the substrate, the breakdown voltage in traditional semiconductor devices is generally between 20V and 50V. If the breakdown voltage is less than 20V, the semiconductor device cannot work properly. If it is greater than 50V, the thickness between the device unit and the substrate needs to be increased, that is, an epitaxial layer needs to be added, which is costly. In this embodiment, the electron flow direction is changed by opening a first via filled with conductive material. By extending the depth of the first via, the breakdown voltage of the semiconductor can be adjusted to 600V, which is much greater than the maximum withstand voltage of 60V in the traditional solution. However, the conductive material is cheaper than doped ions in the epitaxial layer, thereby greatly improving the electrical performance of the DMOS device unit while reducing costs.
[0020] Fourthly, due to the presence of a first via filled with conductive material, the BCD device provided in this embodiment has a stronger voltage withstand capability than the 60V breakdown voltage of a conventional BCD device. Therefore, the spacing between the two electrodes on the semiconductor surface, i.e., the spacing between the gate and the source, can be set smaller than the spacing in the conventional method, resulting in a smaller surface area of the DMOS device unit. This allows for the configuration of more device units per unit area, thereby solving the technical problem of low surface utilization of current BCD devices and achieving the technical effect of improving the surface utilization of BCD devices. Fifthly, the substrate material of DMOS devices is generally silicon. In this embodiment, by setting a metal silicide layer between the device and the inner wall of the first via, an ohmic contact is formed with the epitaxial layer, buried layer, substrate, etc. in the semiconductor device, thereby reducing the contact resistance and thus reducing the total resistance of the DMOS device unit in this embodiment, further reducing the resistance of the BCD device. Attached Figure Description
[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0022] Figure 1This is a schematic diagram of the structure of a conventional BCD device according to this application;
[0023] Figure 2 This is a schematic diagram of the structure of the BCD device provided in the embodiments of this application;
[0024] Figure 3 A schematic diagram of another BCD device with an ohmic contact provided for an embodiment of this application;
[0025] Figure 4 A schematic diagram of another BCD device with a second through hole provided in an embodiment of this application;
[0026] Figure 5 This is a top view of the structure of a BCD device with a second through hole provided in an embodiment of this application. Detailed Implementation
[0027] In the process of developing this application, the applicant discovered that the surface utilization rate of current BCD devices is low.
[0028] To address the aforementioned problems, this application provides a BCD device in its embodiments. To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description, through embodiments and in conjunction with the accompanying drawings, provides a further detailed explanation of an atomic operation control circuit, system, and electronic device of this application. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0029] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). It should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are used solely for the convenience of describing this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0030] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0031] BCD (BJT CMOS DMOS) devices are semiconductor devices that integrate BJT (Bipolar Junction Transistor) devices, CMOS (Complementary Metal Oxide Semiconductor) devices, and DMOS (double-diffused Metal Oxide Semiconductor) devices onto a single chip. They combine the advantages of high transconductance and strong load driving capability of BJT devices, high integration and low power consumption of CMOS devices, and high voltage and high current driving capabilities of DMOS devices.
[0032] The drive and control circuits are typically implemented using CMOS and BJT devices, while high-power output devices are usually implemented using DMOS devices (120). It is generally necessary to bring the drain of the DMOS device from the back of the BCD device to the surface for easy connection to other circuits or electronic components. See also... Figure 1 A conventional BCD device 10 includes: a trench gate 101, a gate oxide layer 102, an N-type heavily doped source region 103, a P-type heavily doped body contact region 104, and a P-type lightly doped body region (…). Figure 1 (Not shown in the diagram) N-type lightly doped drift region 106, N-type heavily doped buried layer region 107, substrate 108, N-type heavily doped connection region 109, connector 110, metal layer 111, and dielectric layer 112. The BCD device 10 is constructed by heavy doping on an epitaxial layer, with the connector 110 connecting the substrate 108 and the metal layer 111 on the surface of the BCD device 10.
[0033] However, the resistance of the DMOS device 120 is mainly composed of drift region resistance and interconnect resistance. For low-voltage devices, the drift region is thinner, reducing drift region resistance, while the proportion of interconnect resistance increases significantly and cannot be ignored in practical products. For high-voltage devices, the drift region is thicker, increasing drift region resistance, and the interconnect thickness also increases accordingly. Ion implantation is difficult to achieve deep doping, and the interconnect resistance also increases. A common solution to this is to increase the ion implantation depth during ultra-high temperature thermal processes. However, as the ion implantation depth increases, lateral ion diffusion also increases, increasing the interconnect area and the surface area of the DMOS device 120. Consequently, the number of devices per unit area on the surface of the BCD device 10 decreases accordingly. Therefore, the current surface utilization rate of the BCD device 10 is relatively low.
[0034] In order to solve the technical problem of low surface utilization of BCD device 10, this application provides a BCD device 10 to improve the surface utilization of BCD device 10.
[0035] Please see Figure 2 The BCD device 20 provided in this application embodiment includes at least the following sequentially connected components: a substrate region 201, a second-concentration doped buried region 202, a plurality of DMOS device units 203, and a dielectric layer 204. Each DMOS device unit 203 includes at least a first-concentration doped drift region 2031 with a concentration lower than that of the second-concentration doped buried region 202, and a double-diffused metal-oxide-semiconductor field-effect transistor (DMOS) device. The device is characterized in that a first via 205 is formed between two adjacent DMOS device units 203. The first via 205 penetrates the dielectric layer 204 and extends to the second-concentration doped buried region 202, and the first via 205 is filled with at least a conductive material 206. Of course, the BCD device 20 also includes other functional layers, such as a trench gate 208, a gate oxide layer 209, an N-type heavily doped source region 210, a P-type heavily doped body contact region 211, a P-type lightly doped body region 212, and a metal layer 214, etc., which are not exhaustively listed here.
[0036] It should be explained that, in this embodiment, the first via 205 is a DMOS device cell 203 formed in the BCD device 20, independent of the BJT device and CMOS device in the BCD device 20. Both the first doped drift region 2031 and the second doped buried region 202 are used to provide current-carrying electrons, and the specific dopant ion type can be specifically set according to actual conditions. For example, the first doped drift region 2031 can be a lightly doped N-type drift region, and the second doped buried region 202 can be a heavily doped N-type buried layer region, or other types of drift regions and doped buried regions. This embodiment does not impose specific limitations and can be selected or set according to actual conditions. In this embodiment, the first via 205 includes a first end and a second end. The first end is located on the surface of the DMOS device unit 203, and the second end extends to the second doped buried region 202. It should be noted that in this embodiment, the second end of the first via 205 can be located in the second doped buried region 202, or it can penetrate the second doped buried region 202 to reach the substrate region 201. This embodiment does not impose specific limitations and can be specifically set according to the specific type of DMOS device in the DMOS device unit 203. The conductive material 206 can be, for example, a metal or metal compound such as tungsten or titanium, or a non-metallic conductive material 206 such as graphite. This embodiment does not impose specific limitations and can be specifically selected according to the actual situation, as long as it can achieve the purpose of conductivity. Of course, the DMOS device unit 203 can also include other functional components, which are not exhaustively listed here and can be specifically configured according to the type of DMOS device unit 203.
[0037] Please see also Figure 3 The BCD device 20 provided in this application embodiment, based on the above structure, has a metal silicide layer 207 disposed between the inner wall of the first through-hole 205 and the filler composed of the conductive material 206. The substrate material of DMOS devices is generally silicon. In this application embodiment, by disposing of a metal silicide layer 207 between the metal silicide layer 207 and the inner wall of the first through-hole 205, an ohmic contact is formed with the epitaxial layer, buried layer, substrate, etc. in the semiconductor device.
[0038] The working principle of the BCD device 20 provided in the embodiments of this application is briefly described below:
[0039] In this embodiment of the application, under the control of an applied voltage, inversion electrons are formed on the surface where the P-type lightly doped region is connected to the gate oxide layer in the DMOS device cell 203 of the BCD device 20, thus forming an electron pathway. The electron flow direction of these inversion electrons is as follows: Figure 2As shown by the dashed line with arrows, the electron flow originates from the heavily doped N-type region, passes through the inversion channel to the first concentration-doped drift region 2031, and then through the second concentration-doped buried region 202 to the conductive material 206 within the first via 205. The conductive material 206 within the first via 205 introduces electron flow into the surface of the DMOS device, facilitating connection with other devices or circuits. Experiments have shown that, compared to the heavy doping connection method of traditional DMOS devices, the number of cells covered by each first via 205 in the BCD device 20 provided in this application embodiment can be increased by 80% to 200% for the same interconnect area.
[0040] The BCD device 20 provided in this application embodiment has a first through-hole 205 between two adjacent DMOS device cells 203, and the first through-hole 205 is filled with at least conductive material 206. Electrons in the first concentration doped drift region 2031 and the second concentration doped buried region 202 can be introduced into the semiconductor surface through the first through-hole 205 and the conductive material 206 in the first through-hole 205 to complete the interconnection of the entire DMOS device cell 203.
[0041] In the first aspect, the embodiments of this disclosure provide a first through hole 205 and fill the first through hole 205 with conductive material 206. The interconnection of the DMOS device unit 203 is achieved through the first through hole 205 and the conductive material 206 in the first through hole 205, that is, the drain in the DMOS device is guided to the surface to facilitate connection with other circuits or devices without additional packaging, thus reducing costs.
[0042] Secondly, the electron flow direction of the DMOS device unit 203 provided in this application embodiment is sequentially along the first concentration doped drift region 2031, the second concentration doped buried region 202, and the first via 205. Compared with the traditional path, there is less lateral diffusion in the epitaxial region, that is, in the first concentration doped drift region 2031 and the second concentration doped buried region 202, thereby reducing the drift region resistance and reducing the total resistance while ensuring the performance of the BCD device 20. At the same time, there are no excessive constraints on the thickness of the semiconductor epitaxial layer, that is, the first concentration doped drift region 2031 and the second concentration doped buried region 202 in this application embodiment. It can be specifically set according to actual needs, which is more flexible, has lower preparation precision requirements, and thus reduces costs.
[0043] Thirdly, since the breakdown voltage is mainly affected by the distance between the device unit and the substrate, the breakdown voltage in traditional semiconductor devices is generally between 20V and 50V. If the breakdown voltage is less than 20V, the semiconductor device cannot work properly. If it is greater than 50V, the thickness between the device unit and the substrate needs to be increased, that is, an epitaxial layer needs to be added, which is costly. In this embodiment, the electron flow direction is changed by opening a first via 205 filled with conductive material 206. By extending the depth of the first via 205, the breakdown voltage of the semiconductor can be adjusted to 600V, which is much greater than the maximum withstand voltage of 60V in the traditional solution. However, the conductive material is cheaper than doped ions in the epitaxial layer, thereby greatly improving the electrical performance of the DMOS device unit 203 while reducing costs.
[0044] Fourthly, due to the presence of a first via 205 filled with conductive material 206, the BCD device 20 provided in this embodiment has a stronger voltage withstand capability than the 60V breakdown voltage of a conventional BCD device. Therefore, the spacing between the two electrodes on the semiconductor surface, i.e., the spacing between the gate and the source, can be set smaller than the spacing in the conventional method, resulting in a smaller surface area of the DMOS device unit 203. This allows for the configuration of more device units per unit area, thereby solving the technical problem of low surface utilization of the current BCD device 20 and achieving the technical effect of improving the surface utilization of the BCD device 20. Fifthly, the substrate material of DMOS devices is generally silicon. In this embodiment, by setting a metal silicide layer 207 between the DMOS device and the inner wall of the first via 205, an ohmic contact is formed with the epitaxial layer, buried layer, substrate, etc. in the semiconductor device, thereby reducing the contact resistance and reducing the total resistance of the DMOS device unit 203 in this embodiment, further reducing the resistance of the BCD device 20.
[0045] In one optional embodiment of this application, the metal silicide layer 207 is a titanium silicide layer, which has stable performance and low resistance. It can further reduce the resistance between the metal silicide layer and the epitaxial layer, buried layer, substrate, etc. in the semiconductor device, reduce the total resistance of the DMOS device unit 203 in this embodiment of the application, and thus improve the performance of the BCD device 20.
[0046] In one optional embodiment of this application, the conductive material 206 is tungsten. Tungsten has stable properties and does not cause excessive contamination to the device fabrication process during semiconductor fabrication. It is a relatively clean metal that can improve the cleanliness of the prepared semiconductor device. Meanwhile, the substrate of the DMOS device unit 203 is generally silicon, and the crystal structure of tungsten is similar to that of silicon. Therefore, in this embodiment of the application, filling the first through-hole 205 with tungsten can improve the stability and reliability of the DMOS device unit 203 and the BCD device 20.
[0047] In an optional embodiment of this application, the substrate region 201 is a P-type substrate, the depth of the first via 205 in the second concentration-doped buried region 202 is not greater than 95% of the thickness of the second concentration-doped buried region 202, and the depth of the first via 205 in the second concentration-doped buried region 202 is not less than 50% of the thickness of the second concentration-doped buried region 202.
[0048] For a P-type substrate, as the depth of the first via 205 into the second concentration-doped buried region 202 increases, the thickness of the second concentration-doped buried region 202 also needs to be increased. In this embodiment, the depth of the first via 205 into the second concentration-doped buried region 202 is no greater than 95% of the thickness of the second concentration-doped buried region 202, leaving a 5% margin of the thickness of the second concentration-doped buried region 202. This ensures that the first via 205 will not penetrate the second concentration-doped buried region 202 due to long-term electron flow during operation, thereby improving the reliability of the DMOS device unit 203 and the BCD device 20.
[0049] Meanwhile, the depth of the first via 205 in the second doped buried region 202 is not less than 50% of the thickness of the second doped buried region 202; otherwise, the electron flow width at the bottom of the first via is narrow, and the DMOS device cell 203 may not be able to conduct. In this embodiment, the depth of the first via 205 in the second doped buried region 202 is set to 50% to 95% of the thickness of the second doped buried region 202, providing the maximum electron flow width while ensuring the normal conduction of the DMOS device cell 203, thus maximizing the conductivity of the BCD device 20 provided in this embodiment. In an optional embodiment of this application, the substrate region 201 is an N-type substrate, and the depth 215 of the first via 205 in the second doped buried region 202 is not greater than the thickness of the second doped buried region 202.
[0050] The depth of the first via 205 in the second concentration-doped buried region 202 is no greater than the thickness of the second concentration-doped buried region 202. For N-type substrates, since the doping concentration of the second concentration-doped buried region 202 is not significantly different from that of the substrate, as the depth of the first via 205 increases, it can directly enter the buried layer. Therefore, the etching precision of the first via 205 does not need to be too stringent. This further reduces the fabrication difficulty and cost while ensuring the reliable performance of the DMOS device cell 203 and the BCD device 20.
[0051] In an optional embodiment of this application, the depth 215 of the first via 205 in the second concentration-doped buried region 202 is not less than the thickness of the epitaxial layer where the DMOS device unit 203 is located.
[0052] like Figure 2 and Figure 3 The dashed arrows in the diagram represent the direction of electron flow in the DMOS device cell 203 when it is in the ON state. The first via 205 and the conductive material 206 within it need to extend deep into the second doped buried region 202 to provide a wider, low-resistance current path and avoid increased resistance due to current accumulation. Especially for some high-voltage devices, as the epitaxial thickness increases, the thickness of the first via 205 entering the second doped buried region 202 must also increase accordingly to ensure it is not less than the thickness of the epitaxial layer. Therefore, in this embodiment, the depth of the first via 205 in the second doped buried region 202 is not less than the thickness of the epitaxial layer containing the DMOS device cell 203, thereby ensuring the conductivity of the first via 205 and the conductive material 206 within it, and thus improving the performance of the DMOS device cell 203 and the BCD device 20.
[0053] In one optional embodiment of this application, the number of the first vias 205 is positively correlated with the number of the DMOS device cells 203.
[0054] Each gate represents a cell. Without an applied voltage, there is no current in the N-type doped source region, P-type channel region, N-type drift region, and N-type buried layer. When the gate voltage exceeds the threshold voltage, an electron accumulation layer forms on the surface of the interconnect near the gate. This electron accumulation layer connects the source and drift regions. Under the influence of an electric field, source electrons flow from the channel, the first doped drift region 2031, the second doped buried region 202, the substrate, and the conductive material 206 in the first via 205 to the metal layer, forming a conduction current. During conduction, electrons from multiple cells share a single path in the first via 205. Therefore, in practical DMOS devices, the number of first vias 205 is positively correlated with the number of DMOS device cells 203 to meet the device's conduction requirements and improve the performance and reliability of the DMOS device cells 203.
[0055] In one optional embodiment of this application, the depth of the first via 205 is positively correlated with the number of DMOS device cells 203.
[0056] The depth of the first via 205 into the second concentration-doped buried region 202 is positively correlated with the number of cells covered by each first via 205, that is, positively correlated with the DMOS device cell 203, so as to provide the electronic path required for the covered DMOS device cell 203 to be turned on, thereby improving the working performance and reliability of the DMOS device cell 203.
[0057] In one optional embodiment of this application, the depth of the first via 205 is positively correlated with the number of DMOS device cells 203 by a coefficient of 5% to 10%.
[0058] The depth of each first via 205 into the second concentration-doped buried region 202 increases with the number of DMOS device cells 203 it covers. For each additional DMOS device cell 203, the depth of the first via 205 needs to be increased by 5% to 10%. This is to provide the most electron pathways for the covered DMOS device cells 203 while increasing the minimum resistance and the weakest current accumulation effect, thereby improving the working performance and reliability of the DMOS device cells 203.
[0059] In one optional embodiment of this application, a second through hole is formed circumferentially on the outer edge of the BCD device, wherein a first end of the second through hole penetrates the surface of the BCD device, and a second end of the second through hole extends to the substrate region of the BCD device; the second through hole is filled with a metal material.
[0060] Please see Figure 4 and Figure 5 In one optional embodiment of this application, a second through-hole 216 is circumferentially formed on the outer edge of the BCD device 20. The first end of the second through-hole 216 penetrates the surface of the BCD device, and the second end extends to the substrate region of the BCD device. The second through-hole 216 is filled with a metal material. This metal material can be grounded. By forming a second through-hole 216 filled with metal material on the outer edge of the BCD device 20, components such as the gate, source, base, and emitter inside the BCD device 20 can be enclosed to achieve shielding, thereby preventing the influence of the external environment on the internal electron flow and further improving the reliability of the BCD device 20 in this embodiment.
[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0062] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A BCD device, comprising at least: a substrate region, a second concentration-doped buried region, a plurality of DMOS device units, and a dielectric layer connected in sequence, wherein, Each of the DMOS device units includes at least: a first concentration doped drift region with a concentration less than that of the second concentration doped buried region, and a double-diffused metal-oxide-semiconductor field-effect transistor (DMOS) device. The DMOS device is characterized in that a first via is formed between two adjacent DMOS device units, the first via penetrating the dielectric layer and extending to the second concentration doped buried region, and the first via being filled with at least a conductive material; a metal silicide layer is disposed between the inner wall of the first via and the filler composed of the conductive material. The depth of the first via is positively correlated with the number of DMOS device cells; The depth of the first via is positively correlated with the number of DMOS device cells by 5% to 10%.
2. The BCD device according to claim 1, characterized in that, The metal silicide layer is a titanium silicide layer.
3. The BCD device according to claim 1, characterized in that, The conductive material is tungsten.
4. The BCD device according to claim 1, characterized in that, The depth of the first via in the second concentration-doped buried region is not less than the thickness of the epitaxial layer where the DMOS device unit is located.
5. The BCD device according to claim 1, characterized in that, The number of the first vias is positively correlated with the number of DMOS device cells.
6. The BCD device according to claim 1, characterized in that, The substrate region is a P-type substrate, and the depth of the first via in the second concentration-doped buried region is no greater than 95% of the thickness of the second concentration-doped buried region.
7. The BCD device according to claim 1, characterized in that, The substrate region is an N-type substrate, and the depth of the first via in the second concentration-doped buried region is not greater than the thickness of the second concentration-doped buried region.
8. The BCD device according to claim 1, characterized in that, The BCD device has a second through hole circumferentially formed on its outer edge. The first end of the second through hole penetrates the surface of the BCD device, and the second end of the second through hole extends to the substrate region of the BCD device. The second through hole is filled with a metal material.