PIPELINE SAR ADC second-stage sampling time control circuit

Abstract

This invention discloses a second-stage sampling time control circuit for a PIPELINE SAR ADC, relating to the field of integrated circuit technology. It includes a second-stage sampling circuit and a second-stage sampling clock generation circuit. The second-stage sampling circuit includes a margin amplifier, a second-stage sampling switch, an input capacitor, a feedback capacitor, and a load capacitor. The input terminal of the margin amplifier is connected to a reference voltage terminal through the second-stage sampling switch and the input capacitor, and the output terminal is grounded through the second-stage sampling switch and the load capacitor. The second-stage sampling clock generation circuit includes an inverter, a delay circuit, and an AND gate. The first input terminal of the AND gate is connected to the input signal, and the second input terminal is connected to the input signal through the delay circuit and the inverter. The output terminal outputs a level signal used to control the on / off state of the second-stage sampling switch. This invention designs the sampling time of the second-stage SAR ADC to vary with the PVT, reducing the bandwidth requirement of the margin amplifier at the SS corner and decreasing the power consumption of the margin amplifier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a second-stage sampling time control circuit for a PIPELINE SAR ADC. Background Technology

[0002] The PIPELINE SAR ADC can effectively reduce conversion time (by about half) and significantly reduce the impact of comparator noise on ADC SNR, making it suitable for medium-to-high precision and medium-speed applications. Figure 1 It uses the commonly used PIPELINE SAR ADC architecture. Figure 2 The above is a timing diagram for the PIPELINE SAR ADC. The high-level time of Sp is the sampling time of the first-stage SAR ADC, and the high-level time of H is the sampling time of the second-stage SAR ADC.

[0003] The bandwidth of a margin amplifier typically varies by more than 50% with respect to PVT, with a small bandwidth at the SS corner and a large bandwidth at the FF corner. For example... Figure 1 The 16x amplifier design must meet the worst-case bandwidth requirements, i.e., the SS corner. If the second-stage sampling time is fixed, it will result in significant design waste. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a second-stage sampling time control circuit for a PIPELINE SARADC.

[0005] To solve the above technical problems, the technical solution of the present invention is as follows:

[0006] A second-stage sampling time control circuit for a PIPELINE SAR ADC includes a second-stage sampling circuit and a second-stage sampling clock generation circuit.

[0007] The second-stage sampling circuit includes a margin amplifier OTA, a second-stage sampling switch CKS_STG2, an input capacitor Cs, a feedback capacitor Cf, and a load capacitor C1. The input terminal of the margin amplifier OTA is connected to the reference voltage terminal through the second-stage sampling switch CKS_STG2 and the input capacitor Cs in sequence. The output terminal of the margin amplifier OTA is connected to the ground terminal through the second-stage sampling switch CKS_STG2 and the load capacitor C1 in sequence. The feedback capacitor Cf is connected between the input terminal and the output terminal of the margin amplifier OTA.

[0008] The second-stage sampling clock generation circuit includes an inverter, a delay circuit, and an AND gate. The first input terminal of the AND gate is connected to the input signal CKI, and the second input terminal of the AND gate is connected to the input signal CKI after passing through the delay circuit and the inverter in sequence. The output terminal of the AND gate outputs a level signal used to control the opening and closing of the second-stage sampling switch CKS_STG2.

[0009] When the output of the AND gate is high, the second-stage sampling switch CKS_STG2 is closed; when the output of the AND gate is low, the second-stage sampling switch CKS_STG2 is open.

[0010] In a preferred embodiment of the second-stage sampling time control circuit of the PIPELINE SAR ADC described in this invention, the MOS transistor in the margin amplifier OTA is of the same type as the MOS transistor in the delay circuit.

[0011] As a preferred embodiment of the second-stage sampling time control circuit of the PIPELINE SAR ADC described in this invention, the delay circuit includes a cascaded inverter.

[0012] As a preferred embodiment of the second-stage sampling time control circuit of the PIPELINE SAR ADC described in this invention, the high-temperature delay of the cascaded inverter is greater than the low-temperature delay, the low-voltage delay of the cascaded inverter is greater than the high-voltage delay, and the SS corner delay of the cascaded inverter is greater than the FF corner delay.

[0013] As a preferred embodiment of the second-stage sampling time control circuit of the PIPELINE SAR ADC described in this invention, the second-stage sampling circuit further includes a first-stage sampling switch CKS_STG1, which is connected in parallel with the feedback capacitor Cf.

[0014] The beneficial effects of this invention are:

[0015] This invention designs the sampling time of the second-stage SAR ADC to vary with the PVT, which greatly reduces the bandwidth requirement of the margin amplifier at the SS corner, thereby significantly reducing the power consumption of the margin amplifier. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a commonly used PIPELINE SAR ADC architecture;

[0018] Figure 2 Timing diagrams for commonly used PIPELINE SAR ADCs;

[0019] Figure 3 A schematic diagram of the circuit connection of the second-stage sampling circuit in the second-stage sampling time control circuit of the PIPELINE SAR ADC provided by the present invention;

[0020] Figure 4 A schematic diagram of the circuit connection of the second-stage sampling clock generation circuit in the second-stage sampling time control circuit of the PIPELINE SAR ADC provided by the present invention.

[0021] Figure 5 The timing diagram of the second-stage sampling clock generation circuit in the second-stage sampling time control circuit of the PIPELINE SAR ADC provided by the present invention. Detailed Implementation

[0022] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0023] This embodiment provides a second-stage sampling time control circuit for a PIPELINE SAR ADC, including a second-stage sampling circuit and a second-stage sampling clock generation circuit.

[0024] For details, see Figure 3 The second-stage sampling circuit includes a margin amplifier OTA, a second-stage sampling switch CKS_STG2, an input capacitor Cs, a feedback capacitor Cf, a load capacitor C1, and a first-stage sampling switch CKS_STG1. The input terminal of the margin amplifier OTA is connected to the reference voltage terminal VREF_FINAL via the second-stage sampling switch CKS_STG2 and the input capacitor Cs. The output terminal of the margin amplifier OTA is connected to the ground terminal Vss via the second-stage sampling switch CKS_STG2 and the load capacitor C1. The first-stage sampling switch CKS_STG1 is connected in parallel with the feedback capacitor Cf. During first-stage SAR ADC sampling, the first-stage sampling switch CKS_STG1 is closed; after sampling, the first-stage SAR ADC opens.

[0025] Depend on Figure 3It can be seen that when the second-stage sampling switch CKS_STG2 is closed, the second-stage SAR ADC starts sampling, and the overhead OTA of the margin amplifier begins to build up. The overhead OTA build-up time is the sampling time of the second-stage SAR ADC.

[0026] The circuit connection diagram of the second-stage sampling clock generation circuit is shown below. Figure 4 As shown, the circuit includes an inverter, a delay circuit, and an AND gate. The first input of the AND gate is connected to the input signal CKI, and the second input is connected to the input signal CKI after passing through the delay circuit and the inverter. The input signal CKI, after passing through the inverter and the delay circuit, forms a CKDB level signal, which is then input to the second input of the AND gate. The output of the AND gate outputs a level signal used to control the opening and closing of the second-stage sampling switch CKS_STG2. Specifically, when the output of the AND gate is high, the second-stage sampling switch CKS_STG2 is closed; when the output of the AND gate is low, the second-stage sampling switch CKS_STG2 is open.

[0027] The delay circuit includes cascaded inverters. Cascaded inverters have a large high-temperature delay and a small low-temperature delay; cascaded inverters have a large low-voltage delay and a small high-voltage delay; cascaded inverters have a large SS corner delay and a small FF corner delay.

[0028] The bandwidth of the margin amplifier OTA is Among them, g m For the transconductance of the operational amplifier, C L This is the load capacitor of the amplifier. The MOSFETs in the margin amplifier OTA are the same type as all the MOSFETs in the delay circuit. Therefore, the transconductance variation trend of the margin amplifier OTA is the same as that of the delay circuit.

[0029] Figure 5 This is the timing diagram for the second-stage sampling clock generation circuit. Figure 5It can be seen that the CKS_STG2 level signal controlling the second-stage sampling switch CKS_STG2 is only high when both the CKI and CKDB level signals are high. The closing time of the second-stage sampling switch CKS_STG2, i.e., the sampling time width TD of the second-stage SAR ADC, is determined by the delay circuit delay. The longer the delay time of the delay circuit delay, the longer the sampling time of the second-stage SAR ADC. In the delay circuit delay, the cascaded inverter has a large high-temperature delay and a small low-temperature delay; a large low-voltage delay and a small high-voltage delay; a large SS corner delay and a small FF corner delay. Therefore, as the delay time of the delay circuit varies with PVT (process, voltage, temperature), the sampling time of the second-stage SAR ADC also varies with PVT.

[0030] Therefore, the technical solution of this application designs the sampling time of the second-stage SAR ADC to vary with PVT, which greatly reduces the bandwidth requirement of the margin amplifier at the SS corner, thereby significantly reducing the power consumption of the margin amplifier.

[0031] In addition to the above embodiments, the present invention may have other implementation methods; all technical solutions formed by equivalent substitution or equivalent transformation fall within the protection scope claimed by the present invention.

Claims

1. A second-stage sampling time control circuit for a PIPELINE SAR ADC, characterized in that: Includes a second-stage sampling circuit and a second-stage sampling clock generation circuit. The second-stage sampling circuit includes a margin amplifier OTA, two second-stage sampling switches CKS_STG2, an input capacitor Cs, a feedback capacitor Cf, and a load capacitor C1. The input terminal of the margin amplifier OTA is connected to the reference voltage terminal through one of the second-stage sampling switches CKS_STG2 and the input capacitor Cs in sequence. The output terminal of the margin amplifier OTA is connected to the ground terminal through the other second-stage sampling switch CKS_STG2 and the load capacitor C1 in sequence. The feedback capacitor Cf is connected between the input terminal and the output terminal of the margin amplifier OTA. The second-stage sampling clock generation circuit includes an inverter, a delay circuit, and an AND gate. The first input terminal of the AND gate is connected to the input signal CKI, and the second input terminal of the AND gate is connected to the input signal CKI after passing through the delay circuit and the inverter in sequence. The output terminal of the AND gate outputs a level signal used to control the opening and closing of the two second-stage sampling switches CKS_STG2. When the output of the AND gate is high, the second-stage sampling switch CKS_STG2 is closed; when the output of the AND gate is low, the second-stage sampling switch CKS_STG2 is open. The delay circuit includes cascaded inverters, wherein the high-temperature delay of the cascaded inverters is greater than the low-temperature delay, the low-voltage delay of the cascaded inverters is greater than the high-voltage delay, and the SS corner delay of the cascaded inverters is greater than the FF corner delay.

2. The second-stage sampling time control circuit of the PIPELINE SAR ADC according to claim 1, characterized in that: The MOS transistors in the margin amplifier OTA are of the same type as those in the delay circuit.

3. The second-stage sampling time control circuit of the PIPELINE SAR ADC according to claim 1, characterized in that: The second-stage sampling circuit also includes a first-stage sampling switch CKS_STG1, which is connected in parallel with the feedback capacitor Cf.

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