Multifunctional computing circuit

Abstract

The invention discloses a multifunctional calculation circuit which comprises a parameter configuration unit used for performing parameter configuration, and configured parameters comprise an addressing base address and an interpolation mode; the read addressing unit is used for generating a read request to a read bus, reading data from an external memory according to the addressing base address, and caching the read data; the data comprises input feature map data and / or input grid data; the first-round addressing address is an addressing base address; the mapping unit is used for performing coordinate transformation according to the cached grid data, and determining adjacent point pixel values and coefficients thereof for interpolation calculation according to the obtained original image coordinates; the multiply-accumulate calculation unit is used for carrying out multiply-accumulate calculation on the adjacent point pixel value and the coefficient thereof determined by the mapping unit to obtain an interpolation; and the write addressing unit is used for writing the interpolation back to the external memory. According to the scheme, the affine transformation function and the grid sampling function can be flexibly achieved, resources are saved, and the interpolation calculation speed in the affine transformation is increased.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to a multifunctional computing circuit. Background Technology

[0002] Affine transformation and grid sampling are two fundamental operations in computer vision and image processing. Affine transformation refers to geometric transformations of an image achieved through linear transformations and translations, and it has applications in image registration, object detection, and image enhancement. Grid sampling refers to sampling an image onto a given coordinate grid. This method can map an input image to an arbitrary output grid, making it widely applicable in tasks such as image deformation, image resampling, and image generation.

[0003] The implementation of affine transformation and grid sampling typically involves taking coordinates from a target image, using an inverse transformation to address the coordinates in the original image, and then calculating the coordinate values ​​through interpolation. In existing technologies, affine transformation and grid sampling are performed using separate circuits; moreover, different circuits are required for different interpolation methods. This approach not only consumes a lot of resources and has low reusability, but also results in high product design complexity and poor versatility. Summary of the Invention

[0004] This invention provides a multifunctional computing circuit that can flexibly implement both affine transformation and mesh sampling functions, saving resources, improving product versatility, and greatly increasing the interpolation calculation speed in affine transformation.

[0005] This invention provides a multifunctional computing circuit, which includes: a parameter configuration unit, a read addressing unit, a mapping unit, a multiply-accumulate calculation unit, and a write addressing unit;

[0006] The parameter configuration unit is used to configure parameters, including: addressing base address and interpolation method;

[0007] The read addressing unit is used to generate a read request to the read bus, read data from the external memory according to the addressing base address, and cache the read data; the data includes: input feature map data and input mesh data; the first round of addressing address is the addressing base address;

[0008] The mapping unit is used to perform coordinate transformation based on the cached grid data, and determine the neighboring pixel values ​​and their coefficients for interpolation calculation based on the obtained original image coordinates.

[0009] The multiply-accumulate calculation unit is used to perform multiply-accumulate calculations on the neighboring pixel values ​​and their coefficients determined by the mapping unit to obtain the interpolation;

[0010] The write addressing unit is used to write the interpolation calculated by the multiply-accumulate calculation unit back to the external memory.

[0011] Optionally, the circuit further includes: a BRAM and a first FIFO buffer;

[0012] The read addressing unit stores the read input feature map data into the BRAM and the read input grid data into the first FIFO buffer.

[0013] Optionally, reading the input feature map has a higher priority than reading the input grid data.

[0014] Optionally, the amount of input feature map data read by the read addressing unit in each round is greater than or equal to the amount of data required by the mapping unit for interpolation calculation.

[0015] Optionally, the mapping unit includes:

[0016] The coordinate transformation unit is used to read input grid data from the first FIFO buffer, perform coordinate transformation on the input grid data, and obtain the coordinates of the original image mapping points;

[0017] The coordinate processing unit is used to separate the coordinates of the mapped points in the original image and output the integer part and the decimal part;

[0018] An interpolation addressing unit is used to determine the neighbor address required for interpolation calculation using the integer part, and read the pixel value corresponding to the neighbor from the BRAM according to the neighbor address, and output the pixel value to the multiply-accumulate calculation unit.

[0019] The coefficient calculation unit is used to determine the coefficients for interpolation calculation of each pixel value using the fractional part, and outputs the coefficients to the multiply-accumulate calculation unit.

[0020] Optionally, the BRAM is a true dual-port RAM.

[0021] Optionally, the interpolation addressing unit determines the neighbor address required for interpolation calculation using the integer part according to the interpolation method configured by the parameter configuration unit.

[0022] Optionally, the interpolation method includes any one of the following: nearest neighbor interpolation, bilinear interpolation.

[0023] Optionally, the interpolation addressing unit is further configured to return a refresh BRAM control signal to the read addressing unit when there is no pixel value in the BRAM corresponding to the neighbor address;

[0024] The read addressing unit is also used to initiate the next round of addressing operation on the input feature map data after receiving the BRAM control signal.

[0025] Optionally, the interpolation addressing unit is further configured to output a set padding value as the pixel value of the neighbor address to the multiply-accumulate calculation unit when the neighbor address does not belong to the address corresponding to the input feature map data.

[0026] Optionally, the circuit further includes: a second FIFO buffer;

[0027] The write addressing unit first caches the interpolation in the second FIFO buffer. After the second FIFO buffer is full or the last interpolation is received, a write request is generated to the write bus to write the data in the second FIFO buffer to the external memory.

[0028] The multifunctional computing circuit provided in this embodiment of the invention shares the same set of addressing logic and computing units for affine transformation and mesh sampling. In the application scenario of affine transformation, the mesh data only needs to be generated in advance by the software during hardware initialization and placed in the memory. In this way, for the application of affine transformation and mesh sampling, the corresponding feature map data and mesh data can be loaded through the parameter configuration unit, and the same set of addressing logic and computing units can be used to realize the calculation of two different functions.

[0029] The multifunctional computing circuit provided in this invention can be configured with different mapping methods, interpolation modes, and data types, exhibiting strong versatility and resource reusability. Furthermore, the invention incorporates an input feature map data caching mechanism. Prefetching and caching input feature map data allows for better data reuse, reduces bandwidth requirements, and increases the efficiency of addressing and reading data. Moreover, during computation, the values ​​of multiple neighboring points can be read simultaneously, increasing the parallelism of data reading during interpolation calculations. This results in advantages such as high efficiency, low resource consumption, strong reusability, high versatility, and flexible configurability. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a multifunctional computing circuit provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of a mapping unit in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of a multiply-accumulate calculation unit in an embodiment of the present invention. Detailed Implementation

[0033] The principles and spirit of the invention will now be described with reference to exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way.

[0034] Affine transformations of an image can be represented by a 2×3 affine transformation matrix, which contains parameters for transformations such as translation, scaling, rotation, and shearing. The affine transformation formula can be expressed as:

[0035] x ′ =Ax + By + TX

[0036] y ′ =Cx+Dy+TY

[0037] Where (x,y) are the coordinates of a point in the target coordinate system, (x ′ ,y ′ ) represents the coordinates mapped to the original image after affine transformation. A, B, C, and D are matrix elements that control rotation, scaling, and cropping, while TX and TY are translation matrix elements of the image.

[0038] By appropriately setting the matrix elements and translation amounts, various types of affine transformations can be achieved, including translation, rotation, scaling, and shearing.

[0039] In existing affine transformation schemes, the target image needs to be addressed first. This is done by transforming the coordinates in the target image to the coordinates in the original image, and then performing addressing calculations based on the mapped coordinates.

[0040] Mesh sampling algorithms are primarily used to sample images on a given coordinate grid, converting a continuous space or surface into a discrete grid representation. This method can map an input image to an arbitrary output grid, making it widely applicable in tasks such as image deformation, image resampling, and image generation. Specifically, mesh sampling has two inputs: an image and a grid with specified sampling locations. Pixel values ​​are extracted from the image according to these locations. Therefore, it corresponds to the formula in affine transformation, where (x, y) represents the coordinate information recorded in the grid. (x...y ... ′ ,y ′ The coordinates are also those in the original graph.

[0041] The above analysis reveals that affine transformation and grid sampling can actually be implemented using the same circuit. The difference lies in the input: affine transformation requires only one input image, while grid sampling requires both an input image and a sampling grid. In affine transformation, (x,y) represents the coordinate information in the target image, with corresponding coordinates (0,0), (1,0),...,(0,1),(1,1),...,(n,n), increasing according to the relationship between x and y. In grid sampling, (x,y) represents the data recorded in the sampling grid, not the coordinates of the corresponding data. Therefore, existing affine transformation circuits that address based on target image coordinates are unsuitable for calculating operators like grid sampling.

[0042] To address the aforementioned issues, this invention provides a multifunctional computing circuit that shares the same addressing logic and computing unit for affine transformation and mesh sampling. In the affine transformation scenario, the input feature map data only needs to be pre-generated by the software during hardware initialization and stored in external memory. Thus, for affine transformation and mesh sampling, their respective input feature map data and mesh data can be loaded through the parameter configuration unit, achieving two different functions using the same set of addressing logic and computing unit.

[0043] like Figure 1 The diagram shown is a structural schematic of a multifunctional computing circuit provided in an embodiment of the present invention.

[0044] The multifunctional computing circuit 10 includes: a parameter configuration unit 11, a read addressing unit 12, a mapping unit 13, a multiply-accumulate calculation unit 14, and a write addressing unit 15. Wherein:

[0045] The parameter configuration unit 11 is used to configure parameters, including: addressing base address and interpolation method.

[0046] The read addressing unit 12 is used to generate a read request to the read bus, read data from the external memory 20 according to the addressing base address, and cache the read data; the data includes: input feature map data and input mesh data; the first round addressing address is the addressing base address.

[0047] It should be noted that, in this embodiment of the invention, the input feature map data is the pixel data of the original image, that is, the pixel value corresponding to each pixel. Corresponding to affine transformation, the input grid data is the coordinate information in the target image; corresponding to grid sampling, the input grid data is the coordinate information in the sampled grid.

[0048] Whether applied to affine transformation or mesh sampling, the input feature map data and input mesh data need to be stored in the external memory 20 in advance. The two are stored in different storage spaces, and the parameter configuration unit 11 needs to configure the addressing base address for these two parts of data.

[0049] The read addressing unit 12 can use different addressing modes for the input feature map data and the input mesh data. Input feature map read addressing can be controlled by both the start signal and the refresh signal, reading until the last feature map data is read; input mesh data addressing can be controlled by the start signal, reading until the last mesh data is read, and the two do not affect each other. When both input feature map data and input mesh data are requested simultaneously, the read request for the input feature map data can be set to a higher priority. Since the amount of input feature map data is larger, this can make the reading of the two types of data more balanced. Thus, the read request for reading the input feature map data from external memory 20 can be executed first, followed by the read request for reading the input mesh data from external memory 20.

[0050] To facilitate subsequent processing of the read data, a buffer can be set in the multi-functional computing circuit 10, and the read addressing unit 12 stores the data read from the external memory 20 into the buffer.

[0051] In one non-limiting embodiment, a BRAM (Block Random Access Memory) and a first FIFO (First In First Out) buffer may be configured.

[0052] Accordingly, the read addressing unit 12 can store the read input feature map data into the BRAM and the read input grid data into the first FIFO buffer. Of course, the read input network data can also be cached in the on-chip BRAM, and this embodiment of the invention does not limit this.

[0053] The amount of input feature map data read by the addressing unit 12 in each round can be greater than or equal to the amount of data required by the mapping unit 13 for interpolation calculation, because the input feature map is read from a continuous address space, in which some input feature map data may not participate in the interpolation calculation.

[0054] The mapping unit 13 is used to perform coordinate transformation based on the cached grid data, and to determine the neighboring pixel values ​​and their coefficients for interpolation calculation based on the obtained original image coordinates.

[0055] The neighboring pixel values ​​can be obtained from the cached input feature map data based on the original image coordinates, which will be discussed in detail later. Figure 2 The specific structure of the mapping unit 13 shown will be described in detail.

[0056] In this embodiment of the invention, the interpolation calculation can employ a variety of interpolation algorithms, such as nearest neighbor interpolation or bilinear interpolation. The specific interpolation algorithm used can be determined according to the interpolation method configured by the parameter configuration unit 11.

[0057] The multiply-accumulate calculation unit 14 is used to perform multiply-accumulate calculations on the neighboring pixel values ​​and their coefficients determined by the mapping unit 13 to obtain the interpolation.

[0058] The write addressing unit 15 is used to write the interpolation calculated by the multiply-accumulate calculation unit 14 back to the external memory.

[0059] In a non-limiting embodiment, the read operation of the read addressing unit 12 on the external memory 20 can be triggered by a register. For example, a start register (not shown) can be set in the multi-functional computing circuit 10. Accordingly, after the parameter configuration unit 11 completes the parameter configuration, a start indication value (e.g., a start indication value of 1) can be written into the start register by an external host to indicate the start of addressing computation.

[0060] Additionally, an end register (not shown) can be configured in the multi-functional computing circuit 10. After the write addressing unit 15 generates the last write request, an end indicator value (e.g., an end indicator value of 1) is written into the end register by the internal circuit to indicate that the addressing calculation is complete. Accordingly, the external host can read the end register to determine whether the addressing calculation is complete.

[0061] The external host can configure the startup register through a general interface of a Field Programmable Gate Array (FPGA).

[0062] Accordingly, the external host triggers the multi-functional computing circuit 10 to start or stop the addressing calculation process by reading the startup register.

[0063] As mentioned earlier, in this embodiment of the invention, the mapping unit 13 can use various interpolation algorithms for interpolation calculation. Regardless of whether it is nearest neighbor interpolation or bilinear interpolation, the logic of mapping the target image to the coordinates of the original image is the same. The difference is that nearest neighbor interpolation only requires the value of the original image mapping point to be rounded down to the nearest integer, while bilinear interpolation requires the values ​​of the four adjacent points of the original image mapping point to be weighted and summed.

[0064] like Figure 2 The diagram shown is a structural schematic of a mapping unit in an embodiment of the present invention.

[0065] To more clearly illustrate the relationships between each unit and other external units in mapping unit 13, Figure 2The diagram also shows BRAM16, read addressing unit 12, and multiply-accumulate calculation unit 14.

[0066] Reference Figure 2 In this example, the mapping unit 13 includes: a coordinate transformation unit 131, a coordinate processing unit 132, an interpolation addressing unit 133, and a coefficient calculation unit 134. Wherein:

[0067] Coordinate transformation unit 131 is used to read input grid data (x, y) from the first FIFO buffer, perform coordinate transformation on the input grid data, and obtain the coordinates (x, y) of the original image mapping point. ′ ,y ′ Where the coordinates (x, y) are the coordinates of the target point in the target map, (x...y ... ′ ,y ′ ) represents the coordinates of the original image mapping point corresponding to the target point (x, y).

[0068] Specifically, the read grid coordinate data can be transformed using affine transformation matrix parameters, which can be derived from... Figure 1 The parameter configuration unit 11 is pre-configured.

[0069] Coordinate processing unit 132 is used to process the coordinates (x, y) of the original image. ′ ,y ′ The integer and decimal parts are separated and output.

[0070] The interpolation addressing unit 133 is used to determine the address of the neighboring point required for interpolation calculation using the integer part, that is, the address of the pixel to be interpolated, read the pixel value corresponding to the neighboring point from BRAM 16 according to the neighboring point address, and output the pixel value to the multiply-accumulate calculation unit 14.

[0071] In this embodiment of the invention, BRAM16 can be a true dual-port RAM. A true dual-port RAM means that both ports can be read from and written to, and the two ports share the same memory.

[0072] Taking bilinear interpolation as an example, the integer part is processed by a multiplier and four adders to obtain the addresses of the four neighboring pixels.

[0073] Accordingly, for example Figure 2 As shown, two true dual-port RAMs, BRAM0 and BRAM1, are used, with a data width of 512 bits and a depth of 1024 bits. The read addressing unit 12 will read data from... Figure 1The different pixel values ​​of the input feature map data read from the external memory 20 are stored in BRAM0 and BRAM1. Since two true dual-port RAMs are used, each RAM stores two rows of data, and each true dual-port RAM can simultaneously read the data of two adjacent points in a row, thus allowing the values ​​of four pixels to be read at once. The four read pixel values ​​are then output to the multiply-accumulate calculation unit 14.

[0074] It should be noted that when there is no pixel value corresponding to the neighbor address in the BRAM16, the interpolation addressing unit 133 can return a refresh BRAM control signal to the read addressing unit 12, and read the corresponding data only after the data in the BRAM16 has been refreshed. Accordingly, after receiving the BRAM control signal, the read addressing unit 12 starts the next round of addressing operation on the input feature map data.

[0075] Additionally, it should be noted that when the neighbor address does not belong to the address corresponding to the input feature map data, the set padding value is output as the pixel value of the neighbor address to the multiply-accumulate calculation unit 14. For example, for the neighboring points of the image edge pixels, including neighboring points outside the input feature map data, the pixel values ​​of these neighboring points can be set to 0.

[0076] The implementation of the interpolation addressing unit 133 may vary depending on the interpolation algorithm. Specifically, it can be determined based on the neighbor positions and number required by the interpolation algorithm. This embodiment of the invention does not limit this.

[0077] The coefficient calculation unit 134 is used to determine the coefficients for interpolation calculation of each pixel value using the fractional part, and outputs the coefficients to the multiply-accumulate calculation unit 14. For example, for bilinear interpolation, the coefficient calculation unit 134 can generate the horizontal and vertical coefficients u, 1-u, v, and 1-v required for the difference based on the fractional part of the coordinate components. The fractional part, through the output of two adders (calculating 1 minus the fractional part) and the two fractional parts themselves, can obtain the distances from the point to each neighboring point, including two horizontal distances and two vertical distances. Then, it passes through two selectors to select one horizontal coefficient and one vertical coefficient. When the mode is selected as nearest neighbor interpolation, the coefficient is 1.

[0078] It should be noted that in the nearest neighbor interpolation algorithm, the coefficients u and v mentioned above can be set to 0, and the same applies to... Figure 2 Mapping unit structure.

[0079] Taking bilinear interpolation as an example again... Figure 3 A schematic diagram of a multiply-accumulate calculation unit 14 in an embodiment of the present invention is shown.

[0080] Reference Figure 3The multiply-accumulate calculation unit 14 includes multiple multipliers and adders.

[0081] Where f(x,y) represents the pixel value of the nth target point, f(i,j), f(i+1,j), f(i,j+1), and f(i+1,j+1) represent the pixel values ​​of the four neighboring pixels, and u, 1-u, v, and 1-v represent the corresponding weighting coefficients. Each f(x,y) is calculated as follows:

[0082] f(x,y)=f(i,j)×(1-u)×(1-v)+f(i+1,j)×u×(1-v)+f(i,j+1)

[0083] ×(1-u)×v+f(i+1,j+1)×u×v

[0084] The above calculation process is completed using a pipeline structure, as detailed below:

[0085] The first-level pipeline calculates (1-u)×(1-v), u×(1-v), (1-u)×v and u×v, which are the weighting coefficients corresponding to each neighboring point;

[0086] The second-stage pipeline completes four multiplication calculations, multiplying the pixel value of each neighboring point by the corresponding weighting coefficient to obtain f(i,j)×(1-u)×(1-v), f(i+1,j)×u×(1-v), etc.

[0087] The third and fourth stage pipelines use two-stage adders to accumulate the four products of the second stage pipeline.

[0088] The fifth-level pipeline completes the rounding saturation logic for the final calculation result data, that is, rounding the final data to the nearest integer. If the rounded integer is greater than the maximum integer that the data type can represent, then it saturates to the maximum integer.

[0089] This completes the bilinear interpolation calculation process for a target point.

[0090] Because of the use of a pipelined circuit structure, the delay in the calculation process does not affect the throughput, resulting in high efficiency.

[0091] Continue to refer to Figure 1 The write addressing unit 15 needs to write the interpolated data back to the external memory 20. In a non-limiting embodiment, a second FIFO buffer (not shown) can be provided in the multi-function computing circuit 10.

[0092] Accordingly, the write addressing unit 15 first caches the interpolation into the second FIFO buffer. After the second FIFO buffer is full or the last interpolation is received, a write request is generated to the write bus to write the data in the second FIFO buffer to the external memory 20.

[0093] The multifunctional computing circuit provided in this embodiment of the invention shares the same set of addressing logic and computing units for affine transformation and mesh sampling. In the application scenario of affine transformation, the mesh data only needs to be generated in advance by the software during hardware initialization and placed in the memory. In this way, for the application of affine transformation and mesh sampling, the corresponding feature map data and mesh data can be loaded through the parameter configuration unit, and the same set of addressing logic and computing units can be used to realize the calculation of two different functions.

[0094] The solution of this invention can support different interpolation and padding methods for different application scenarios, and can support multiple data types during interpolation calculation.

[0095] In implementing affine transformation schemes, different interpolation calculations are required to obtain the final affine calculation result. Different interpolation methods have different circuit addressing units. Specifically: Bilinear interpolation first maps the target image coordinates to the original image according to the scaling ratio, then calculates the target image value by weighting and summing the four nearest integer coordinates of the mapped point in the original image and their distance. Nearest neighbor interpolation also maps the target image coordinates to the original image according to the scaling ratio, but only requires addressing the point where the mapped point in the original image is rounded down. In other words, compared to bilinear interpolation, nearest neighbor interpolation only requires addressing one point.

[0096] Traditional bilinear interpolation requires reading the coordinates of four neighboring points. The calculation process of reading these four points sequentially is usually performed serially. Furthermore, for a given point, the coordinates of its four neighboring points are often distributed in different spatial locations and are not contiguous. This significantly impacts the efficiency of addressing calculations.

[0097] The multifunctional computing circuit provided in this invention embodiment can realize parallel addressing of multiple channels. For example, in bilinear interpolation calculation, it can address four adjacent points simultaneously, greatly improving addressing efficiency and thus efficiently completing the interpolation calculation of all target points. Moreover, the addressing mode in this invention can be flexibly configured by software, exhibiting strong versatility. Differences in the same interpolation method across different algorithms can also be addressed by modifying the corresponding configuration parameters in software.

[0098] The present invention utilizes a single circuit to support multiple operators, resulting in low resource consumption and high efficiency.

[0099] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0100] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A multifunctional computing circuit, characterized in that, The circuit includes: a parameter configuration unit, a read addressing unit, a mapping unit, a multiply-accumulate calculation unit, and a write addressing unit; The parameter configuration unit is used to configure parameters, including: addressing base address and interpolation method; The read addressing unit is used to generate a read request to the read bus, read data from the external memory according to the addressing base address, and cache the read data; the data includes: input feature map data and input mesh data; the first round of addressing address is the addressing base address; The mapping unit is used to perform coordinate transformation based on the cached grid data, and determine the neighboring pixel values ​​and their coefficients for interpolation calculation based on the obtained original image coordinates. The multiply-accumulate calculation unit is used to perform multiply-accumulate calculations on the neighboring pixel values ​​and their coefficients determined by the mapping unit to obtain the interpolation; The write addressing unit is used to write the interpolation calculated by the multiply-accumulate calculation unit back to the external memory.

2. The multifunctional computing circuit according to claim 1, characterized in that, The circuit also includes: a BRAM and a first FIFO buffer; The read addressing unit stores the read input feature map data into the BRAM and the read input grid data into the first FIFO buffer.

3. The multifunctional computing circuit according to claim 2, characterized in that, Reading the input feature map has a higher priority than reading the input grid data.

4. The multifunctional computing circuit according to claim 1, characterized in that, The amount of input feature map data read by the read addressing unit in each round is greater than or equal to the amount of data required by the mapping unit for interpolation calculation.

5. The multifunctional computing circuit according to claim 2, characterized in that, The mapping unit includes: The coordinate transformation unit is used to read input grid data from the first FIFO buffer, perform coordinate transformation on the input grid data, and obtain the coordinates of the original image mapping points; The coordinate processing unit is used to separate the coordinates of the mapped points in the original image and output the integer part and the decimal part; An interpolation addressing unit is used to determine the neighbor address required for interpolation calculation using the integer part, and read the pixel value corresponding to the neighbor from the BRAM according to the neighbor address, and output the pixel value to the multiply-accumulate calculation unit. The coefficient calculation unit is used to determine the coefficients for interpolation calculation of each pixel value using the fractional part, and output the coefficients to the multiply-accumulate calculation unit.

6. The multifunctional computing circuit according to claim 5, characterized in that, The BRAM is a true dual-port RAM.

7. The multifunctional computing circuit according to claim 5, characterized in that, The interpolation addressing unit determines the neighbor address required for interpolation calculation using the integer part according to the interpolation method configured by the parameter configuration unit.

8. The multifunctional computing circuit according to claim 7, characterized in that, The interpolation method includes any one of the following: nearest neighbor interpolation, bilinear interpolation.

9. The multifunctional computing circuit according to claim 5, characterized in that, The interpolation addressing unit is also used to return a refresh BRAM control signal to the read addressing unit when there is no pixel value in the BRAM corresponding to the neighbor address; The read addressing unit is also used to initiate the next round of addressing operation on the input feature map data after receiving the BRAM control signal.

10. The multifunctional computing circuit according to claim 9, characterized in that, The interpolation addressing unit is also used to output the set padding value as the pixel value of the neighbor address to the multiply-accumulate calculation unit when the neighbor address does not belong to the address corresponding to the input feature map data.

11. The multifunctional computing circuit according to claim 1, characterized in that, The circuit also includes: a second FIFO buffer; The write addressing unit first caches the interpolation in the second FIFO buffer. After the second FIFO buffer is full or the last interpolation is received, a write request is generated to the write bus to write the data in the second FIFO buffer to the external memory.

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