Transition-aware dynamic element matching

Abstract

This application relates to transition-aware dynamic element matching. A system includes a digital-to-analog converter comprising a plurality of cell elements and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes circuitry configured to determine a number of cell elements of the digital-to-analog converter to transition (N trn ) from an on state to an off state, determine a first number of cell elements to turn on, and determine a second number of cell elements to turn off. The circuitry can further generate a first signal identifying individual cell elements of the one or more cell elements of the digital-to-analog converter in an off state to turn on and a second signal identifying the individual cell elements of the one or more cell elements of the digital-to-analog converter in an on state to turn off.

Description

[0001] Copyright Notice

[0002] This patent document contains a portion of copyrighted material. As shown in the patent documents or records of the United States Patent and Trademark Office, the copyright holder does not object to any reproduction of this patent document or record, but will otherwise retain all copyright. Technical Field

[0003] This invention generally relates to methods, systems, and apparatus for dynamic element matching in digital-to-analog converters. Background Technology

[0004] Many modern high-speed communication systems, including both wireless and wired communication systems, have become based on digital-to-analog converters (DACs). High-resolution, high-speed DACs often suffer from timing or amplitude mismatches, which limit the overall performance of these systems. Conventional methods for mitigating these errors lead to increased power consumption and hardware complexity while failing to address harmonic effects in the data waveform.

[0005] Therefore, methods, systems, and devices for matching dynamic sensing elements are provided. Summary of the Invention

[0006] In one aspect, this application provides a method comprising: determining a transition (N) of a digital-to-analog converter from an on state to an off state or from an off state to an on state. trn The number of unit elements; at least in part based on N. trn Determine the first number of unit elements of the digital-to-analog converter to be turned on from the off state; at least in part based on N. trn Determine a second number of unit elements of the digital-to-analog converter to be turned off from the on state; select, via dynamic element matching logic, a first number of individual unit elements to be turned on from one or more unit elements of the digital-to-analog converter in the off state; and select, via the dynamic element matching logic, a second number of individual unit elements to be turned off from one or more unit elements of the digital-to-analog converter in the on state.

[0007] In another aspect, this application provides a logic circuit comprising: a register configured to store a constant switching rate value, wherein the constant switching rate value is switched at each sampling interval by a digital-to-analog converter from an on state to an off state or from an off state to an on state (N). trn The number of unit elements is given; a dynamic element matching circuit is coupled to the register, wherein the dynamic element matching circuit is configured to be at least partially based on N. trnDetermine the first number of unit elements of the digital-to-analog converter to be turned on from the off state; at least in part based on N. trn Determine a second number of unit elements of the digital-to-analog converter to be turned off from the on state; generate a first signal, wherein the first signal indicates the selection of the first number of individual unit elements, wherein the first signal further identifies the individual unit elements to be turned on among one or more unit elements of the digital-to-analog converter in the off state; and generate a second signal, wherein the second signal indicates the selection of the second number of individual unit elements, wherein the second signal further identifies the individual unit elements to be turned off among one or more unit elements of the digital-to-analog converter in the on state.

[0008] In another aspect, this application provides a system comprising: a digital-to-analog converter including a plurality of unit elements, each unit element configured to be controllable by a control signal; an encoder coupled to the digital-to-analog converter, the encoder being configured to generate the control signal based on a digital input, wherein the encoder includes circuitry configured to: determine whether the digital-to-analog converter is to transition from an on state to an off state or from an off state to an on state (N... trn The number of unit elements; determine N. trn The first number of unit elements of the digital-to-analog converter to be turned on from the off state in the number of conversions; determine the N trn The digital-to-analog converter (DAC) is to be turned off from an on state in a number of conversion cycles; a first signal is generated, wherein the first signal indicates the selection of the first number of individual unit elements, wherein the first signal further identifies the individual unit elements to be turned on among one or more unit elements of the DAC in the off state; and a second signal is generated, wherein the second signal indicates the selection of the second number of individual unit elements, wherein the second signal further identifies the individual unit elements to be turned off among one or more unit elements of the DAC in the on state. Attached Figure Description

[0009] A further understanding of the nature and advantages of particular embodiments can be achieved by referring to the remainder of the specification and the drawings, in which similar element symbols are used to refer to similar components. In some examples, sublabels are associated with reference numbers to indicate one of a plurality of similar components. When a reference number is mentioned without specifying an existing sublabel, it is intended to refer to all such plurality of similar components.

[0010] Figure 1 This is a schematic block diagram of a transition-sensing dynamic element-matched digital-to-analog converter system according to various embodiments;

[0011] Figure 2 This is a schematic diagram of the transition sensing dynamic element matching encoder logic circuit according to various embodiments;

[0012] Figure 3 This is a schematic diagram illustrating the process of matching transition-sensing dynamic elements according to various embodiments;

[0013] Figure 4 It is a timing diagram illustrating the relationship between the number of transitions and timing error according to various embodiments; and

[0014] Figure 5 This is a flowchart of a method for matching dynamic sensing elements according to various embodiments. Detailed Implementation

[0015] Various embodiments provide tools and techniques for matching dynamic sensing elements.

[0016] In some embodiments, a method for transition sensing dynamic element matching is provided. The method may include determining a digital-to-analog converter transition (N) from an on state to an off state or from an off state to an on state. trn The number of unit elements. The method can be implemented by at least partially based on N. trn Determine the first number of cell elements to be turned on from the off state in the digital-to-analog converter, and at least in part based on N. trn The method continues by determining a second number of unit elements of the digital-to-analog converter to be turned off from the on state. The method may further include selecting, via dynamic element matching logic, a first number of individual unit elements to be turned on from one or more unit elements of the digital-to-analog converter in the off state, and selecting, via the dynamic element matching logic, a second number of individual unit elements to be turned off from one or more unit elements of the digital-to-analog converter in the on state.

[0017] In some embodiments, a device for transition-sensing dynamic element matching is provided. The device may include a register configured to store a constant transition rate value, wherein the constant transition rate value is determined by the transition (N) of a digital-to-analog converter from an on state to an off state or from an off state to an on state. trn The number of unit elements is given. The device may further include dynamic element matching circuitry coupled to the register. The dynamic element matching circuitry may be configured to be at least partially based on N. trn Determine the first number of cell elements to be turned on from the off state in the digital-to-analog converter, and at least in part based on N. trnA second number of unit elements of the digital-to-analog converter to be turned off from the on state are determined. The dynamic element matching circuit may be further configured to generate a first signal indicating the selection of the first number of individual unit elements, wherein the first signal further identifies the individual unit elements to be turned on among one or more unit elements of the digital-to-analog converter in the off state, and generate a second signal indicating the selection of the second number of individual unit elements, wherein the second signal further identifies the individual unit elements to be turned off among one or more unit elements of the digital-to-analog converter in the on state.

[0018] In a further embodiment, a system for transition sensing dynamic element matching is provided. The system may include a digital-to-analog converter comprising a plurality of unit elements, each unit element configured to be controllable by a control signal. The system may further include a dynamic element matching encoder coupled to the digital-to-analog converter, the dynamic element matching encoder being configured to generate the control signal based on a digital input, wherein the dynamic element matching encoder includes circuitry. The circuitry may be configured to determine whether the digital-to-analog converter is to transition from an on state to an off state or from an off state to an on state (N... trn The number of unit elements. The circuit can be further configured to determine N. trn The first number of unit elements of the digital-to-analog converter to be turned on from the off state in the number of conversions, and determining the N trn The circuit may further generate a first signal indicating the selection of the first number of individual unit elements, wherein the first signal further identifies the individual unit elements to be turned on among the one or more unit elements of the digital-to-analog converter in the off state, and generate a second signal indicating the selection of the second number of individual unit elements, wherein the second signal further identifies the individual unit elements to be turned off among the one or more unit elements of the digital-to-analog converter in the on state.

[0019] In the following description, numerous details are set forth for purposes of explanation to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments may be practiced without some of these details. In other instances, structures and apparatuses are illustrated in block diagram form. Several embodiments are described herein, and while various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be grouped with those of other embodiments. However, for the same reason, any single feature or plurality of features of any described embodiment should not be considered essential to every embodiment of the invention, as such features may be omitted in other embodiments of the invention.

[0020] Similarly, when an element is referred to herein as "connected" or "coupled" to another element, it should be understood that the element may be directly connected to the other element, or that there is an intervening element between the elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, it should be understood that there is no intervening element in the "direct" connection between the elements. However, the presence of a direct connection does not preclude the possibility of other connections in which intervening elements may be present.

[0021] Furthermore, for ease of description, the methods and processes discussed herein may be described in a specific order. However, it should be understood that, unless the context otherwise requires, the intervention process may occur before and / or after any part of the described process, and furthermore, various steps may be reordered, added, and / or omitted according to various embodiments.

[0022] Unless otherwise specified, all figures used herein to express quantities, dimensions, etc., should be understood to be modified by the term "approximately" in all instances. In this application, unless specifically stated otherwise, the use of the singular includes the plural, and unless otherwise specified, the use of the terms "and" and "or" means "and / or". Furthermore, the use of the term "including" and other forms such as "includes" and "included" should be considered non-exclusive. Moreover, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

[0023] Conventional methods for mitigating timing and amplitude errors in DACs typically result in increased power demands, increased hardware complexity, and an inability to address second harmonic distortion. Conventional techniques focus on indiscriminately randomizing errors by dynamically switching between DAC unit elements using inefficient switching schemes (as in conventional Dynamic Element Matching (DEM)). Specifically, DEM refers to a technique used to randomize errors attributable to individual DAC unit elements by dynamically switching the individual DAC unit elements used for a given DAC code. This breaks the static relationship between the DAC code (e.g., the input code) and the error through the random rotation of thermometer bits (e.g., unary codes used to control the unit elements of the DAC). Other methods utilize additional components, such as virtual switches or random signal choppers, each of which introduces additional complexity, inefficiency, switching noise, and increased power consumption.

[0024] Therefore, the embodiments described below allow for more efficient, targeted, transition-aware dynamic element matching schemes for switching DAC unit elements. Specifically, the embodiments described below use a constant slew rate (DEM) scheme to determine how many DAC unit elements and which individual DAC unit elements will be switched. Advantages of the embodiments described below may include a constant current draw from the pre-driver power supply, which reduces power supply ripple and resulting inter-symbol interference (ISI), and further mitigates harmonic distortion (HD). n Spurious noise. Furthermore, by utilizing the Constant Switching Rate DEM (CTR-DEM) method, "just the right amount" of transient switching can be achieved without excessively increasing switching noise in low-power output signals as would be the case with conventional DEM schemes. These characteristics further contribute to achieving a lower noise floor that scales with signal power. In addition, CTR-DEM mitigates second harmonic distortion (HD2) by enforcing a constant switching rate, thereby ensuring a more uniform error distribution.

[0025] The CTR-DEM algorithm can also be paired with other digital predistortion corrections to further improve DAC performance. Furthermore, the noise floor scales with input power to maintain a robust signal-to-noise ratio (SNR), directly increasing the DAC's dynamic range. CTR-DEM can be implemented entirely in the digital domain so as not to disturb the DAC's sensitive and high-speed analog sections. Additionally, the ripple-reduced power supply may require less stringent external filtering and isolation between supplies, reducing system cost and increasing overall system channel density and data throughput. Compared to conventional DEM DACs, the embodiments described below allow the number of transitions to scale with DAC output power and frequency, further allowing users to finely tune the system's SNR.

[0026] Figure 1This is a schematic block diagram of a transition-sensing dynamic element-matched digital-to-analog converter system 100 according to various embodiments. System 100 includes a constant transition rate DEM (CTR-DEM) encoder 105 and a DAC 115. The CTR-DEM further includes CTR-DEM logic 110, and the DAC 115 further includes one or more unit elements 120a to 120j. It should be noted that in... Figure 1 Various components of system 100 are schematically shown, and modifications to the various components and other arrangements of system 100 are possible and vary according to various embodiments.

[0027] In various embodiments, the CTR-DEM encoder 105 can be configured to receive m-bit digital input d. a [n], where m is an integer. The CTR-DEM encoder 105 can be configured to encode an m-bit digital input to produce a j-bit unary code d. u [n], where j is the integer corresponding to the largest decimal value of an m-digit number (e.g., j = 2^m). m -1). For example, if m = 4, then j = 15, where j corresponds to the 4-digit value of "1111". Similarly, for m = 7, j = 127.

[0028] In various instances, the CTR-DEM encoder 105 may be coupled to the DAC 115. The DAC 115 may contain one or more unit elements 120a to 120j. In some instances, the DAC 115 may have a number of unit elements j corresponding to the number of bits of the digital output of the CTR-DEM encoder 105. Therefore, in some instances, the digital output d... u [n] can include j individual bits d u,i [n]. Therefore, in some instances, each individual bit d of the CTR-DEM encoder 105 u,i [n] can be a unit number input corresponding to the i-th unit element 120a to 120j, where i is an integer from 1 to j.

[0029] Accordingly, in some instances, the numeric output (e.g., unary code) d u [n] can be an encoded control signal generated by the CTR-DEM encoder 105, for example, from a binary digital signal d. a The unary encoded signal (also known as "thermometer code") generated by [n]. Digital output d u [n] can be a control signal that indicates or otherwise selects which unit elements 120a to 120j of DAC 115 are enabled.

[0030] In various instances, CTR-DEM logic 110 can be implemented in hardware, software, or a combination of both. In some instances, CTR-DEM encoder 105 and CTR-DEM logic 110 can be implemented without limitation as a circuit (containing logic circuitry), a custom integrated circuit (IC), a system-on-a-chip (SoC), or a field-programmable gate array (FPGA) implementation. In other instances, CTR-DEM encoder 105 can be implemented as part of a DAC controller. For example, CTR-DEM logic 110 can be implemented as part of the firmware of a DAC controller.

[0031] According to various embodiments, DAC 115 may include circuitry and components for converting digital signals into analog signals, such as wireless (e.g., radio frequency (RF)) and / or wired signals (e.g., fiber optic, copper wire, twisted pair, etc.). DAC 115 may include DACs of various architectures and / or designs, including, without limitation, pulse-width modulation (PWM) DACs, delta-Σ DACs, thermometer-encoded DACs, oversampling DACs, noise-shaping DACs, digitally controlled oscillators, resistor DACs (e.g., resistor ladder (R-2R) DACs), current DACs, voltage DACs, switched-resistor DACs, unary DACs, binary weighted DACs, or other suitable DAC designs. In further embodiments, the DAC may be implemented using combinations of components (e.g., resistors, capacitors, current sources, voltage sources, etc.). In yet another example, DAC system 100 may be part of an ADC. For example, DAC system 100 may form at least a portion of the clock data recovery (CDR) circuitry of the ADC. For example, DAC system 100 may be a phase interpolator DAC configured to output analog signals based on phase interpolator codes.

[0032] In some further instances, DAC 115 may utilize combined and / or hybrid designs. For example, in various embodiments, the unit elements of DAC 115 may themselves be individual DACs. In some instances, DAC 115 may, without limitation, comprise unary unit elements and / or binary weighted unit elements. For example, in some embodiments, DAC 115 may comprise multiple unary unit elements, wherein the corresponding outputs of all unit elements have the same weight. In other instances, segmented or “hybrid” designs may be utilized. In a segmented design, DAC 115 may comprise both unary unit elements (where the corresponding outputs of all unit elements are equally weighted) and binary weighted unit elements (e.g., the outputs of unit elements may be weighted separately).

[0033] In some instances, DAC 115 may comprise j number of unit elements 120a to 120j. In some instances, updates to the analog signal may occur at uniform sampling intervals, where the nth sampling interval is denoted by "n". In a multi-bit DAC, to generate an analog signal, the outputs of individual unit elements 120a to 120j may be coupled to a summing node, which allows the individual analog signals to be summed to produce an output analog signal. Therefore, the output analog signal may have the same characteristics as the input unary code (e.g., d). u The value corresponding to the value of [n]).

[0034] In a conventional DEM, mismatches among unit elements 120a to 120j can introduce errors into the analog signal output. For example, each unit element 120a to 120j may have a random amplitude error (r). i At any given point, the total amplitude error (e) amp (n) can be derived from each corresponding unary code (u) of the i-th unit element 120a to 120j. i (n) and random amplitude error r i The sum of the products is given as follows:

[0035]

[0036] In a further example, each transition of each unit element 120a to 120j (e.g., 0 to 0, 0 to 1, 1 to 1, and 1 to 0) can generate a corresponding transient error waveform (e 00i e 01i e 11i e 10i Ignoring clock feedthrough, we can assume e 00i =e 11i =0. Transformation error e 01i and e 10i It can be decomposed into delay (t) del,i ) and work cycle (t) cyc,j ) error, where e 01i =t cyc,i -t del,i And for the i-th unit element 120a to 120j, e 10i =t cyc,i +t del,i Therefore, the total delay error (e) can be given as follows: del (n)) and total work cycle error (e cyc (n)):

[0037]

[0038] and

[0039]

[0040] Harmonic distortion can be introduced by these errors, because e amp (n), e del (n) and e cyc (n) can have the same periodicity as the digital input. Therefore, the constant switching rate DEM scheme can be implemented via CTR-DEM logic 110, as discussed below. Figure 2 To describe in further detail.

[0041] Figure 2 This is a schematic diagram of a transition sensing dynamic element matching encoder logic circuit 200 according to various embodiments. The encoder logic circuit 200 includes a control register 205, clipping detection logic 210, on / off calculation logic 215, a difference block 220, a first random permutation logic 225, a second random permutation logic 230, a multiplexer 235, and a flip-flop 240. It should be noted that... Figure 2 The schematic diagram illustrates various components of the logic circuit 200, and modifications to the various components and other arrangements of the logic circuit 200 are possible and vary according to various embodiments. In various embodiments, the encoder logic circuit 200 and its various logic and sub-components may be implemented as hardware using various hardware and logic components, such as digital logic and / or logic circuits.

[0042] According to various embodiments, control register 205 may store a 4-bit value for a constant transition rate. It should be understood that the number of bits in the control register is not limited to 4 bits, and in some embodiments may contain more or fewer bits. In some further instances, the number of bits in control register 205 may correspond to the value of the constant transition rate.

[0043] In various instances, a constant transition rate can indicate the number of transitions (N) to be performed at each sampling interval. trn In some instances, N trn This can be set to a static value, which can be a fixed number of transitions in a unary code, wherein the unary code is further based on an input code (e.g., numeric input d). a [n]). In some instances, N trn It can be determined based on the amplitude of the incremental code, which can be given by the following formula:

[0044] Δ[n]=code(n)–code(n-1) (Equation 4)

[0045] Where code(n) and code(n-1) are the input codes, and can be combined with the input code "d a [n]” and “d a [n-1]” can be used interchangeably.

[0046] In a further example, N trn It can be an adjustable value. For example, in some embodiments, N trn This can be set by the user. In other instances, N trn The DAC can be adjusted during operation and / or in real time based on system requirements and / or metrics. For example, in some embodiments, the DAC may receive feedback from a receiver requesting an increase or decrease in amplitude (e.g., power). Accordingly, the DAC may increase N in response to a request to increase amplitude. trn And N decreases in response to a decrease in amplitude. trn In the case of modulated data, for example in a wireless DAC, N trn_opt It can be determined to vary with the carrier frequency and the type of data transmitted. For example, the data signal can exhibit characteristics that can be used to set the optimal N. trn Peak-to-average ratio.

[0047] As previously described, in some embodiments, N trn It can be a hard-coded value. In some instances, the hard-coded value can be determined based on known signal characteristics of a given use case or one or more common applications. In some instances, the optimal number of transitions N... trn_opt It can be set to the maximum value equal to the incremental code: max(Δ(n]). This produces an error distribution curve without HD2 and the minimum background noise required to suppress HD2.

[0048] In various instances, the optimal N trn_opt Amplitude P that can be input digitally sig and the frequency F of digital input sig Proportional. The following text discusses... Figure 4 To describe N in further detail trn The choice and its effects.

[0049] In some instances, the clipping detection logic 210 can be configured to check N trn Clipping. Specifically, the clipping detection logic 210 can receive digital input d. a [n] and N trn And compare the two inputs to ensure that condition d is met. a <N trn / 2 <N u -d a , where N u This refers to the number of unit elements. Therefore, the clipping detection logic 210 can ensure N trn The selection ensures that there exists a transformation that can produce the correct unary encoded output d. u Sufficient unit elements of [n]. For example, if N is chosen to be too large... trn (For example, N)trn / 2>N u -d a If there exists a numeric input value d, then there exists a numeric input value d. a The smaller range, where N trn It can be enforceable. Therefore, if N trn If it's too high, then in some instances, N can be reduced. trn On the other hand, if N trn If N is too low, then HD2 and other harmonic distortions may occur. In some instances, if N... trn If the value is too low, the clipping detection logic can be configured to add additional transformations (e.g., N). trn +1), without affecting the absolute value of the unary encoded output. Correspondingly, in various instances, the value belongs to the range d. a <N trn / 2 <N u -d a The value N inside trn The clipping detection logic 210 can output a signal L. trn .

[0050] In some alternative embodiments, the DAC (e.g., DAC 115) may further include one or more redundant unit elements. In such embodiments, one or more redundant unit elements may be turned on or off as needed to avoid clipping. In some instances, one or more redundant elements may act as “zero-padding” for the input code and remain off (or on in some instances) until one or more redundant unit elements are needed to force N for a given input code. trn This transition occurs even when the code is close to 0 (e.g., all "0" codes) or full (e.g., all "1" codes). In this configuration, L trn It can be equal to N trn And unary code d u The bit width j of [n] can be increased to the number of redundant DAC units (k). Accordingly, for m-bit input code, the number of bits j can be given by the following formula: j = (2 m -1)+k. In some instances, one or more redundant unit elements may be provided together with clipping detection logic 210. In other embodiments, clipping detection logic 210 may be skipped, and one or more redundant unit elements may be used instead.

[0051] In various embodiments, the on / off calculation logic 215 can be configured to calculate the number of unit elements to be turned on (X). on ) and the number of unit components to be turned off (X) off Specifically, X on and X off It can correspond to L trnThe number of unit elements to be turned on or off during the transition. Therefore, in some instances, X on +X off =L trn .

[0052] The on / off calculation logic 215 can be configured to receive an incremental code Δ[n] from the difference block 220. Accordingly, in some instances, the difference block 220 can be configured to determine the current code (e.g., numeric input d). a [n]) and previous code (e.g., numeric input d from the previous loop). a The first difference of the difference of [n-1]) is the inverse z-transform. In this example, the previous loop could refer to a DAC (e.g., Figure 1 The difference block 220 is the previous sampling interval of the DAC 115 and / or DAC system 100. Like other components of the encoder logic circuit 200, the difference block 220 can also be logic circuitry. In some instances, the difference block 220 may be implemented using registers (e.g., one or more D flip-flops).

[0053] Therefore, the on / off calculation logic 215 can be based on the incremental code (Δ[n]) and L trn Determine the number of unit elements to be turned on and the number of unit elements to be turned off during the transition. Therefore, once the number of transitions L is determined... trn Changes to previous codes (e.g., increment codes) can be used to determine how many additional cell elements need to be turned on or off. For example, if the increment code is 1, then one additional cell may need to be turned on. Therefore, the on / off calculation logic can determine X. on Set to be X off More than 1. Accordingly, in some instances, X on With X off The relationship between them can be expressed as: X on =X off +Δ[n].

[0054] Number of units X to be turned off off It can provide up to the first random permutation logic 225, and the number of units that need to be connected is X. onA second random permutation logic 230 may be provided. In various instances, the first random permutation logic 225 and the second random permutation logic 230 may include various types of randomization and / or randomness selection algorithms to randomize and / or select individual unit elements to be turned on or off using appropriate algorithms (e.g., random and / or randomness algorithms for selecting specific bit positions associated with individual unit elements to be switched among a plurality of unit elements). In some instances, the first random permutation logic 225 and the second random permutation logic 230 may include various types of DEM algorithms, including, without limitation, random averaging, clocked averaging, individual level averaging, data-weighted averaging, etc.

[0055] The first random permutation logic 225 can be configured based on the input X indicating the number of unit elements to be turned off. off and a signal (idx) indicating which individual unit elements were turned on during a previous cycle (e.g., a previous sampling interval). on This determines which individual unit elements should be turned off (e.g., unit elements that were previously turned on and need to be turned off). Specifically, the first random permutation logic 225 can indicate which idx should be turned off during the current sampling interval. on Which specific unit elements. In some instances, idx on This can be equal to the input unary code d of the previous loop. u [n-1]. Therefore, in some instances, the first random permutation logic 225 can be derived from the signal idx that has been indicated as passed. on Select the X unit element to be turned off when it is turned on. off A specific number of individual unit elements. For example, the specific individual unit elements to be turned off can be selected from idx according to a randomization and / or randomness selection algorithm (e.g., a dynamic element matching algorithm). on The first random permutation logic 225 can then output a signal sel indicating which unit elements have been selected to be turned off. off .

[0056] The second random permutation logic 230 can be configured based on the input X indicating the number of unit elements to be turned on. on and a signal indicating which individual unit elements were turned off during the previous cycle (idx) off This determines which individual unit elements should be turned on (e.g., unit elements that were previously turned off and are to be turned on). Specifically, the second random permutation logic 230 can indicate which idx should be turned on during the current sampling interval. off Which specific unit elements. Accordingly, in some instances, idx off It can be equal to d u The inverse of [n-1]. In some instances, the second random permutation logic 230 can be derived from the signal idx that has been passed.off Select the X unit element to be turned on when turning off. on A specific number of individual unit elements. For example, the specific individual unit elements to be connected can be selected from idx according to a randomization and / or randomness selection algorithm. off The second random permutation logic 230 can output a signal sel indicating which unit elements have been selected to be turned on. on .

[0057] In some instances, the output signal sel on and sel off It can be provided as a control signal to multiplexer 235 to select between the inputs of multiplexer 235. Specifically, the inputs of multiplexer 235 may include the input unary code of the previous loop, d u [n-1] inputs, logic 1 (e.g., logic high) and logic 0 (e.g., logic low). Based on some examples, the sel in the i-th bit position... off (sel off,i The value can be set to 1 if the corresponding i-th unit element needs to be turned off, and is set to 0 if no change is needed. Similarly, the value of sel in the i-th bit position is... on (sel on,i The value can be set to 1 if the corresponding i-th unit element is to be turned on, and is set to 0 if no change is needed. In some instances, sel off,i and sel on,i A 2-bit control signal can be generated for the multiplexer to select various inputs. Therefore, to turn off the i-th unit element of the DAC, a control signal of 10 can be generated, indicating that the multiplexer 235 should output logic 0. Similarly, to turn on the i-th unit element of the DAC, a control signal of 01 can be generated, indicating that the multiplexer 235 should output logic 1. If a control signal of 00 is output, it indicates that the i-th unit element should not change, and the multiplexer 235 can output the unary code d from the previously cycled i-th position. u,i [n-1]. In this way, the multiplexer 235 can generate a new input unary code d for the current loop. u [n]. The current input unary loop can then be stored at flip-flop 240. In some instances, flip-flop 240 can be clocked by a clock signal (e.g., a sampling clock) with a period equal to the sampling interval.

[0058] In this way, the encoder logic circuit 200 can generate input unary codes to turn the DAC unit elements on and off according to the CTR-DEM scheme. Specifically, under the CTR-DEM framework, a constant number of transitions can be enforced with transition sensing (i.e., sensing whether a given unit element will undergo a transition from on to off or from off to on). For example, a constant number of transitions can be consistently performed at each sampling interval / cycle.

[0059] Figure 3 This is a schematic diagram illustrating the process 300 of matching transition-sensing dynamic elements according to various embodiments. Specifically, Figure 3 Individual unit elements 305a to 305o are illustrated in tabular form, comprising the first unit element R1 305a to the fifteenth unit element R15 305o. Column "n" 310 may correspond to a cycle or sampling interval, where n = 1 may correspond to the first cycle, and so on. code(n) 315 may correspond to the digital input d during the nth cycle. a The value of [n]. The column below each of the unit elements R1 305a to R15 305o graphically illustrates whether the corresponding unit element is on or off and the unary code (e.g., d) in the corresponding bit position corresponding to said unit element. u The corresponding bit of [n]). A shaded square indicates an on cell element, and the number 1 indicates that the unary code value at the corresponding bit position is 0. A blank square indicates an off cell element, and the number 0 indicates that the unary code value at the corresponding bit position is 0. For example, for the first loop n=1, when reading across the entire row, the unary code d u [1] = 110111100001100 corresponds to the code(n) value of 8 (e.g., d a [1] = 1000).

[0060] Unit element transitions (e.g., from on to off or from off to on) are depicted as shaded squares (e.g., indicating a transition from off to on) and empty squares (e.g., indicating a transition from on to off). In the illustrated example, N is used. trn =5. Therefore, for each loop, enforce (e.g., consistently execute at each loop) N. trn A transformation of 5 corresponds to 5 transformations. For example, in the transformation from n=1 to n=2, the value of code(n) changes from code(1)=8 (alternately, d...). a [1] = 1000) is changed to code(2) = 9 (instead, d a [2] = 1001). Accordingly, under CTR-DEM, in order to enforce Ntrn For the transformation to 5, use X on =3 and X off =2. Therefore, the input unary code is from d. u [1] = 110111100001100 changed to d u [2] = 110111101010010, where R7, R5, and R2 are selected to turn on from the off state (e.g., to switch to the on state), and R4 and R3 are selected to turn off from the on state (e.g., to switch to the off state). In this way, the CTR-DEM scheme can continue with each of the remaining loops n = 3 to n = 16, and so on.

[0061] Figure 4 Timing diagram 400 is a graphical illustration of the relationship between the number of transitions and timing error according to various embodiments. Timing diagram 400 includes input code(n) waveform 405, delta(n) waveform 410, and error distribution curve waveforms 415a to 415c.

[0062] Conventional DEM attempts to break the numeric input code(n) (also known as d) a [n]) and unary code u i (n)(also known as d) u A static deterministic relation between [n]), where u i (n) = B2T(code(n)), where B2T is the binary-to-thermometer code conversion. Alternatively, a dynamic relationship is formed, where u i (n) = DEM(code(n)), which will reduce the amplitude error (r) i ), delay error (t) del,i ) and working cycle error (t) cyc,i This is converted to noise rather than harmonic distortion (HDx). Generally, DEM can increase switching activity, thus leading to a total delay error e del (n) and total working cycle error e cyc The RMS value of (n) is higher and the degradation of SNDR increases. Therefore, for a conventional DEM, spurious-free dynamic range (SFDR) can be improved at the cost of some degradation of signal-to-noise ratio and dispersion ratio (SNDR), while HD2 remains unchanged.

[0063] As can be seen in the error distribution curves waveforms 415a to 415c, for a conventional DEM, the error introduced by the duty cycle mismatch can be the same for both the rising and falling edge transitions. Therefore, the duty cycle error can be considered as having an error distribution curve given by the absolute value of delta(n) (used interchangeably with the "increment code" and "Δ[n]"), thus exhibiting a 2x signal frequency pattern. Therefore, second harmonic distortion (HD2) remains unchanged under the conventional DEM scheme.

[0064] Accordingly, the CTR-DEM scheme can enforce a constant conversion rate, with each cycle having N of the unit element. trn Sub-transformations. This is achieved by forcing a constant number of sub-unit element transformations or, if necessary, performing additional transformations (e.g., ~N). trn or N trn+1 This can alleviate the impact of N relative to the absolute value of delta(n). trn DAC switching current (I sw ) and pre-driven ISI. Furthermore, CTR-DEM can perform a fixed number of transformations, independent of code or incremental code. Therefore, eliminating dependence on code allows errors to propagate as noise rather than spurious noise.

[0065] Error distribution curve 415a illustration, where N trn Instances set to too high. Due to N trn Too high, thus exhibiting an increase in background noise. In various instances, more N switches than are needed to generate a given incremental code (e.g., abs(delta(n))) can be utilized. extra A number of “extra” switches achieve a constant switching rate. Therefore, the number of extra switches can be given as: N extra =N trn –abs(delta(n)), where abs(delta(n)) is the absolute value of delta(n). N extra It can always be an even value, so that any transition of a cell that was turned off matches the corresponding transition of a cell that was turned on.

[0066] Error distribution curve 415b illustration, which utilizes N trn_opt An example of N. trn_opt It is set to be equal to max(delta(n)). This produces an error distribution curve without HD2 and the minimum background noise required to suppress HD2. Optimal N trn It is proportional to the amplitude and frequency of the input code / signal. The error distribution curve 415c is where N is... trn Instances set to too low. Because N trnToo low, so the peak of abs(delta(n)) remains exposed, leading to the appearance of HD2 spurious emissions.

[0067] Therefore, by tuning N trn The proposed CTR-DEM achieves an improved SNDR superior to conventional DEMs, approaching DEM-free levels, while eliminating all mismatch-related spurious emissions. This is achieved by tuning N... trn CTR-DEM is capable of maintaining optimal SNDR across different power levels and carrier frequencies, thereby achieving a lower noise floor that scales with signal power and carrier frequency, while also improving SFDR. In some instances, tuning (e.g., adjusting) N trn It may further include checking N trn Clipping, as mentioned above Figure 2 The clipping detection logic 210 is described.

[0068] Figure 5 This is a flowchart of a method 500 for matching transition sensing dynamic elements according to various embodiments. Method 500, at block 505, determines a constant transition rate (N... trn Let's begin. As previously described, in some instances, N... trn This can be the number of transitions to be performed. For example, a transition can indicate a change in the state of a cell element from an off state to an on state or from an on state to an off state, where the state of a cell element, as used herein, refers to whether the cell element is on (e.g., on state) or off (e.g., off state). In CTR-DEM logic, the number of transitions can be the number of transitions (e.g., 1 to 0, or 0 to 1) from the unary code of the previous loop.

[0069] In some instances, N trn It can be set to a static value. In other instances, N trn It can be an adjustable value. For example, in some embodiments, N trn This can be set by the user. In other instances, N trn It can be adjusted during operation and / or in real time based on system requirements and / or metrics. In a further embodiment, N trn These can be hard-coded values. In some instances, hard-coded values ​​may be determined based on known signal characteristics of a given use case or one or more common applications. (The above text is about...) Figure 2 and 4 Further discussion will include N trn Tune to the optimal value. In some instances, N trn It can be based on the maximum amplitude of the incremental code plus the additional number of transformations N. extra To determine, as previously described.

[0070] Method 500 can obtain the digital input (e.g., d) at block 510 for the current cycle (e.g., the current sampling interval of the DAC). a [n]) to continue. In various instances, the digital input can be a binary coded digital signal indicating the signal to be converted into an analog signal. In some instances, the digital input of the current loop can be combined with the digital input from the previous loop (e.g., d) a [n-1]) are compared to determine the incremental code, as previously described.

[0071] At box 515, method 500 continues by checking clipping. In some instances, N can be checked based on the numeric input. trn Clipping. Specifically, N trn The value d can be entered with a number. a Compare to ensure that N is accessible. trn The number of transitions generates a corresponding unary code. In some instances, clipping can be checked by ensuring the following condition: d a <N trn / 2 <N u -d a In some instances, if clipping is detected, the number of transitions N can be reduced. trn On the other hand, if N trn If N is too low, then HD2 and other harmonic distortions may occur. In some instances, if N... trn If the value is too low, the clipping detection logic can be configured to add additional transformations (e.g., N). trn +1).

[0072] In some embodiments, method 500 may further include alternatively and / or additionally utilizing one or more redundant unit elements at block 535. As previously described, in some instances, the DAC may further include one or more redundant unit elements. In such embodiments, one or more redundant unit elements may be turned on or off as needed to avoid clipping. In some instances, one or more redundant elements may act as “zero-padding” for the input code and remain in an off state (or, in some instances, an on state) until one or more redundant unit elements are needed to enforce N for a given input code. trn This transition occurs even when the code is close to 0 (e.g., all "0" codes) or full (e.g., all "1" codes). In this configuration, L trn It can be equal to N trn Therefore, in some instances, the check clipping described above can be skipped, and one or more redundant unit elements can be used instead. In other embodiments, one or more redundant unit elements can be used in combination with check clipping.

[0073] At box 520, method 500 determines the number X of unit elements to be turned on (from the off state). on and the number of unit elements to be turned off (from the on state) X off Let's continue. In some instances, X can be determined based on the incremental code Δ[n]. on and X off For example, an increment code can indicate a change in a digital signal from a previous cycle. Therefore, an increment code can indicate a decrease in the input code (which may correspond to a number of additional unit elements to be turned off) or an increase in the input code (which may correspond to a number of additional unit elements to be turned on). Accordingly, in some instances, X on With X off The relationship between them can be expressed as: X on =X off +Δ[n]. When Δ[n] is positive (indicating an increase in digital input), the number of unit elements to be turned on (e.g., X). on The number of unit elements to be turned off (e.g., X) is comparable. off ) more Δ[n]. Conversely, when Δ[n] is negative (indicating a decrease in the numerical input value), X on Comparable to X off Small Δ[n].

[0074] Method 500 continues at block 525 by selecting a cell element for the transition. In various embodiments, random permutation logic may be implemented to select individual cell elements for the transition from the on state to the off state (based on X). off ) and the transition from the off state to the on state (based on X) on As previously described, random permutation logic can include various types of DEM algorithms, including, without limitation, random averaging, clocked averaging, individual level averaging, data-weighted averaging, etc., for randomizing and / or selecting individual unit elements to be turned on or off. In a further embodiment, the random permutation logic may alternatively include or be replaced by a deterministic DEM algorithm. For example, the switched elements may be uniformly distributed over time according to a deterministic pattern and / or sequence, such that timing errors attributable to individual unit elements are uniformly spread over a particular transition. For example, for N trn The number of transformations can be adjusted using random permutation logic, which can be used to adjust idx. on and / or idx off To follow a deterministic pattern and / or sequence of which bits (e.g., corresponding cell elements) are to be turned on or off.

[0075] In some instances, the first permutation logic circuit can be configured based on the input X indicating the number of cell elements to be turned off. offand a signal (idx) indicating which individual unit elements were turned on during a previous cycle (e.g., a previous sampling interval). on This determines which individual unit components should be turned off (e.g., unit components that were previously turned on and need to be turned off). Accordingly, in some instances, idx on This can be equal to the input unary code d of the previous loop. u [n-1]. Therefore, in some instances, the first randomized permutation logic circuit can be selected from the signal idx indicated as having passed, according to a randomization and / or randomness selection algorithm (e.g., a dynamic element matching algorithm). on Select the X unit element to be turned off when it is turned on. off The number of unit elements. The first random permutation logic can then output a signal sel indicating which unit elements have been selected to be turned off. off .

[0076] The second random permutation logic can be configured based on the input X indicating the number of unit elements to be turned on. on and a signal indicating which individual unit elements were turned off during the previous cycle (idx) off This determines which individual unit components should be turned on (e.g., unit components that were previously turned off and are now to be turned on). Accordingly, idx off It can be equal to d u The inverse of [n-1]. Therefore, in some instances, the second random permutation logic can be derived from the signal idx indicated as having passed, based on a randomization and / or randomness selection algorithm (e.g., a dynamic element matching algorithm). off Select the X unit element to be turned on when turning off. on The number of unit elements. The second random permutation logic can output a signal sel indicating which unit elements have been selected to be turned on. on .

[0077] Method 500 further includes generating unary code for the current loop at box 530. In various instances, this can be based on the sel indicating the selected unit for the transition. on and sel off The output generates the unary code for the current loop. As previously described, in some instances, the output signal sel is used. on and sel off It can be provided as a control signal to the multiplexer to select between the multiplexer's inputs. Specifically, the multiplexer's inputs may include the input unary code from the previous loop, d u [n-1] inputs, logic 1 (e.g., logic high) and logic 0 (e.g., logic low). Based on some examples, the sel in the i-th bit position... off (sel off,iThe value can be set to 1 if the corresponding i-th unit element needs to be turned off, and is set to 0 if no change is needed. Similarly, the value of sel in the i-th bit position is... on (sel on,i The value can be set to 1 if the corresponding i-th unit element is to be turned on, and is set to 0 if no change is needed. In some instances, sel off,i and sel on,i A 2-bit control signal can be generated for the multiplexer to select various inputs. Therefore, to turn off the i-th unit element of the DAC, a control signal of 10 can be generated, indicating that the multiplexer should output logic 0. Similarly, to turn on the i-th unit element of the DAC, a control signal of 01 can be generated, indicating that the multiplexer should output logic 1. If a control signal of 00 is output, it indicates that the i-th unit element should not change, and the multiplexer can output the unary code d from the i-th position of the previous cycle. u,i [n-1]. In this way, in some instances, the multiplexer can generate a new input unary code d for the current loop. u [n]. In a further example, for instance, the current input unary loop can then be stored at a flip-flop, which can be clocked by a clock signal with a period equal to the sampling interval. In yet another embodiment, the generation of unary codes can be performed by logic or components other than a multiplexer. For example, as long as the generated unary code reflects the transition of the unit element (e.g., to turn on and off), based on the signal sel off and sel on Other suitable circuits can be used to generate the unary code d described above. u [n]. Accordingly, in a further example, the state of each unit element of the DAC can be controlled according to a unary code, as previously discussed regarding... Figure 3 As described.

[0078] The techniques and processes described above with respect to various embodiments may be performed by one or more systems 100 and / or their subsystems and components, such as those described above with respect to... Figures 1 to 2 The described change-aware DEM encoder logic circuit 200 is capable of performing methods as described herein, provided by various other embodiments.

[0079] While some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Furthermore, while the various methods and processes described herein may be described with respect to specific structures and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any particular structure and / or functional architecture, but can instead be implemented in any suitable hardware configuration. Similarly, while some functionality may be attributed to one or more system components, unless the context otherwise requires, this functionality may be distributed among various other system components according to several embodiments.

[0080] Furthermore, although the steps of the methods and processes described herein are presented in a specific order for ease of description, these steps may be rearranged, added, and / or omitted according to various embodiments unless the context otherwise requires. Moreover, steps described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described with respect to a particular architecture and / or a system may be organized in an alternative architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without certain features are described for ease of description and to illustrate aspects of those embodiments, various components and / or features described herein with respect to particular embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context otherwise requires. Therefore, although several embodiments have been described above, it will be understood that the invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A method comprising: Determine the number of conversions N for the digital-to-analog converter. trn The number of unit elements that transition from the ON state to the OFF state or from the OFF state to the ON state; At least in part based on N trn Determine the first number of unit elements of the digital-to-analog converter to be turned on from the off state; At least in part based on N trn Determine a second number of unit elements of the digital-to-analog converter to be turned off from the on state; The first number of individual unit elements to be turned on are selected from one or more unit elements of the digital-to-analog converter that are in the off state via dynamic element matching logic. and The second number of individual unit elements to be turned off are selected from one or more unit elements of the digital-to-analog converter that are in the on state via the dynamic element matching logic.

2. The method according to claim 1, further comprising: Generate a unary code, wherein the unary code is configured to turn on the selected first number of individual unit elements and turn off the selected second number of individual unit elements, wherein each corresponding bit position of the unary code controls the state of the corresponding unit element corresponding to the corresponding bit position; and The state of each of the plurality of unit elements of the digital-to-analog converter is controlled based on the unary code.

3. The method according to claim 1, further comprising: Determine whether it is possible to perform N of the plurality of unit elements of the digital-to-analog converter for the current value of the digital input during the current sampling interval. trn .

4. The method of claim 3, wherein determining whether the N can be executed trn Further includes: Determine whether the current value of the numerical input is less than (N) trn / 2), and further determine that the total number of unit elements minus the current value of the digital input is greater than (N trn / 2).

5. The method of claim 3, further comprising: Based on the determination that N cannot be executed trn And adjust N trn Adjusting N trn Includes reducing the value N trn .

6. The method of claim 1, wherein N trn Set to the maximum value of the absolute value of the incremental code plus the corresponding number of transitions N. extra Wherein N extra It is an even number, and the increment code indicates the change of the current value of the digital input during the current sampling interval from the previous value of the digital input during the previous sampling interval.

7. The method of claim 1, wherein selecting the first number of individual unit elements to be turned on and the second number of individual unit elements to be turned off further comprises: According to a randomization algorithm, the first number of individual unit elements to be turned on are selected from the one or more unit elements of the digital-to-analog converter that are in the off state; and According to the randomization algorithm, the second number of individual unit elements to be turned off are selected from the one or more unit elements of the digital-to-analog converter that are in the on state.

8. The method of claim 7, wherein the randomization algorithm comprises at least one of random averaging, clock-controlled averaging, individual level averaging, or data-weighted averaging.

9. A logic circuit comprising: A register configured to store a constant switching rate value, wherein the constant switching rate value is converted at each sampling interval by the number of switching operations N of the digital-to-analog converter. trn The number of unit elements that transition from the on state to the off state or from the off state to the on state is given. Dynamic element matching circuitry coupled to the register, wherein the dynamic element matching circuitry is configured to: At least in part based on N trn Determine the first number of unit elements of the digital-to-analog converter to be turned on from the off state; At least in part based on N trn Determine a second number of unit elements of the digital-to-analog converter to be turned off from the on state; A first signal is generated, wherein the first signal indicates the selection of the first number of individual unit elements, wherein the first signal further identifies the individual unit element to be turned on among one or more unit elements of the digital-to-analog converter that are in the off state; and A second signal is generated, wherein the second signal indicates the selection of the second number of individual unit elements, wherein the second signal further identifies the individual unit element to be turned off among one or more unit elements of the digital-to-analog converter that are in the on state.

10. The logic circuit of claim 9, wherein the dynamic element matching circuit is further configured to: A unary code for the current sampling interval is generated based on the first and second signals, wherein the unary code is configured to turn on the identified first number of individual unit elements and turn off the identified second number of individual unit elements, wherein each corresponding bit position of the unary code controls the state of the corresponding unit element corresponding to the corresponding bit position; and The state of each of the plurality of unit elements of the digital-to-analog converter is controlled based on the unary code.

11. The logic circuit of claim 10, wherein the dynamic element matching circuit further comprises a multiplexer, wherein the multiplexer receives at its input a logic low level, a logic high level, and a unary code of a previous sampling interval, wherein the multiplexer is configured to output the unary code of the current sampling interval based at least in part on the first and second signals.

12. The logic circuit of claim 9, wherein the dynamic element matching circuit is further configured to: Determine whether it is possible to perform N of the plurality of unit elements of the digital-to-analog converter for the current value of the digital input during the current sampling interval. trn .

13. The logic circuit of claim 12, wherein determining whether the N can be executed... trn Further includes: Determine whether the current value of the numerical input is less than (N) trn / 2), and further determine that the total number of unit elements minus the current value of the digital input is greater than (N trn / 2).

14. The logic circuit of claim 12, wherein generating the first and second signals further comprises: The first number of individual unit elements are selected from the one or more unit elements of the digital-to-analog converter in the off state according to the randomization algorithm; and The second number of individual unit elements are selected from the one or more unit elements of the digital-to-analog converter that are in the on state according to the randomization algorithm.

15. A system comprising: A digital-to-analog converter comprising multiple unit elements, each configured to be controllable by a control signal; An encoder coupled to the digital-to-analog converter, the encoder being configured to generate the control signal based on a digital input, wherein the encoder includes circuitry configured to: Determine the number of conversions N for the digital-to-analog converter. trn The number of unit elements that transition from the ON state to the OFF state or from the OFF state to the ON state; Determine the N trn The first number of unit elements in the digital-to-analog converter to be turned on from the off state; Determine the N trn The second number of unit elements of the digital-to-analog converter to be turned off from the on state; A first signal is generated, wherein the first signal indicates the selection of the first number of individual unit elements, wherein the first signal further identifies the individual unit element to be turned on among one or more unit elements of the digital-to-analog converter that are in the off state; and A second signal is generated, wherein the second signal indicates the selection of the second number of individual unit elements, wherein the second signal further identifies the individual unit element to be turned off among one or more unit elements of the digital-to-analog converter that are in the on state.

16. The system of claim 15, wherein the circuitry is further configured to: The control signal for the current sampling interval is generated based on the first and second signals, wherein the control signal is configured to turn on the identified first number of individual unit elements and turn off the identified second number of individual unit elements, wherein each corresponding bit position of the control signal controls the state of the corresponding unit element corresponding to the corresponding bit position, wherein the control signal is unary coded; and The state of each of the plurality of unit elements of the digital-to-analog converter is controlled based on the control signal.

17. The system of claim 16, wherein the circuitry further comprises a multiplexer, wherein the multiplexer receives at its input a control signal of logic low, logic high, and a previous sampling interval, wherein the multiplexer is configured to output the control signal of the current sampling interval based at least in part on the first and second signals.

18. The system of claim 15, wherein the circuitry is further configured to determine whether N of the plurality of unit elements of the digital-to-analog converter can be performed for the current value of the digital input during the current sampling interval. trn .

19. The system of claim 18, wherein determining whether the N can be executed trn It further includes determining whether the current value of the digital input is less than (N) trn / 2), and further determine that the total number of unit elements minus the current value of the digital input is greater than (N trn / 2).

20. The system of claim 15, wherein generating the first and second signals further comprises: The first number of individual unit elements are selected from the one or more unit elements of the digital-to-analog converter in the off state according to the randomization algorithm; and The second number of individual unit elements are selected from the one or more unit elements of the digital-to-analog converter that are in the on state according to the randomization algorithm.

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