A switching circuit and switching power supply

Abstract

The embodiment of the application provides a kind of switch circuit and switching power supply, it is related to electronic circuit technical field, can reduce dead time, reduce dead zone loss, and then reduce the loss of switch circuit.The first switch is coupled between the first node and the first reference ground in the switch circuit;The control end of the first switch is coupled with the output end of the first drive stage circuit;The first input end of the first drive stage circuit is coupled with the output end of the logic processing circuit, and the grounding terminal is coupled with the first reference ground;The second switch is coupled between the first voltage input end and the first node;The control end of the second switch is coupled with the second switch signal input end;The first input end of the high-pass filter is coupled with the first voltage input end, the second input end is coupled with the second voltage input end, and the output end is coupled with the second input end of the first drive stage circuit;The logic processing circuit is used to cut off the coupling between the grounding terminal of the first drive stage circuit and the first reference ground after the second switch is turned off before the first switch is turned on.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a switching circuit and a switching power supply. Background Art

[0002] Currently, in a switching circuit, the input voltage can be converted into a stable output voltage by controlling the time ratio of multiple switches being turned on and off. In the prior art, the structure of the switching circuit 01 is as follows: Figure 1 As shown, it includes a first power tube S1, a second power tube S2, a first power tube driving stage circuit 1, a second power tube driving stage circuit 2, an inductor L, a capacitor C, a voltage input terminal Vin, a voltage output terminal Vo, a first switching signal input terminal PWML and a second switching signal input terminal PWMH. The first power tube S1 includes a first parasitic diode D1, and the second power tube S2 includes a second parasitic diode D2. In which, the first power tube S1 is an N-type tube, and the second power tube S2 is a P-type tube. The first power tube S1 and the second power tube S2 are coupled to the switching node Lx; the first power tube S1 is coupled between the switching node Lx and the reference ground GND; the second power tube S2 is coupled between the voltage input terminal Vin and the switching node Lx; the control terminal of the first power tube S1 is coupled to the first switching signal input terminal PWML through the first power tube driver stage circuit 1; the control terminal of the second power tube S2 is coupled to the second switching signal input terminal PWMH through the second power tube driver stage circuit 2; the inductor L is coupled between the switching node Lx and the voltage output terminal Vo, and the capacitor C is coupled between the voltage output terminal Vo and the reference ground GND.

[0003] Figure 2 for Figure 1 The waveform diagram of the signal of the switching circuit 01 is shown. When the first switching signal input terminal PWML receives a high level signal, the first power tube S1 is turned on, and when the second switching signal input terminal PWMH receives a low level signal, the second power tube S2 is turned on. Figure 1 and Figure 2 By controlling the time ratio of the first power tube S1 and the second power tube S2 to be alternately turned on and off, the voltage provided by the voltage input terminal Vin can be output to the voltage output terminal Vo. In order to avoid the first power tube S1 and the second power tube S2 in the switching circuit 01 being turned on at the same time during the switching process, causing the voltage input terminal Vin and the reference ground GND to be directly connected, thereby causing the power supply connected to the voltage input terminal Vin to burn out, the reference ground GND is used to connect the first power tube S1 and the second power tube S2 to the switching circuit 01. Figure 2Generally, there is a simultaneous-off time in the process of alternating on and off of the first power tube S1 and the second power tube S2, and the time when the first power tube S1 and the second power tube S2 are simultaneously turned off is called dead time. In the dead time, the voltage of the switch node Lx gradually decreases, and when the voltage of the switch node Lx decreases to a certain value, the first parasitic diode D1 is turned on, and the inductor L current continues to flow through the first parasitic diode D1 to ensure that the voltage output terminal Vo stably outputs voltage.

[0004] However, since the conduction voltage drop of the parasitic diode (for example, about 0.7V) is much larger than the conduction voltage drop of the power tube (for example, 10mV), when the same current flows, the power loss of the first parasitic diode D1 is several orders of magnitude different from the power loss of the power tube, so the conduction loss of the first parasitic diode D1 greatly increases the loss of the switching circuit 01. In addition, as the switching frequency of the switching circuit 01 increases, the proportion of the dead time also increases, so the dead time loss becomes one of the main losses of the high-frequency switching circuit. SUMMARY

[0005] The embodiments of the present application provide a switching circuit and a switching power supply, which can reduce the dead time, reduce the dead time loss, and further reduce the loss of the switching circuit.

[0006] To achieve the above object, the present application adopts the following technical solutions:

[0007] In a first aspect, a switching circuit is provided. The switching circuit includes a first switch, a first driving stage circuit, a second switch, a high-pass filter, a logic processing circuit, a first voltage input terminal, a second voltage input terminal, a voltage output terminal, a first switch signal input terminal, a second switch signal input terminal, and a first reference ground. The first switch is coupled between a first node and the first reference ground. A control terminal of the first switch is coupled to an output terminal of the first driving stage circuit. A first input terminal of the first driving stage circuit is coupled to an output terminal of the logic processing circuit, and a ground terminal of the first driving stage circuit is coupled to the first reference ground. The second switch is coupled between the first voltage input terminal and the first node. A control terminal of the second switch is coupled to the second switch signal input terminal. A first input terminal of the high-pass filter is coupled to the first voltage input terminal, a second input terminal of the high-pass filter is coupled to the second voltage input terminal, and an output terminal of the high-pass filter is coupled to a second input terminal of the first driving stage circuit. A first input terminal of the logic processing circuit is coupled to the first switch signal input terminal, and a second input terminal of the logic processing circuit is coupled to the second switch signal input terminal. The logic processing circuit is configured to cut off the coupling between the ground terminal of the first driving stage circuit and the first reference ground after the second switch is turned off and before the first switch is turned on. The first node is coupled to the voltage output terminal. In the operation of the switching circuit, the first switch and the second switch are turned on and off alternately. By controlling the ratio of the time when the first switch and the second switch are turned on and off, the voltage provided by the first voltage input terminal can be converted into a required voltage output from the voltage output terminal. In addition, during the process of the first switch and the second switch being turned on and off alternately, at the moment when the second switch is turned off, before the first switch is turned on, the energy of the parasitic inductance generated between the first voltage input terminal and the second switch raises the voltage of the first voltage input terminal. Since the switching circuit includes the high-pass filter, which is coupled to the first voltage input terminal, the feedforward effect of the high-pass filter causes the high-pass filter to provide the voltage provided by the second voltage input terminal to the second input terminal of the first driving stage circuit after raising the voltage. In this way, the actual working voltage of the first driving stage circuit in the dead time is higher than the voltage provided by the second voltage input terminal in the non-dead time, so that the first driving stage circuit drives the first switch to be turned on in advance under the action of the feedforward voltage, i.e., the actual working voltage. In the prior art, the first switch is turned off in the dead time, and only in the non-dead time, the voltage received by the first switch signal input terminal can control the first driving stage circuit to receive the voltage provided by the second voltage input terminal and drive the first switch to be turned on. However, in the embodiment of the present application, the first switch is driven to be turned on in advance by the feedforward effect of the high-pass filter in the dead time, thereby effectively reducing the dead time and the dead time loss, and further reducing the loss of the switching circuit and improving the efficiency of the switching circuit.On this basis, before the second switch is opened and the first switch is turned on, the logic processing circuit can cut off the coupling between the ground end of the first driving stage circuit and the first reference ground, thereby avoiding the high-pass filter from releasing the voltage provided by the second voltage input end after the voltage is raised by the first reference ground.

[0008] In a possible implementation, the high-pass filter comprises a first capacitor and a first resistor; the first capacitor is coupled between the first voltage input end and the second input end of the first driving stage circuit; and the first resistor is coupled between the second voltage input end and the second input end of the first driving stage circuit. At the moment when the second switch is opened and before the first switch is turned on, the energy of the parasitic inductance raises the voltage of the first voltage input end. At this time, the voltage of one end of the first capacitor connected to the first voltage input end is raised, which is greater than the voltage of the first voltage input end. At the same time, since the high-pass filter comprises the first capacitor, the voltage of the other end of the first capacitor can be raised by the feedforward effect of the first capacitor in the high-pass filter and provided to the first driving stage circuit. In this way, the actual working voltage of the first driving stage circuit is raised, which is higher than the voltage provided by the second voltage input end controlled by the previous stage. Therefore, the first driving stage circuit will drive the first switch to turn on in advance under the action of the feedforward voltage.

[0009] In a possible implementation, the logic processing circuit comprises a flip-flop and an OR gate; the second switch signal input end is coupled to the clock end of the flip-flop; the reset end of the flip-flop is coupled to the first switch signal input end; the flip-flop further comprises an input end for receiving a fixed high level or a fixed low level; the output end of the flip-flop is coupled to the first input end of the OR gate; the second input end of the OR gate is coupled to the first switch signal input end; and the output end of the OR gate is coupled to the first input end of the first driving stage circuit. When the flip-flop comprises the input end for receiving a fixed high level, the output end of the flip-flop will be triggered according to the rising edge or the falling edge of the signal provided by the second switch signal input end received by the clock end, and the high level signal of the signal output by the output end of the flip-flop. When the flip-flop comprises the input end for receiving a fixed low level, the output end of the flip-flop will be triggered according to the rising edge or the falling edge of the signal provided by the second switch signal input end received by the clock end, and the low level signal of the signal output by the output end of the flip-flop. In addition, since the reset end of the flip-flop is coupled to the first switch signal input end, when the signal provided by the first switch signal input end changes from low level to high level or from high level to low level, the signal output by the output end of the flip-flop returns to the previous signal. The output end of the OR gate will output the corresponding signal to the first input end of the first driving stage circuit according to the signals of the first input end and the second input end, so as to cut off the coupling between the ground end of the first driving stage circuit and the first reference ground.

[0010] In a possible implementation, the logic processing circuit includes a delay circuit, a first AND gate, a second AND gate, a first inverter, a second inverter, and an OR gate; the second switch signal input end is coupled to the first input end of the first AND gate through the delay circuit, and is coupled to the second input end of the first AND gate through the first inverter; the output end of the first AND gate is coupled to the first input end of the second AND gate, the first switch signal input end is coupled to the second input end of the second AND gate through the second inverter, and the output end of the second AND gate is coupled to the first input end of the OR gate; the second input end of the OR gate is coupled to the first switch signal input end, and the output end of the OR gate is coupled to the first input end of the first drive stage circuit. Taking, for example, a case where the signal received by the second switch signal input end changes from a high-level signal to a low-level signal and the signal received by the first switch signal input end changes from a low-level signal to a high-level signal, after the signal received by the second switch signal input end is delayed by the delay circuit, the output end of the delay circuit outputs a high-level signal, and at the same time, the signal received by the second switch signal input end outputs a high-level signal after passing through the first inverter; one input end of the first AND gate receives the high-level signal output by the output end of the delay circuit, and the other input end receives the high-level signal output by the first inverter, so that the output end of the first AND gate outputs a high-level signal; the input end of the second inverter receives the low-level signal received by the first switch signal input end, and the output end of the second inverter outputs a high-level signal; one input end of the second AND gate receives the high-level signal output by the output end of the first AND gate, and the other input end receives the high-level signal output by the output end of the second inverter, and the output end of the second AND gate outputs a high-level signal. During this time, one input end of the OR gate receives the high-level signal output by the output end of the second AND gate, and the other input end receives the low-level signal provided by the first switch signal input end, so that the output end of the OR gate outputs a high-level signal, which can control the coupling between the ground end of the first drive stage circuit and the first reference ground to be disconnected.

[0011] In a possible implementation, the delay circuit includes n third inverters connected in series; where n≥2, n is a positive even number. Here, the n third inverters connected in series can output the signal received by the second switch signal input end after delaying for a certain time.

[0012] In a possible implementation, the delay circuit includes a second capacitor and a second resistor connected in series. Here, the second capacitor and the second resistor connected in series can output the signal received by the second switch signal input end after delaying for a certain time.

[0013] In a possible implementation, the first driving stage circuit includes a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch; the third switch and the fourth switch are coupled to the second node; the control end of the first switch is coupled to the second node; the third switch is coupled between the output end of the high-pass filter and the second node, and the fourth switch is coupled between the second node and the first reference ground; the fifth switch is coupled between the second voltage input end and the control end of the third switch; the sixth switch is coupled between the control end of the third switch and the first reference ground; the control end of the fifth switch and the control end of the sixth switch are coupled to the first switch signal input end; the seventh switch is coupled between the second voltage input end and the control end of the fourth switch; the eighth switch is coupled between the control end of the fourth switch and the first reference ground; the control end of the seventh switch and the control end of the eighth switch are coupled to the output end of the logic processing circuit. The third switch is a pull-up tube in the first driving stage circuit, the fourth switch is a pull-down tube in the first driving stage circuit, and the third switch and the fourth switch are used to control the voltage of the control end of the first switch. The fifth switch and the sixth switch are used to control the voltage of the control end of the third switch, and the seventh switch and the eighth switch are used to control the voltage of the control end of the fourth switch.

[0014] In a possible implementation, the switch circuit further includes a second driving stage circuit; the control end of the second switch is coupled to the second switch signal input end through the second driving stage circuit. Since the control end of the second switch is coupled to the second driving stage circuit, the driving capability of the control end of the second switch can be improved, and the time for the second switch to turn on or off can be reduced.

[0015] In a possible implementation, the switch circuit further comprises a third voltage input terminal and a second reference ground, and the second driving stage circuit further comprises a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch and a fourteenth switch. The ninth switch is coupled between the third voltage input terminal and the control terminal of the second switch, and the tenth switch is coupled between the control terminal of the second switch and the second reference ground. The eleventh switch is coupled between the third voltage input terminal and the control terminal of the ninth switch, and the twelfth switch is coupled between the control terminal of the ninth switch and the second reference ground. The control terminal of the eleventh switch and the control terminal of the twelfth switch are both coupled to the second switch signal input terminal. The thirteenth switch is coupled between the third voltage input terminal and the control terminal of the tenth switch, and the fourteenth switch is coupled between the control terminal of the tenth switch and the second reference ground. The control terminal of the thirteenth switch and the control terminal of the fourteenth switch are both coupled to the second switch signal input terminal. The ninth switch is a pull-up tube in the second driving stage circuit, the tenth switch is a pull-down tube in the second driving stage circuit, and the ninth switch and the tenth switch are configured to control the voltage at the control terminal of the second switch. The eleventh switch and the twelfth switch are configured to control the voltage at the control terminal of the ninth switch, and the thirteenth switch and the fourteenth switch are configured to control the voltage at the control terminal of the tenth switch.

[0016] In a possible implementation, the switch circuit further comprises an inductor and a third capacitor. The inductor is coupled between the first node and the voltage output terminal, and the third capacitor is coupled between the voltage output terminal and the first reference ground. The inductor can function as a freewheeling diode, so that the voltage output terminal can stably output a voltage, and the voltage output by the voltage output terminal can avoid high-low changes. The third capacitor can function as a voltage stabilizer, and can reduce the ripple of the high-low changes of the voltage output by the voltage output terminal.

[0017] In a possible implementation, the first switch and the second switch are insulated gate bipolar transistors, metal-oxide-semiconductor field effect transistors or PN junction field effect transistors.

[0018] In a possible implementation, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch are insulated gate bipolar transistors, metal-oxide-semiconductor field effect transistors or PN junction field effect transistors.

[0019] In a second aspect, a switching circuit is provided. The switching circuit comprises a first switch, a first driving stage circuit, a second switch, a high-pass filter, a logic processing circuit, a first voltage input terminal, a second voltage input terminal, a voltage output terminal, a first switch signal input terminal, a second switch signal input terminal, and a first reference ground. The first switch is coupled between a first node and the first reference ground; a control terminal of the first switch is coupled with an output terminal of the first driving stage circuit; a ground terminal of the first driving stage circuit is coupled with the first reference ground; the second switch is coupled between the first voltage input terminal and the first node; a control terminal of the second switch is coupled with the second switch signal input terminal; a first input terminal of the high-pass filter is coupled with the first voltage input terminal, a second input terminal of the high-pass filter is coupled with the second voltage input terminal, and an output terminal of the high-pass filter is coupled with a second input terminal of the first driving stage circuit; the logic processing circuit comprises a flip-flop and an OR gate; the second switch signal input terminal is coupled with a clock terminal of the flip-flop; a reset terminal of the flip-flop is coupled with the first switch signal input terminal; the flip-flop further comprises an input terminal for receiving a fixed high level or a fixed low level; an output terminal of the flip-flop is coupled with a first input terminal of the OR gate, a second input terminal of the OR gate is coupled with the first switch signal input terminal, and an output terminal of the OR gate is coupled with a first input terminal of the first driving stage circuit. The specific structure of the first driving stage circuit and the high-pass filter, the type of each switch, and other structures of the switching circuit can be referred to the first aspect above, and will not be described here again. In addition, the switching circuit has the same technical effects as the foregoing embodiments, and thus will not be described here again.

[0020] In a third aspect, a switching circuit is provided. The switching circuit includes a first switch, a first driver stage circuit, a second switch, a high-pass filter, a logic processing circuit, a first voltage input terminal, a second voltage input terminal, a voltage output terminal, a first switch signal input terminal, a second switch signal input terminal, and a first reference ground. The first switch is coupled between a first node and a first reference ground; the control terminal of the first switch is coupled to the output terminal of the first driver stage circuit; and the ground terminal of the first driver stage circuit is coupled to the first reference ground. The second switch is coupled between the first voltage input terminal and the first node; the control terminal of the second switch is coupled to the second switch signal input terminal. The first input terminal of the high-pass filter is coupled to the first voltage input terminal, the second input terminal of the high-pass filter is coupled to the second voltage input terminal, and the output terminal of the high-pass filter is coupled to the second input terminal of the first driver stage circuit. The logic processing circuit includes a delay circuit, a first AND gate, a second AND gate, a first inverter, a second inverter, and an OR gate. The second switch signal input terminal is coupled to the first input terminal of the first AND gate through a delay circuit; the second switch signal input terminal is also coupled to the second input terminal of the first AND gate through a first inverter; the output terminal of the first AND gate is coupled to the first input terminal of the second AND gate, the first switch signal input terminal is coupled to the second input terminal of the second AND gate through a second inverter, and the output terminal of the second AND gate is coupled to the first input terminal of the OR gate; the second input terminal of the OR gate is coupled to the first switch signal input terminal, and the output terminal of the OR gate is coupled to the first input terminal of the first driver stage circuit. Among them, the specific structure of the first driver stage circuit and the high-pass filter, the type of each switch, and other structures of the switch circuit can all refer to the above-mentioned first aspect and will not be repeated here. In addition, the switch circuit has the same technical effects as the aforementioned embodiment, and will not be repeated here.

[0021] In a fourth aspect, a switching power supply is provided. The switching power supply includes a controller and the aforementioned switching circuit; a first switching signal input terminal and a second switching signal input terminal are both coupled to the controller. The controller is configured to output a first switching signal and provide the first switching signal to the first switching signal input terminal to control the on / off state of the first switch. The controller is also configured to output a second switching signal and provide the second switching signal to the second switching signal input terminal to control the on / off state of the second switch. This switching power supply has the same technical effects as the aforementioned embodiments, and thus will not be further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a switching circuit provided by the prior art;

[0023] Figure 2 for Figure 1 Waveform diagram of each signal in the switching circuit shown;

[0024] Figure 31 is a schematic diagram of the structure of a switching circuit;

[0025] Figure 4 A schematic diagram of the structure of a switching power supply provided in an embodiment of the present application;

[0026] Figure 5 A schematic structural diagram of a switching circuit provided in an embodiment of the present application;

[0027] Figure 6 A schematic structural diagram of a switch circuit provided in another embodiment of the present application;

[0028] Figure 7a A schematic structural diagram of a switch circuit provided in yet another embodiment of the present application;

[0029] Figure 7b A schematic structural diagram of a switch circuit provided in yet another embodiment of the present application;

[0030] Figure 8 for Figure 7b Waveform diagram of each signal in the switching circuit shown;

[0031] Figure 9 A schematic structural diagram of a switch circuit provided in another embodiment of the present application;

[0032] Figure 10 for Figure 9 Waveform diagram of each signal in the switching circuit shown;

[0033] Figure 11 A schematic structural diagram of a switching circuit provided in yet another embodiment of the present application.

[0034] Reference numerals:

[0035] 01-switching circuit; 02-controller; 1-first power tube driver stage circuit; 2-second power tube driver stage circuit; 10-first driver stage circuit; 20-high-pass filter; 30-logic processing circuit; 40-second driver stage circuit; 301-trigger; 302-OR gate; 303-fourth inverter; 304-delay circuit; 305-first AND gate; 306-second AND gate; 307-first inverter; 308-second inverter. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0037] Hereinafter, the terms "first", "second", and the like are used only to describe convenience and do not imply or suggest relative importance or a specific number of the technical features indicated. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. For example, a plurality of processing units refers to two or more processing units.

[0038] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood broadly, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through an intermediate medium. In addition, the term "electrical connection" can be direct electrical connection, or indirect electrical connection through an intermediate medium. In addition, the term "coupling" can mean that two or more components have direct physical contact or electrical contact, or that two or more components do not have direct contact with each other, but are electrically connected or interact through an intermediate medium.

[0039] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described as "exemplary" or "for example" in the present application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the term "exemplary" or "for example" is intended to present concepts in a concrete manner.

[0040] At present, the loss in the dead time (which can also be referred to as dead time loss) is one of the main losses of the switching circuit 01. In order to improve the energy density of the switching circuit 01 and reduce the output ripple, the speed of the switching circuit 01 is continuously increasing, which has evolved from several hundred KHz to the order of 100 MHz, and the corresponding dead time loss is also continuously increasing.

[0041] In order to reduce the dead time and reduce the dead time loss, a logic interlocking dead time scheme can be used, Figure 3 A structural schematic diagram of a switching circuit 01 using a logic interlocking dead time scheme is provided, as shown in Figure 3As shown, the switching circuit 01 includes a first power transistor (also called an upper transistor) S1 and a second power transistor (also called a lower transistor) S2. The first power transistor S1 includes a first parasitic diode D1, and the second power transistor S2 includes a second parasitic diode D2. The first power transistor S1 and the second power transistor S2 are coupled to a switching node Lx; the first power transistor S1 is coupled between the voltage input terminal Vin and the switching node Lx; the second power transistor S2 is coupled between the switching node Lx and the first reference ground GND. The control terminal of the first power transistor S1 is coupled to a first power transistor driver stage circuit 1, which includes two inverters connected in series. The first power transistor driver stage circuit 1 is coupled to the output terminal of an AND gate a. One input terminal of the AND gate a is coupled to the second switching signal input terminal PWMH, and the other input terminal of the AND gate a is coupled to the control terminal of the second power transistor S2. The control terminal of the second power transistor S2 is coupled to a second power transistor driver stage circuit 2, which includes two inverters connected in series. The second power transistor driver stage circuit 2 is coupled to the output terminal of an AND gate b. One input terminal of the AND gate b is coupled to the control terminal of the first power transistor S1 via an inverter Inv (inverter) 1, and the other input terminal of the AND gate b is coupled to the second switching signal input terminal PWMH via an inverter Inv (inverter) 2. An inductor L is coupled between a switching node Lx and a voltage output terminal Vo. A capacitor C is coupled between the voltage output terminal Vo and a first reference ground GND. When the switch circuit 01 adopts a logic interlock dead zone solution, by real-time detection of the switch control gate signals of the control terminals of the first power tube S1 and the second power tube S2, the other power tube is turned on only after the gate voltage of one of the first power tube S1 and the second power tube S2 controls the power tube to reach the off condition, thereby reducing the dead zone time and ensuring that the two power tubes are not turned on at the same time.

[0042] However, when the logic interlocking dead zone scheme is adopted, on the one hand, because the length of the coupling between the control end of the first power tube S1 and one input end of the AND gate b and the length of the coupling between the control end of the second power tube S2 and one input end of the AND gate a are too long, the feedback signal path of the switching control gate signal of the control end of the first power tube S1 to one input end of the AND gate b and the switching control gate signal of the control end of the second power tube S2 to one input end of the AND gate a is too long, which limits the reduction of the dead zone time. On the other hand, because the detection signal (i.e. the switching control gate signal of the control end of the second power tube S2) received by one input end of the AND gate a needs to wait for the driving delay Tdrive of the first power tube driving stage circuit 1 after the detection signal is stable before controlling the first power tube S1 to act, and similarly, the detection signal (i.e. the switching control gate signal of the control end of the first power tube S1) received by one input end of the AND gate b needs to wait for the driving delay Tdrive of the second power tube driving stage circuit 2 after the detection signal is stable before controlling the second power tube S2 to act, and this driving delay becomes the bottleneck of reducing the dead zone time. If the driving capability of the first power tube driving stage circuit 1 is increased (for example, the size of the driving MOS tube in the first power tube driving stage circuit 1 is increased) to reduce the driving delay of the subsequent stage, i.e. the driving delay of the first power tube driving stage circuit 1 to the first power tube S1, and the size of the driving MOS tube in the first power tube driving stage circuit 1 is increased, which will cause the driving delay of the current stage, i.e. the driving delay of the output end of the AND gate a to the first power tube driving stage circuit 1, and similarly, increasing the driving capability of the second power tube driving stage circuit 2 will cause similar problems as increasing the driving capability of the first power tube driving stage circuit 1, and therefore, the driving delay Tdrive always exists and is determined by the FOM (figure of merit, performance coefficient) value representing the intrinsic process, which can only be optimized with the evolution of the process and cannot be fundamentally broken through. In summary of the above two aspects, when the logic interlocking dead zone scheme is adopted, the reduction of the dead zone time is limited, and the dead zone time can only be in the order of ns, which can be applied in low-frequency (kHz to MHz level) switching circuits, but cannot be accepted in high-frequency (several tens to several hundred MHz) switching circuits. Based on the above, in order to reduce the dead zone loss, the embodiments of the present application provide a switching power supply, as shown in the figure, which includes a switching circuit (also referred to as a buck (buck) converter) 01 and a controller 02. Figure 4 The main structure of the above-mentioned switching circuit 01 is as shown in the figure.

[0043] The main structure of the above-mentioned switching circuit 01 is as shown in the figure. Figure 4As shown, it includes a first switch M1, a first drive stage circuit 10, a second switch M2, a high-pass filter 20, a logic processing circuit 30, a first voltage input terminal PVDD, a second voltage input terminal VDRIVE, a voltage output terminal Vo, a first switch signal input terminal PWML, a second switch signal input terminal PWMH and a first reference ground GND.

[0044] The first switching signal input terminal PWML and the second switching signal input terminal PWMH are both coupled to the controller 02. The controller 02 is used to output the first switching signal PWML and provide the first switching signal PWML to the first switching signal input terminal PWML to control the on or off of the first switch M1. The controller 02 is also used to output the second switching signal PWMH and provide the second switching signal PWMH to the second switching signal input terminal PWMH to control the on or off of the second switch M2.

[0045] Among them, such as Figure 4 As shown, the first switch M1 is coupled between the first node Lx and the first reference ground GND; the control terminal LG of the first switch M1 is coupled to the output terminal p of the first driver stage circuit 10; the first input terminal d of the first driver stage circuit 10 is coupled to the output terminal e of the logic processing circuit 30, and the ground terminal f of the first driver stage circuit 10 is coupled to the first reference ground GND. The second switch M2 is coupled between the first voltage input terminal PVDD and the first node Lx; the control terminal HG of the second switch M2 is coupled to the second switching signal input terminal PWMH. The first input terminal m of the high-pass filter 20 is coupled to the first voltage input terminal PVDD, the second input terminal o of the high-pass filter 20 is coupled to the second voltage input terminal VDRIVE, and the output terminal n of the high-pass filter 20 is coupled to the second input terminal g of the first driver stage circuit 10. A first input terminal h of the logic processing circuit 30 is coupled to the first switching signal input terminal PWML, and a second input terminal i of the logic processing circuit 30 is coupled to the second switching signal input terminal PWMH. The logic processing circuit 30 is configured to disconnect the ground terminal f of the first driver stage circuit 10 from the first reference ground GND after the second switch M2 is turned off and before the first switch M1 is turned on. A first node Lx is coupled to the voltage output terminal Vo.

[0046] It should be noted that the high-pass filter 20 is used to raise the voltage provided by the second voltage input terminal VDRIVE and provide it to the second input terminal g of the first driver stage circuit 10 after the second switch M2 is turned off and before the first switch M1 is turned on, so as to turn on the first switch M1.

[0047] It is understood that in some embodiments, Figure 4As shown, the ground terminal j of the logic processing circuit 30 is coupled with the first reference ground GND, the third input terminal k of the logic processing circuit 30 is coupled with the second voltage input terminal VDRIVE, and the third input terminal of the first driving stage circuit 10 is coupled with the second voltage input terminal VDRIVE.

[0048] It should be understood that in the switching circuit 01, due to packaging, PCB (printed circuit board) trace or via design, etc., a parasitic inductor between the power supply and the switch will be generated, for example, a parasitic inductor in series between the first voltage input terminal PVDD and the second switch M2. Figure 4 The parasitic inductor is represented by L' in the middle.) The parasitic inductor L' is generally in the order of nH, and in general, the parasitic inductor L' is harmful and cannot be eliminated. It should be noted that the current continuity of the inductor itself determines that in the interval when the second switch M2 is off and the first switch M1 is on, the parasitic inductor L' continues to flow, and the energy on the parasitic inductor L' will suddenly raise the voltage of the first voltage input terminal PVDD, at which time the second switch M2 will bear additional electrical stress.

[0049] Here, the first switch M1 and the second switch M2 are power tubes arranged in the power path. The type of power tube can be an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (also known as a metal oxide semiconductor field effect transistor) (MOSFET), or a PN junction field effect transistor (PNJFET).

[0050] On this basis, the first switch M1 and the second switch M2 can both be N-type tubes; they can both be P-type tubes; of course, one can be a P-type tube and the other can be an N-type tube, for example, the first switch M1 is an N-type tube and the second switch M2 is a P-type tube, and for example, the first switch M1 is a P-type tube and the second switch M2 is an N-type tube. Hereinafter, the specification and the accompanying drawings will be described with the first switch M1 and the second switch M2 as N-type tubes.

[0051] In addition, the second switch M2 can be referred to as an upper tube, and the first switch M1 can be referred to as a lower tube.

[0052] In the process of the first switch M1 and the second switch M2 being alternately turned on and turned off, in order to avoid the first switch M1 and the second switch M2 being turned on at the same time, causing the first voltage input terminal PVDD and the first reference ground GND being directly turned on, and further causing the power supply coupled with the first voltage input terminal PVDD to be burned out, thus in the process of the first switch M1 and the second switch M2 being alternately turned on and turned off, there is a time period in which the first switch M1 and the second switch M2 are turned off at the same time, i.e. the dead time.

[0053] The embodiment of the present application provides a kind of switch circuit 01, the switch circuit 01 includes first switch M1, first drive stage circuit 10, second switch M2, high pass filter 20, logic processing circuit 30, first voltage input terminal PVDD, second voltage input terminal VDRIVE, voltage output terminal Vo, first switch signal input terminal PWML and second switch signal input terminal PWMH.In the working process of the switch circuit 01, first switch M1 and second switch M2 are alternately turned on and turned off, by controlling the proportion of the time of first switch M1 and second switch M2 being turned on and turned off, so that the voltage provided by the first voltage input terminal PVDD can be converted into the voltage required from voltage output terminal Vo output.

[0054] On this basis, in the process of alternating on and off of the first switch M1 and the second switch M2, at the moment when the second switch M2 is off, before the first switch M1 is on, the energy of the parasitic inductance L' generated between the first voltage input terminal PVDD and the second switch M2 raises the voltage of the first voltage input terminal PVDD, at the same time, due to the fact that the switching circuit 01 includes the high-pass filter 20, the high-pass filter 20 is coupled with the first voltage input terminal PVDD, thus the feedforward effect of the high-pass filter 20 makes the high-pass filter 20 provide the voltage raised from the second voltage input terminal VDRIVE to the second input terminal g of the first drive stage circuit 10, in this way, the actual working voltage of the first drive stage circuit 10 in the dead time is higher than the voltage provided by the second voltage input terminal VDRIVE in the non-dead time, thus the first drive stage circuit 10 drives the first switch M1 to be on in advance under the action of the feedforward voltage, i.e. the actual working voltage, compared with the prior art, in the dead time, only in the non-dead time, the voltage received by the first switch signal input terminal PWML can control the first drive stage circuit 10 to receive the voltage provided by the second voltage input terminal VDRIVE to drive the first switch M1 to be on, while in the embodiment of the present application, in the dead time, the first switch M1 is driven to be on in advance by the feedforward effect of the high-pass filter 20, thus the dead time is effectively reduced, the dead time loss is reduced, and further the loss of the switching circuit 01 is reduced, and the efficiency of the switching circuit 01 is improved. In addition, before the second switch M2 is off and the first switch M1 is on, due to the fact that the logic processing circuit 30 can cut off the coupling between the ground terminal f of the first drive stage circuit 10 and the first reference ground GND, thus the voltage raised from the second voltage input terminal VDRIVE by the high-pass filter 20 is prevented from being pulled down and released by the first reference ground GND.

[0055] Based on this, the switching circuit 01 provided by the embodiment of the present application can be applied to the high-frequency switching circuit 01, and under the premise of not changing the size of the drive stage circuit, the overshoot voltage generated by the parasitic inductance L' after the second switch M2 is off is used to enhance the driving ability of the first drive stage circuit 10 to the first switch M1 in the dead time, reduce the dead time, and reduce the loss of the switching circuit 01.

[0056] It should be noted that the voltage rise (which can also be referred to as overshoot) of the first voltage input terminal PVDD is the result of the second switch M2 being off, thus the feedforward of the high-pass filter 20 can ensure that it is introduced after the second switch M2 is off, and the first drive stage circuit 10 of the first switch M1 introduces the energy before the first switch M1 is turned on, thus in any extreme case, there is no risk of punch-through caused by the first switch M1 and the second switch M2 being on at the same time, i.e. the risk of power burnout.

[0057] In some embodiments, as Figure 5As shown, the high-pass filter 20 includes a first capacitor C1 and a first resistor R1. The first capacitor C1 is coupled between the first voltage input terminal PVDD and the second input terminal g of the first driving stage circuit 10. The first resistor R1 is coupled between the second voltage input terminal VDRIVE and the second input terminal g of the first driving stage circuit 10.

[0058] With reference to Figure 5 At the moment when the second switch M2 is turned off, before the first switch M1 is turned on, the energy of the parasitic inductance L' raises the voltage of the first voltage input terminal PVDD. At this time, the voltage at the point m is raised and is greater than the voltage of the first voltage input terminal PVDD. At the same time, since the high-pass filter 20 includes the first capacitor C1, the voltage at the point n is raised by the feedforward effect of the first capacitor C1 in the high-pass filter 20 and is provided to the first driving stage circuit 10. In this way, the actual working voltage of the first driving stage circuit 10 is raised and is higher than the voltage provided by the second voltage input terminal VDRIVE controlled by the previous stage. Therefore, the first driving stage circuit 10 is driven to turn on the first switch M1 in advance under the action of the feedforward voltage.

[0059] In some embodiments, as Figure 5 As shown, the switch circuit 01 further includes an inductance L and a third capacitor C3. The inductance L is coupled between the first node Lx and the voltage output terminal Vo. The third capacitor C3 is coupled between the voltage output terminal Vo and the first reference ground GND. One end of the third capacitor C3 is coupled to the voltage output terminal Vo, and the other end is coupled to the first reference ground GND.

[0060] Here, the inductance L is coupled between the first node Lx and the voltage output terminal Vo. The inductance L can function as a freewheeling diode, so that the voltage output terminal Vo can stably output a voltage and avoid changes in the high and low voltage output by the voltage output terminal Vo. In addition, the third capacitor C3 is coupled between the voltage output terminal Vo and the first reference ground GND. The third capacitor C3 can function as a voltage stabilizer and can reduce the ripple of changes in the high and low voltage output by the voltage output terminal Vo.

[0061] In some embodiments, as Figure 6As shown, the first driver stage circuit 10 includes a third switch M3, a fourth switch M4, a fifth switch M5, a sixth switch M6, a seventh switch M7 and an eighth switch M8; the third switch M3 and the fourth switch M4 are coupled to the second node p (i.e., the output terminal p of the first driver stage circuit 10); the control terminal LG of the first switch M1 is coupled to the second node p; the third switch M3 is coupled between the output terminal n of the high-pass filter 20 and the second node p, the fourth switch M4 is coupled between the second node p and the first reference ground GND; the fifth switch M5 is coupled to the second voltage input terminal VD RIVE and the control terminal of the third switch M3; the sixth switch M6 is coupled between the control terminal of the third switch M3 and the first reference ground GND; the control terminal of the fifth switch M5 and the control terminal of the sixth switch M6 are coupled to the first switch signal input terminal PWML; the seventh switch M7 is coupled between the second voltage input terminal VDRIVE and the control terminal of the fourth switch M4; the eighth switch M8 is coupled between the control terminal of the fourth switch M4 and the first reference ground GND; the control terminal of the seventh switch M7 and the control terminal of the eighth switch M8 are coupled to the output terminal e of the logic processing circuit 30.

[0062] like Figure 6 As shown, when the high-pass filter 20 includes a first capacitor C1 and a first resistor R1, the first capacitor C1 is coupled between the first voltage input terminal PVDD and the third switch M3; the first resistor R1 is coupled between the second voltage input terminal VDRIVE and the third switch M3.

[0063] It should be noted that the third switch M3 and the fourth switch M4 are used to control the voltage of the control terminal LG of the first switch M1. The fifth switch M5 and the sixth switch M6 are used to control the voltage of the control terminal of the third switch M3. The seventh switch M7 and the eighth switch M8 are used to control the voltage of the control terminal of the fourth switch M4.

[0064] Here, the third switch M3, the fourth switch M4, the fifth switch M5, the sixth switch M6, the seventh switch M7, and the eighth switch M8 are power transistors, which may be, for example, insulated gate bipolar transistors, metal-oxide semiconductor field-effect transistors, or PN junction field-effect transistors.

[0065] In addition, the third switch M3 can be a P-type transistor and the fourth switch M4 can be an N-type transistor, or the third switch M3 can be an N-type transistor and the fourth switch M4 can be a P-type transistor. Since the third switch M3 is coupled between the output end n of the high-pass filter 20 and the second node p, and the first input end m of the high-pass filter 20 is coupled to the first voltage input end PVDD and the second input end o of the high-pass filter 20 is coupled to the second voltage input end VDRIVE, the third switch M3 is a pull-up transistor (Mpush) in the first driving stage circuit 10. Since the fourth switch M4 is coupled between the second node p and the first reference ground GND, the fourth switch M4 is a pull-down transistor (Mpull) in the first driving stage circuit 10.

[0066] In addition, the fifth switch M5 coupled to the control end of the third switch M3 and the sixth switch M6 can be a P-type transistor and an N-type transistor, respectively, or the fifth switch M5 can be an N-type transistor and the sixth switch M6 can be a P-type transistor. The seventh switch M7 coupled to the control end of the fourth switch M4 and the eighth switch M8 can be a P-type transistor and an N-type transistor, respectively, or the seventh switch M7 can be an N-type transistor and the eighth switch M8 can be a P-type transistor.

[0067] The following will be described with reference to the specific connection relationship of each switch in the switch circuit 01. Figure 6 Figure 6 The drain of the first switch M1 is coupled to the first node Lx, the source is coupled to the first reference ground GND, and the gate (i.e., the control end) is coupled to the second node p. The drain of the second switch M2 is coupled to the first voltage end PVDD, the source is coupled to the first node Lx, and the gate is coupled to the second switch signal input end PWMH. The source of the third switch M3 is coupled to the first capacitor C1, and the drain is coupled to the second node p. The drain of the fourth switch M4 is coupled to the second node p, and the source is coupled to the first reference ground GND. The source of the fifth switch M5 is coupled to the second voltage input end VDRIVE, the drain is coupled to the gate of the third switch M3, and the gate is coupled to the first switch signal input end PWML. The drain of the sixth switch M6 is coupled to the gate of the third switch M3, the source is coupled to the first reference ground GND, and the gate is coupled to the first switch signal input end PWML. The source of the seventh switch M7 is coupled to the second voltage input end VDRIVE, the drain is coupled to the gate of the fourth switch M4, and the gate is coupled to the output end e of the logic processing circuit 30. The drain of the eighth switch M8 is coupled to the gate of the fourth switch M4, the source is coupled to the first reference ground GND, and the gate is coupled to the output end e of the logic processing circuit 30.

[0068] ​Based on the above, it should be understood that when the type of the above-mentioned switch changes (for example, from a P-type transistor to an N-type transistor, or from an N-type transistor to a P-type transistor), the connection relationship between the source and drain of the switch changes accordingly. For example, when the second switch M2 is a P-type transistor, the source of the second switch M2 is coupled to the first voltage terminal PVDD, and the drain is coupled to the first node Lx. For other switches provided in the embodiments of the present application, when the type changes, the connection relationship between the source and drain of each switch can refer to the second switch M2, and will not be repeated here.

[0069] For the logic processing circuit 30 in the switch circuit 01 , two specific implementations are provided as examples below.

[0070] The first implementation method: Figure 7a As shown, the logic processing circuit 30 includes a flip-flop (also known as a D flip-flop) 301 and an OR gate 302; the second switching signal input terminal PWMH is coupled to the clock terminal CLK of the flip-flop 301 (the clock terminal CLK is the second input terminal i of the logic processing circuit 30); the reset terminal RESET of the flip-flop 301 is coupled to the first switching signal input terminal PWML; the flip-flop 301 also includes an input terminal D for receiving a fixed high level (which can be represented by "1") or a fixed low level (which can be represented by "0"); the output terminal of the flip-flop 301 is coupled to the first input terminal of the OR gate 302, the second input terminal of the OR gate 302 (the second input terminal of the OR gate 302 is the first input terminal h of the logic processing circuit 30) is coupled to the first switching signal input terminal PWML, and the output terminal of the OR gate 302 (the output terminal of the OR gate 302 is the output terminal e of the logic processing circuit 30) is coupled to the first input terminal d of the first driver stage circuit 10.

[0071] When the first driving stage circuit 10 includes a third switch M3 , a fourth switch M4 , a fifth switch M5 , a sixth switch M6 , a seventh switch M7 and an eighth switch M8 , the output terminal of the OR gate 302 is coupled to the control terminals of the seventh switch M7 and the eighth switch M8 .

[0072] Attachment Figure 7aFor example, when the input end D of the flip-flop 301 receives a high level (represented by "1"), the output end of the flip-flop 301 will be triggered according to the rising edge of the signal provided by the second switch signal input end PWMH received by the clock end CLK, i.e., when the signal provided by the second switch signal input end PWMH changes from a low level to a high level, the signal EN-FF output by the output end of the flip-flop 301 is a high level signal; or, the output end of the flip-flop 301 will be triggered according to the falling edge of the signal provided by the second switch signal input end PWMH received by the clock end CLK, i.e., when the signal provided by the second switch signal input end PWMH changes from a high level to a low level, the signal EN-FF output by the output end of the flip-flop 301 is a high level signal.

[0073] In some embodiments, as shown in FIG. 3, the logic processing circuit 30 further includes a fourth inverter 303, and the second switch signal input end PWMH is coupled to the clock end CLK of the flip-flop 301 through the fourth inverter 303. Here, the input end of the fourth inverter 303 (the input end of the fourth inverter 303 is the second input end i of the logic processing circuit 30) is coupled to the second switch signal input end PWMH, and the output end of the fourth inverter 303 is coupled to the clock end CLK. Figure 7b

[0074] In the case that the signal provided by the second switch signal input end PWMH changes from a high level to a low level, and the output end of the flip-flop 301 is triggered according to the rising edge of the clock end CLK, since the logic processing circuit 30 includes the fourth inverter 303, the fourth inverter 303 can invert the signal provided by the second switch signal input end PWMH, so that when the signal provided by the second switch signal input end PWMH changes from a high level to a low level, the output end of the flip-flop 301 will be triggered according to the rising edge of the clock end CLK, so that the signal EN-FF output by the output end of the flip-flop 301 is a high level signal. Or, in the case that the signal provided by the second switch signal input end PWMH changes from a low level to a high level, and the output end of the flip-flop 301 is triggered according to the falling edge of the clock end CLK, since the logic processing circuit 30 includes the fourth inverter 303, the fourth inverter 303 can invert the signal provided by the second switch signal input end PWMH, so that when the signal provided by the second switch signal input end PWMH changes from a low level to a high level, the output end of the flip-flop 301 will be triggered according to the falling edge of the clock end CLK, so that the signal EN-FF output by the output end of the flip-flop 301 is a high level signal.

[0075] ​On this basis, since the reset terminal RESET of the trigger 301 is coupled to the first switching signal input terminal PWML, when the signal provided by the first switching signal input terminal PWML changes from a low level to a high level, or from a high level to a low level, the signal EN-FF outputted from the output terminal of the trigger 301 returns to a low level signal.

[0076] The following combination Figure 8 The timing diagram shown is for Figure 7b The working process of the switching circuit 01 shown is introduced. Figure 7b The switch circuit 01 shown takes the first switch M1 and the second switch M2 as N-type transistors, the third switch M3 as a P-type transistor, the fourth switch M4 as an N-type transistor, the fifth switch M5 as a P-type transistor, the sixth switch M6 as an N-type transistor, the seventh switch M7 as a P-type transistor, and the eighth switch M8 as an N-type transistor as an example. Figure 8 The timing diagram shown provides a waveform diagram of the signal received by the second switch signal input terminal PWMH; a waveform diagram of the signal received by the first switch signal input terminal PWML; a waveform diagram of the signal received by the control terminal HG of the second switch M2; a waveform diagram of the signal EN-FF output by the output terminal EN-FF of the trigger 301; a waveform diagram of the signal received by the first node Lx; a waveform diagram of the signal received by the first voltage terminal PVDD; a waveform diagram of the signal received by the second voltage terminal VDRIVE; and a waveform diagram of the signal received by the control terminal LG of the first switch M1. Figure 8 The dotted line portion in the waveform diagram of the signal received by the first node Lx, the dotted line portion in the waveform diagram of the signal received by the second voltage terminal VDRIVE, and the dotted line portion in the waveform diagram of the signal received by the control terminal LG of the first switch M1 all represent waveform diagrams of corresponding signals in the prior art.

[0077] refer to Figure 7b and Figure 8 , the signal received at the second switch signal input terminal PWMH changes from a high level signal VH to a low level signal VL ( Figure 8 When the second switch M2 is turned off, the parasitic inductance L' ( Figure 7bThe parasitic inductance L' continues to flow, the voltage of the first voltage terminal PVDD surges (also referred to as lifting), and thus the voltage of the point m is lifted. At this time, the first capacitor (also referred to as a feedforward capacitor) C1 in the high-pass filter 20 synchronously pulls up the voltage of the point n, and the voltage VDRIVE' of the point n is greater than the voltage VDRIVE provided by the second voltage terminal VDRIVE. At the same time, the signal received by the first switch signal input terminal PWML is a low-level signal VL. Since the fifth switch M5 is a P-type tube and the sixth switch M6 is an N-type tube, the fifth switch M5 is turned on, and the sixth switch M6 is turned off. The voltage VDRIVE provided by the second voltage terminal VDRIVE is provided to the control terminal of the third switch M3 through the fifth switch M5. Since the third switch M3 is a P-type tube, and the voltage of the source (i.e., the s terminal) of the third switch M3 (i.e., the voltage VDRIVE' of the point n) is greater than the voltage of the g terminal (i.e., the control terminal or the gate), the third switch M3 is momentarily turned on. At this time, the voltage VDRIVE' of the point n that has been lifted is provided to the second node p through the third switch M3. The second node p is coupled to the control terminal LG of the first switch M1, and the first switch M1 is an N-type tube. Thus, the first switch M1 is turned on in advance. The shaded part in the waveform diagram of the signal received by the first node Lx represents the power consumption that can be reduced by the switch circuit 01 provided in the embodiment of the present application relative to the switch circuit 01 provided in the prior art. Based on the working process of the switch circuit 01, it can be seen that the first switch M1 is turned on in advance due to the fact that the second switch M2 is turned off, the voltage of the first voltage terminal PVDD surges, and the voltage of the point n is lifted due to the feedforward effect of the first capacitor C1 in the high-pass filter 20. Thus, although the first switch M1 is turned on in advance, the first switch M1 and the second switch M2 do not have the risk of being turned on at the same time under any circumstances.

[0078] On this basis, after the signal received by the second switch signal input end PWMH changes from a high-level signal VH to a low-level signal VL, that is, after the second switch M2 is turned off, before the signal received by the first switch signal input end PWML changes from a low-level signal VL to a high-level signal VH, the output end of the flip-flop 301 in the logic processing circuit 30 is triggered according to the falling edge of the signal provided by the second switch signal input end PWMH received by the clock end CLK, and the signal EN-FF output by the output end of the flip-flop 301 is a high-level dead zone signal. During this time, one input end of the OR gate 302 in the logic processing circuit 30 receives the high-level signal VH output by the output end of the flip-flop 301, and the other input end receives the low-level signal VL provided by the first switch signal input end PWML, so that the output end of the OR gate 302 outputs a high-level signal. Since the control ends of the seventh switch M7 and the eighth switch M8 are coupled with the output end of the OR gate 302, the seventh switch M7 is a P-type tube, and the eighth switch M8 is an N-type tube, at this time, the seventh switch M7 is turned off, the eighth switch M8 is turned on, and the voltage of the first reference ground GND is provided to the control end of the fourth switch M4 through the eighth switch M8, thereby controlling the fourth switch M4 to be turned off. In this way, the voltage of the first reference ground GND is prevented from being provided to the second node p through the fourth switch M4, at this time, the voltage of the second node p changes from a low-resistance pull-down to a high resistance, ensuring that the upper rush energy passing through the third switch M3 will not be discharged to the ground after the third switch M3 is turned on, and the voltage of the second node p remains high, thereby allowing the first switch M1 to be turned on in advance and reducing the actual dead zone time.

[0079] After the signal received by the first switch signal input end PWML is pulled high, that is, changes to a high-level signal VH, the signal EN-FF output by the output end of the flip-flop 301 returns to a low-level signal VL. Since one input end of the OR gate 302 receives the low-level signal output by the output end of the flip-flop 301, and the other input end receives the high-level signal VH provided by the first switch signal input end PWML, the output end of the OR gate 302 outputs a high-level signal. At this time, the seventh switch M7 is turned off, the eighth switch M8 is turned on, and the voltage of the first reference ground GND is provided to the control end of the fourth switch M4 through the eighth switch M8, thereby controlling the fourth switch M4 to be turned off. At the same time, since the high-level signal VH provided by the first switch signal input end PWML controls the sixth switch M6 to be turned on and the fifth switch M5 to be turned off, the voltage of the first reference ground GND is provided to the control end of the third switch M3 through the sixth switch M6, thereby controlling the third switch M3 to be turned on. The voltage provided by the second voltage input end VDRIVE is provided to the second node p through the third switch M3, thereby controlling the first switch M1 to be turned on. As can be seen, after the signal received by the first switch signal input end PWML is pulled high, the control end LG of the first switch M1 continues to be controlled by the signal received by the first switch signal input end PWML.

[0080] The second implementation manner is shown in Figure 9 The logic processing circuit 30 includes a delay circuit 304, a first AND gate 305, a second AND gate 306, a first inverter 307, a second inverter 308, and an OR gate 302.

[0081] The second switch signal input end PWMH is coupled with the first input end of the first AND gate 305 through the delay circuit 304. Here, the input end of the delay circuit 304 (the input end of the delay circuit 304 is the second input end i of the logic processing circuit 30) is coupled with the second switch signal input end PWMH, and the output end PWMH-D of the delay circuit 304 is coupled with the first input end of the first AND gate 305. The second switch signal input end PWMH is also coupled with the second input end of the first AND gate 305 through the first inverter 307. Here, the input end of the first inverter 307 is coupled with the second switch signal input end PWMH, and the output end of the first inverter 307 is coupled with the second input end of the first AND gate 305. The output end PPH of the first AND gate 305 is coupled with the first input end of the second AND gate 306, and the first switch signal input end PWML is coupled with the second input end of the second AND gate 306 through the second inverter 308. Here, the input end of the second inverter 308 is coupled with the first switch signal input end PWML, the output end of the second inverter 308 is coupled with the second input end of the second AND gate 306, and the output end of the second AND gate 306 is coupled with the first input end of the OR gate 302. The second input end of the OR gate 302 (the second input end of the OR gate 302 is the first input end h of the logic processing circuit 30) is coupled with the first switch signal input end PWML, and the output end of the OR gate 302 (the output end of the OR gate 302 is the output end e of the logic processing circuit 30) is coupled with the first input end d of the first drive stage circuit 10.

[0082] In some embodiments, the delay circuit 304 described above includes n third inverters connected in series. Here, n≥2, n is a positive even number. The n third inverters connected in series can output the signal received by the second switch signal input end PWMH after a certain time delay.

[0083] In some other embodiments, the delay circuit 304 described above includes a second capacitor C2 and a second resistor R2 connected in series. Here, the second capacitor C2 and the second resistor R2 connected in series can output the signal received by the second switch signal input end PWMH after a certain time delay.

[0084] The working process of the switch circuit 01 shown in Figure 10 is introduced below in combination with the timing diagram shown in Figure 9 . Figure 9The shown switch circuit 01 takes the first switch M1 and the second switch M2 as N-type tubes, the third switch M3 as a P-type tube, the fourth switch M4 as an N-type tube, the fifth switch M5 as a P-type tube, the sixth switch M6 as an N-type tube, the seventh switch M7 as a P-type tube, and the eighth switch M8 as an N-type tube as an example. Figure 10 The shown timing diagram respectively provides a waveform diagram of the signal provided by the second switch signal input end PWMH; a waveform diagram of the signal provided by the output end PWMH-D of the delay circuit 304; a waveform diagram of the signal provided by the output end PPH of the first AND gate 305; a waveform diagram of the signal received by the first switch signal input end PWML; and a waveform diagram of the signal EN-FF output by the output end of the second AND gate 306.

[0085] Reference Figure 9 and Figure 10, after the signal received by the second switch signal input terminal PWMH changes from the high level signal VHand the low level signal VL, that is, after the second switch M2 is turned off, before the signal received by the first switch signal input terminal PWML changes from the low level signal VL to the high level signal VH, the voltage VDRIVE' that has been raised at the n point is provided to the second node p through the third switch M3, which is similar to the first implementation manner, and details are not described herein. At the same time, after the signal received by the second switch signal input terminal PWMH changes from the high level signal VHand the low level signal VL, that is, after the second switch M2 is turned off, before the signal received by the first switch signal input terminal PWML changes from the low level signal VL to the high level signal VH, the signal received by the second switch signal input terminal PWMH is input to the output terminal PWMH-D of the delay circuit 304 after passing through the delay circuit 304, and the output terminal PWMH-D of the delay circuit 304 outputs the high level signal VH. At the same time, the signal received by the second switch signal input terminal PWMH is output as the high level signal VH after passing through the first inverter 307; the first AND gate 305 receives the high level signal VH output by the output terminal PWMH-D of the delay circuit 304 at one input terminal and receives the high level signal VH output by the first inverter 307 at the other input terminal, and the output terminal PPH of the first AND gate 305 outputs the high level signal VH; the second inverter 308 receives the low level signal VL received by the first switch signal input terminal PWML at the input terminal, and the output terminal of the second inverter 308 outputs the high level signal VH; the second AND gate 306 receives the high level signal VH output by the output terminal PPH of the first AND gate 305 at one input terminal and receives the high level signal VH output by the output terminal of the second inverter 308 at the other input terminal, and the signal EN-FF output by the output terminal of the second AND gate 306 is the high level signal VH. At this time, the one input terminal of the OR gate 302 receives the high level signal VH output by the output terminal of the second AND gate 306, and the other input terminal of the OR gate 302 receives the low level signal VL provided by the first switch signal input terminal PWML, so that the output terminal of the OR gate 302 outputs the high level signal. Since the control terminals of the seventh switch M7 and the eighth switch M8 are coupled with the output terminal of the OR gate 302, the seventh switch M7 is a P-type tube, and the eighth switch M8 is an N-type tube, at this time, the seventh switch M7 is turned off, the eighth switch M8 is turned on, and the voltage of the first reference ground GND is provided to the control terminal of the fourth switch M4 through the eighth switch M8, so as to control the fourth switch M4 to be turned off. In this way, the voltage of the first reference ground GND is prevented from being provided to the second node p through the fourth switch M4, at this time, the voltage of the second node p changes from the low resistance pull-down to the high resistance, so as to ensure that the uprush energy passing through the third switch M3 cannot be discharged to the ground through the fourth switch M4, the voltage of the second node p is kept raised, so as to make the first switch M1 turned on in advance, and the actual dead time is reduced.

[0086] In addition, after the signal received by the first switch signal input terminal PWML is pulled high, i.e., becomes a high-level signal VH, the control terminal LG of the first switch M1 continues to be controlled by the signal received by the first switch signal input terminal PWML. For details, reference can be made to the above embodiment, which will not be described here again.

[0087] It should be noted that the logic processing circuit 30 includes but is not limited to the above first implementation and the second implementation.

[0088] In some embodiments, as shown in Figure 5 , Figure 6 , Figure 7a , Figure 7b and Figure 9 , the switch circuit 01 can further include a second drive stage circuit 40. The control terminal HG of the second switch M2 is coupled to the second switch signal input terminal PWMH through the second drive stage circuit 40.

[0089] Here, the first input terminal q of the second drive stage circuit 40 is coupled to the second switch signal input terminal PWMH, and the output terminal s of the second drive stage circuit 40 is coupled to the control terminal HG of the second switch M2. On this basis, it should be understood that in some embodiments, the switch circuit 01 further includes a third voltage input terminal VDRIVE-HG and a second reference ground GND-HG. The second input terminal t of the second drive stage circuit 40 is coupled to the third voltage input terminal VDRIVE-HG, and the ground terminal u of the second drive stage circuit 40 is coupled to the second reference ground GND-HG.

[0090] Since the control terminal HG of the second switch M2 is coupled to the second drive stage circuit 40, the driving capability of the control terminal HG of the second switch M2 can be improved, and the time for the second switch M2 to turn on or off can be reduced.

[0091] In addition, the structure of the second drive stage circuit 40 and the structure of the first drive stage circuit 10 can be the same or different.

[0092] In some examples, as shown in Figure 11As shown, the switch circuit 01 further comprises a third voltage input terminal VDRIVE-HG and a second reference ground GND-HG, and the second driving stage circuit 40 further comprises a ninth switch M9, a tenth switch M10, an eleventh switch M11, a twelfth switch M12, a thirteenth switch M13 and a fourteenth switch M14. The ninth switch M9 is coupled between the third voltage input terminal VDRIVE-HG and the control terminal HG of the second switch M2, and the tenth switch M10 is coupled between the control terminal HG of the second switch M2 and the second reference ground GND-HG. The eleventh switch M11 is coupled between the third voltage input terminal VDRIVE-HG and the control terminal of the ninth switch M9, and the twelfth switch M12 is coupled between the control terminal of the ninth switch M9 and the second reference ground GND-HG. The control terminal of the eleventh switch M11 and the control terminal of the twelfth switch M12 are both coupled to the second switch signal input terminal PWMH. The thirteenth switch M13 is coupled between the third voltage input terminal VDRIVE-HG and the control terminal of the tenth switch M10, and the fourteenth switch M14 is coupled between the control terminal of the tenth switch M10 and the second reference ground GND-HG. The control terminal of the thirteenth switch M13 and the control terminal of the fourteenth switch M14 are both coupled to the second switch signal input terminal PWMH.

[0093] Here, the ninth switch M9 is a pull-up tube in the second driving stage circuit 40, the tenth switch M10 is a pull-down tube in the second driving stage circuit 40, and the ninth switch M9 and the tenth switch M10 are used to control the voltage of the control terminal HG of the second switch M2. The eleventh switch M11 and the twelfth switch M12 are used to control the voltage of the control terminal of the ninth switch M9, and the thirteenth switch M13 and the fourteenth switch M14 are used to control the voltage of the control terminal of the tenth switch M10.

[0094] It should be noted that the ninth switch M9, the tenth switch M10, the eleventh switch M11, the twelfth switch M12, the thirteenth switch M13 and the fourteenth switch M14 are power tubes. The type of power tube may be, for example, an insulated gate bipolar transistor, a metal-oxide semiconductor field effect transistor or a PN junction field effect transistor.

[0095] On this basis, the ninth switch M9, the tenth switch M10, the eleventh switch M11, the twelfth switch M12, the thirteenth switch M13 and the fourteenth switch M14 can be N-type tubes or P-type tubes.

[0096] In addition, the connection relationship of the source and drain of the ninth switch M9, the tenth switch M10, the eleventh switch M11, the twelfth switch M12, the thirteenth switch M13 and the fourteenth switch M14 in the second driving stage circuit 40 can refer to the above description of the connection relationship of the source and drain of the first switch M1, the second switch M2, the third switch M3, the fourth switch M4, the fifth switch M5 and the sixth switch M6 in the first driving stage circuit 30. Figure 6The connection relationship of the source and the drain of each switch is shown in the figure and will not be described here.

[0097] Based on the structure of the second driving stage circuit 40, the working process of the second driving stage circuit 40 is described below by taking the ninth switch M9 as a P-type tube, the tenth switch M10 as an N-type tube, the eleventh switch M11 as a P-type tube, the twelfth switch M12 as an N-type tube, the thirteenth switch M13 as a P-type tube, and the fourteenth switch M14 as an N-type tube as an example.

[0098] When the voltage received by the second switch signal input end PWMH is a high-level signal VH, the eleventh switch M11 and the thirteenth switch M13 are both turned off, the twelfth switch M12 and the fourteenth switch M14 are both turned on, the voltage provided by the second reference ground GND-HG is input to the control end of the ninth switch M9 through the twelfth switch M12, thereby controlling the ninth switch M9 to be turned on, and at the same time, the voltage provided by the second reference ground GND-HG is input to the control end of the tenth switch M10 through the fourteenth switch M14, thereby controlling the tenth switch M10 to be turned off. Since the ninth switch M9 is turned on and the tenth switch M10 is turned off, the voltage provided by the third voltage input end VDRIVE-HG is input to the control end HG of the second switch M2 through the ninth switch M9, thereby controlling the second switch M2 to be turned on. Therefore, when the voltage provided by the second switch signal input end PWMH is a high-level signal VH, the second switch M2 is turned on.

[0099] When the voltage received by the second switch signal input end PWMH is a low-level signal VL, the eleventh switch M11 and the thirteenth switch M13 are both turned on, the twelfth switch M12 and the fourteenth switch M14 are both turned off, the voltage provided by the third voltage input end VDRIVE-HG is input to the control end of the ninth switch M9 through the eleventh switch M11, thereby controlling the ninth switch M9 to be turned off, and at the same time, the voltage provided by the third voltage input end VDRIVE-HG is input to the control end of the tenth switch M10 through the thirteenth switch M13, thereby controlling the tenth switch M10 to be turned on. Since the ninth switch M9 is turned off and the tenth switch M10 is turned on, the voltage provided by the second reference ground GND-HG is input to the control end HG of the second switch M2 through the tenth switch M10, thereby controlling the second switch M2 to be turned off. Therefore, when the voltage provided by the second switch signal input end PWMH is a low-level signal VL, the second switch M2 is turned off.

[0100] Based on the above, the voltage received by the second switch signal input end PWMH and the second driving stage circuit 40 can control the second switch M2 to be turned on or turned off.

[0101] The embodiment of the present application further provides a switching circuit 01, and the main structure of the switching circuit 01 is as shown in the figure. Figure 7aAs shown, the switch circuit 01 includes a first switch M1, a first driving stage circuit 10, a second switch M2, a high-pass filter 20, a logic processing circuit 30, a first voltage input terminal PVDD, a second voltage input terminal VDRIVE, a voltage output terminal Vo, a first switch signal input terminal PWML, a second switch signal input terminal PWMH, and a first reference ground GND. The first switch M1 is coupled between a first node Lx and the first reference ground GND; a control terminal LG of the first switch M1 is coupled with an output terminal p of the first driving stage circuit 10; a ground terminal f of the first driving stage circuit 10 is coupled with the first reference ground GND. The second switch M2 is coupled between the first voltage input terminal PVDD and the first node Lx; a control terminal HG of the second switch M2 is coupled with the second switch signal input terminal PWMH. A first input terminal m of the high-pass filter 20 is coupled with the first voltage input terminal PVDD, a second input terminal o of the high-pass filter 20 is coupled with the second voltage input terminal VDRIVE, and an output terminal n of the high-pass filter 20 is coupled with a second input terminal g of the first driving stage circuit 10. The logic processing circuit 30 includes a flip-flop 301 and an OR gate 302; the second switch signal input terminal PWMH is coupled with a clock terminal CLK of the flip-flop 301; a reset terminal RESET of the flip-flop 301 is coupled with the first switch signal input terminal PWML; the flip-flop 301 further includes an input terminal D for receiving a fixed high level or a fixed low level; an output terminal of the flip-flop 301 is coupled with a first input terminal of the OR gate 302, a second input terminal of the OR gate 302 is coupled with the first switch signal input terminal PWML, and an output terminal of the OR gate 302 is coupled with a first input terminal d of the first driving stage circuit 10.

[0102] In some embodiments, as shown in FIG. 2, the logic processing circuit 30 further includes a fourth inverter 303, and the second switch signal input terminal PWMH is coupled with the clock terminal CLK of the flip-flop 301 through the fourth inverter 303. Figure 7b

[0103] In some embodiments, the switch circuit 01 described above can further include a second driving stage circuit 40; the control terminal HG of the second switch M2 is coupled with the second switch signal input terminal PWMH through the second driving stage circuit 40.

[0104] It should be noted that the specific structures of the first driving stage circuit 10, the high-pass filter 20, and the second driving stage circuit 40, other structures of the switch circuit, the types of various switches, etc. can refer to the above embodiments, which will not be described here again.

[0105] The embodiments of the present application also provide a switch circuit 01, the main structure of which is shown in FIG. 2. Figure 9 ​As shown, the switch circuit 01 includes a first switch M1, a first driving stage circuit 10, a second switch M2, a high-pass filter 20, a logic processing circuit 30, a first voltage input terminal PVDD, a second voltage input terminal VDRIVE, a voltage output terminal Vo, a first switch signal input terminal PWML, a second switch signal input terminal PWMH, and a first reference ground GND. The first switch M1 is coupled between a first node Lx and the first reference ground GND; a control terminal LG of the first switch M1 is coupled with an output terminal p of the first driving stage circuit 10; a ground terminal f of the first driving stage circuit 10 is coupled with the first reference ground GND. The second switch M2 is coupled between the first voltage input terminal PVDD and the first node Lx; a control terminal HG of the second switch M2 is coupled with the second switch signal input terminal PWMH. A first input terminal m of the high-pass filter 20 is coupled with the first voltage input terminal PVDD, a second input terminal o of the high-pass filter 20 is coupled with the second voltage input terminal VDRIVE, and an output terminal n of the high-pass filter 20 is coupled with a second input terminal g of the first driving stage circuit 10. The logic processing circuit 30 includes a delay circuit 304, a first AND gate 305, a second AND gate 306, a first inverter 307, a second inverter 308, and an OR gate 302. The second switch signal input terminal PWMH is coupled with a first input terminal of the first AND gate 305 through the delay circuit 304; the second switch signal input terminal PWMH is also coupled with a second input terminal of the first AND gate 305 through the first inverter 307; an output terminal PPH of the first AND gate 305 is coupled with a first input terminal of the second AND gate 306, the first switch signal input terminal PWML is coupled with a second input terminal of the second AND gate 306 through the second inverter 308, and an output terminal of the second AND gate 306 is coupled with a first input terminal of the OR gate 302; a second input terminal of the OR gate 302 is coupled with the first switch signal input terminal PWML, and an output terminal of the OR gate 302 is coupled with a first input terminal d of the first driving stage circuit 10.

[0106] In some embodiments, the switch circuit 01 can further include a second driving stage circuit 40; the control terminal HG of the second switch M2 is coupled with the second switch signal input terminal PWMH through the second driving stage circuit 40.

[0107] It should be noted that the specific structures of the first driving stage circuit 10, the high-pass filter 20, the second driving stage circuit 40, and the delay circuit 304, other structures of the switch circuit, types of the switches, etc. can refer to the above embodiments, which will not be described here.

[0108] The embodiments of the present application further provide a power supply chip, which includes the above-mentioned switch circuit 01. The power supply chip provided by the embodiments of the present application can be applied to any electronic device, such as a mobile phone, a tablet computer, a wearable device (such as a smart watch), etc.

[0109] It should be noted that the first drive stage circuit 10, the high-pass filter 20, the logic processing circuit 30, the third capacitor C3, and the second drive circuit 40 in the above-mentioned switching circuit 01 can be integrated on a power supply chip. In addition, the first switch M1, the second switch M2, and the inductor L can be integrated on the power supply chip or can be arranged outside the power supply chip.

[0110] In addition, the logic outputting the first switch signal PWML and the second switch signal PWMH can be integrated on the power supply chip or can be integrated on other chips.

[0111] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A switching circuit, characterized by, The application relates to a voltage output circuit, comprising: a first switch, a first driving stage circuit, a second switch, a high-pass filter, a logic processing circuit, a first voltage input end, a second voltage input end, a voltage output end, a first switch signal input end, a second switch signal input end and a first reference ground; the first switch is coupled between a first node and the first reference ground; a control end of the first switch is coupled with an output end of the first driving stage circuit; a first input end of the first driving stage circuit is coupled with an output end of the logic processing circuit, and a ground end of the first driving stage circuit is coupled with the first reference ground; the second switch is coupled between the first voltage input end and the first node; a control end of the second switch is coupled with the second switch signal input end; a first input end of the high-pass filter is coupled with the first voltage input end, a second input end of the high-pass filter is coupled with the second voltage input end, and an output end of the high-pass filter is coupled with a second input end of the first driving stage circuit; a first input end of the logic processing circuit is coupled with the first switch signal input end, and a second input end of the logic processing circuit is coupled with the second switch signal input end; the logic processing circuit is used for cutting off the coupling between the ground end of the first driving stage circuit and the first reference ground after the second switch is turned off and before the first switch is turned on; the first node is coupled with the voltage output end.

2. The switching circuit of claim 1, wherein the high-pass filter comprises a first capacitor and a first resistor; the first capacitor is coupled between the first voltage input end and the second input end of the first driving stage circuit; the first resistor is coupled between the second voltage input end and the second input end of the first driving stage circuit.

3. The switching circuit according to claim 1 or 2, characterized in that the logic processing circuit comprises a flip-flop and an OR gate; the second switch signal input end is coupled with a clock end of the flip-flop; a reset end of the flip-flop is coupled with the first switch signal input end; the flip-flop further comprises an input end for receiving a fixed high level or a fixed low level; an output end of the flip-flop is coupled with a first input end of the OR gate, a second input end of the OR gate is coupled with the first switch signal input end, and an output end of the OR gate is coupled with a first input end of the first driving stage circuit.

4. The switching circuit according to claim 1 or 2, characterized in that, the logic processing circuit comprises a delay circuit, a first AND gate, a second AND gate, a first inverter, a second inverter and an OR gate; the second switch signal input end is coupled with a first input end of the first AND gate through the delay circuit, and the second switch signal input end is further coupled with a second input end of the first AND gate through the first inverter; an output end of the first AND gate is coupled with a first input end of the second AND gate, the first switch signal input end is coupled with a second input end of the second AND gate through the second inverter, and an output end of the second AND gate is coupled with a first input end of the OR gate; a second input end of the OR gate is coupled with the first switch signal input end, and an output end of the OR gate is coupled with a first input end of the first driving stage circuit.

5. The switching circuit of claim 4, wherein The delay circuit comprises n third inverters connected in series, wherein n is an even positive integer greater than or equal to 2.

6. The switching circuit of claim 4, wherein The delay circuit comprises a second capacitor and a second resistor connected in series.

7. The switching circuit according to any one of claims 1 to 6, characterized in that The first driving stage circuit comprises a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch and an eighth switch. The third switch and the fourth switch are coupled to a second node; a control terminal of the first switch is coupled to the second node. The third switch is coupled between an output terminal of the high-pass filter and the second node, and the fourth switch is coupled between the second node and the first reference ground. The fifth switch is coupled between the second voltage input terminal and a control terminal of the third switch. The sixth switch is coupled between the control terminal of the third switch and the first reference ground; a control terminal of the fifth switch and a control terminal of the sixth switch are coupled to the first switch signal input terminal. The seventh switch is coupled between the second voltage input terminal and a control terminal of the fourth switch. The eighth switch is coupled between the control terminal of the fourth switch and the first reference ground; a control terminal of the seventh switch and a control terminal of the eighth switch are coupled to an output terminal of the logic processing circuit.

8. The switching circuit according to any one of claims 1 to 7, characterized in that The switch circuit further comprises a second driving stage circuit. A control terminal of the second switch is coupled to a second switch signal input terminal through the second driving stage circuit.

9. The switching circuit according to any of claims 1-8, characterized in that, The switch circuit further comprises an inductor and a third capacitor. The inductor is coupled between the first node and the voltage output terminal. The third capacitor is coupled between the voltage output terminal and the first reference ground.

10. The switching circuit of claim 1, wherein, The first switch and the second switch are insulated gate bipolar transistors, metal-oxide semiconductor field effect transistors or PN junction field effect transistors.

11. The switching circuit of claim 7, wherein, The third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch and the eighth switch are insulated gate bipolar transistors, metal-oxide semiconductor field effect transistors or PN junction field effect transistors.

12. A switching power supply, characterized by The switch circuit comprises a controller and a switch circuit as claimed in any one of claims 1-11. The first switch signal input terminal and the second switch signal input terminal are both coupled to the controller.

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