Current mirror arrangement

Abstract

The present disclosure relates to current mirror arrangements. An example current mirror arrangement comprises a current mirror circuit having an input transistor and an output transistor, wherein the base / gate terminal of the input transistor is coupled to its collector / drain terminal via a transistor matrix comprising a plurality of transistors. The transistors of the transistor matrix form two parallel feedback loops together with the input transistor, such that the input transistor is part of both loops. The first loop is a fast, low-gain loop, while the second loop is a slow, high-gain loop. At lower input frequencies, the high-gain loop can suitably bias and accurately produce a voltage on the base / gate terminal of the input transistor, while at higher input frequencies, the fast loop can significantly extend the linear operating frequency band. Thus, a current mirror arrangement can be implemented that is improved in terms of linearity and signal bandwidth.

Description

[0001] This application is a divisional application of the application with application number 202110107181.8, filed on January 27, 2021, and titled “Current Mirror Arrangement”. TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic devices, and more particularly, to a current mirror arrangement. BACKGROUND

[0003] Current mirror is one of the few components necessary for general circuit design. In particular, wideband linear current mirror is one of the main building blocks of open loop wideband linear amplifiers, which are widely used in communication, military, automotive, industrial, and other broad markets.

[0004] Designing a current mirror that mirrors an input current with constant current gain in a linear fashion over a wide operating bandwidth is not trivial, especially at increasing fundamental input signal frequencies. The linearity and signal bandwidth of a current mirror ultimately set an upper limit on the dynamic range of an amplifier or any other circuit using the current mirror at a given operating frequency. Traditionally, linearity comes at the expense of bandwidth and power. Therefore, having a current mirror with both high linearity and wide signal bandwidth would provide a clear competitive advantage in differentiating products in a given market. SUMMARY

[0005] According to one aspect of the present disclosure, a current mirror arrangement is provided, comprising: a current mirror circuit comprising an input transistor and an output transistor, the current mirror circuit configured to receive an input current and generate an output current based on the input current; and a plurality of other transistors, wherein: a first subset of the plurality of other transistors is coupled to form a first feedback path from a first terminal of the input transistor to a second terminal of the input transistor, and a second subset of the plurality of other transistors is coupled to form a second feedback path from the first terminal of the input transistor to the second terminal of the input transistor, the second feedback path being different from the first feedback path.

[0006] According to another aspect of the present disclosure, a current mirror arrangement is also provided, comprising: a plurality of transistors each having a first terminal, a second terminal, and a third terminal, the plurality of transistors comprising at least transistors Q1, Q2, Q3, and Q4, arranged such that: the first terminal of the transistor Q1 is coupled to the first terminal of the transistor Q2, the second terminal of the transistor Q1 is coupled to the third terminal of the transistor Q3, and the first terminal of the transistor Q1 is further coupled to the second terminal of the transistor Q3 and the third terminal of the transistor Q4, respectively.

[0007] According to another aspect of the disclosure, there is provided a current mirror arrangement comprising: a current mirror circuit comprising an input transistor Q1 and an output transistor Q2; and a transistor matrix comprising a plurality of transistors coupled between a first terminal of the input transistor Q1 and a second terminal of the input transistor Q1. BRIEF DESCRIPTION OF DRAWINGS

[0008] For a more complete understanding of the present disclosure, and the features and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like parts, in which:

[0009] Figure 1 A circuit diagram of an NPN implementation of a conventional current mirror with a current gain K is provided.

[0010] Figure 2 A circuit diagram of an NPN implementation of a current mirror of Figure 1 is provided, additionally showing relevant parasitic elements for high operating frequencies.

[0011] Figures 3 to 6 A circuit diagram of a current mirror arrangement with reduced input impedance according to various embodiments of the disclosure is provided;

[0012] Figure 7 A schematic diagram of a system implementing a current mirror arrangement with reduced input impedance according to some embodiments of the disclosure is provided. DETAILED DESCRIPTION

[0013] Review

[0014] The systems, methods, and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the overall desirable attributes of the systems, methods, and devices disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the description below.

[0015] In one aspect, various current mirror arrangements are disclosed. An example arrangement includes a current mirror circuit configured to receive an input signal (e.g., an input current signal) at an input and output a mirror signal (e.g., a mirror current signal) at an output. The current mirror circuit includes an input transistor Ql and an output transistor Q2, where the base / gate terminal of the input transistor Ql is coupled to its collector / drain terminal via a transistor matrix including multiple transistors. The transistors of the transistor matrix form two parallel feedback loops with the input transistor Ql, so the input transistor Ql is part of both loops. The first loop can be referred to as “low gain” and the second loop can be referred to as “high gain” to convey the fact that the gain of the first loop is lower than the gain of the second loop. In addition, the first loop can be referred to as “fast” and the second loop can be referred to as “slow” to convey the fact that when the frequency of the input signal is in a lower frequency range (thus: “slow”), the overall loop gain of the current mirror arrangement is determined by the second high gain loop, while for input signals of higher frequency (thus: “fast”), the overall loop gain of the current mirror arrangement is determined by the first loop of low gain. At relatively lower input frequencies, the high gain second loop can be suitably biased and accurately produce a voltage on the base / gate terminal of the input transistor Ql, while at higher input frequencies, the fast first loop can greatly expand the linear operating frequency band. Providing a transistor matrix that forms such a fast, low gain first loop and a slow, high gain second loop, each of which includes the input transistor Ql of the current mirror circuit, modifies the input of the current mirror circuit in a way that can effectively reduce its input impedance. Equivalently, it reduces the linear and nonlinear voltage swing on node Nl, thereby further suppressing the nonlinear current contribution of any parasitic capacitors present on that node. As a result, a current mirror arrangement with improved linearity and signal bandwidth can be achieved.

[0016] Because various embodiments of the current mirror arrangements described herein can advantageously allow for reducing the input impedance of the current mirror circuit (by including first and second feedback loops as described herein), such arrangements are referred to herein as “current mirror arrangements with reduced input impedance.”

[0017] The precise design of a current mirror arrangement with reduced input impedance can be implemented in many different ways, all of which are within the scope of the present disclosure. In one example of a design variation in accordance with various embodiments of the present disclosure, each transistor of the input impedance reduced current mirror arrangement can be selected individually (e.g., individually for each transistor of the current mirror circuit and for each transistor in the matrix of transistors) to use bipolar transistors (e.g., where the various transistors can be NPN and / or PNP transistors), field effect transistors (FETs), such as metal oxide semiconductor (MOS) technology transistors (e.g., where the various transistors can be N-type MOS (NMOS) and / or P-type MOS (PMOS) transistors), or a combination of one or more FETs and one or more bipolar transistors. In view of this, in the following description, a transistor is described with reference to first, second, and third terminals of the transistor. If the transistor is a bipolar transistor, the “first terminal” of the transistor is used to refer to the base terminal; if a MOS transistor, the term “first terminal” is used to refer to the gate terminal; if the transistor is a bipolar transistor, the term “second terminal” of the transistor is used to refer to the collector terminal; if the transistor is a MOS transistor, the term “second terminal” is used to refer to the drain terminal; if the transistor is a bipolar transistor, the term “third terminal” of the transistor is used to refer to the emitter terminal, while if the transistor is a MOS transistor, the term “third terminal” is used to refer to the source terminal. These terms remain the same regardless of whether the transistor of a given technology is an N-type transistor (e.g., an NPN transistor if the transistor is a bipolar transistor; an NMOS transistor if the transistor is a MOS transistor) or a P-type transistor (e.g., a PNP transistor if the transistor is a bipolar transistor; a PMOS transistor if the transistor is a MOS transistor).

[0018] In another example, in various embodiments, for each transistor of the current mirror arrangement having a reduced input impedance, a selection can be made, respectively, of which transistors are implemented as N-type transistors (e.g., NMOS transistors for transistors implemented as FETs, or NPN transistors for transistors implemented as bipolar transistors), and which transistors are implemented as P-type transistors (e.g., PMOS transistors for transistors implemented as FETs or PNP transistors for transistors implemented as bipolar transistors). In other examples, in various embodiments, a selection can be made of which type of transistor architecture to employ. For example, any transistors of the current mirror arrangement having a reduced input impedance implemented as FETs as described herein can be planar transistors or non-planar transistors, such as FinFETs, nanowire transistors, or nanoribbon transistors. Other possible design variations can include implementing the current mirror arrangement having a reduced input impedance as a single-ended input / output or differential input / output circuit, employing a cascode of two or more transistors in any portion of the device, and the like. A current mirror arrangement having a reduced input impedance is shown in Figures 3-6 However, in accordance with the description provided herein, any implementation of a current mirror arrangement having a reduced input impedance is within the scope of the present disclosure.

[0019] The ratio of the output signal provided at the output of the current mirror circuit to the input signal provided at the input of the current mirror circuit can be substantially equal to K. K is a current gain, which can be any positive value greater than 0, where the exact value of K can but need not be an integer. For embodiments of bipolar implementations, the value of K can be indicative of (e.g., equal to or based on) the ratio of the area of the emitter of the output transistor Q2 to the area of the emitter of the input transistor Ql. For embodiments of MOS implementations, the value of K can be indicative of the ratio of the aspect ratio of the output transistor Q2 to the aspect ratio of the input transistor Ql, where the aspect ratio of a MOS transistor can be defined as the channel width of the transistor divided by its channel length. In embodiments where K is greater than 0 but less than 1, multiplying by K means reducing or attenuating the input signal to generate the output signal. In embodiments where K is greater than 1, multiplying by K means increasing or amplifying the input signal to generate the output signal.

[0020] In some embodiments, the current mirror circuit of any current mirror arrangement described herein can receive an input signal based on a bias current and a signal current used for the current mirror arrangement. In some embodiments, a current mirror arrangement with reduced input impedance can be implemented as a single-ended arrangement. In other embodiments, the current mirror arrangements described herein can be differential, as a given arrangement can include two instances of the current mirror arrangements described herein, which can be substantially copies of each other, differing from each other in each received input current (and therefore in each generated output current). For example, a first instance of a given current mirror arrangement can receive a first input current I. INP The input signal is in the form of a bias current IB and a signal current I for the current mirror arrangement. IN The sum (e.g., I) INP =IB+I IN ), while a second instance of a given current mirror arrangement can receive a second input current I. INM The input signal is in the form of a bias current IB and a signal current I. IN The difference between them (e.g., I) INM =IB-I IN Therefore, given first and second instances of a current mirror arrangement, they can be considered as parts of a differential current mirror arrangement. In such an embodiment, the output current of the first part can be I... OP =K*I INP The output current of the second part can be I. OM =K*I INM .

[0021] As those skilled in the art will understand, as described herein, aspects of this disclosure, particularly aspects of current mirror arrangements with reduced input impedance, can be embodied in various ways—for example, as a method or system. The following detailed description provides various descriptions of certain specific embodiments. However, the innovations described herein can be embodied in many different ways, for example, as defined and covered by the claims or selected examples. For instance, while some descriptions are provided herein with respect to bipolar (e.g., NPN or PNP embodiments) or MOS (e.g., NMOS or PMOS embodiments) transistors, other embodiments of the current mirror arrangements described herein may include any combination of bipolar and MOS transistors.

[0022] In the following description, reference is made to the accompanying drawings, wherein similar reference numerals may indicate the same or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that some embodiments may include more elements than shown in the figures and / or a subset of the elements shown. Additionally, some embodiments may combine any suitable combination of features from two or more figures.

[0023] With the numerous examples provided herein, interactions can be described in terms of two, three, four, or more electronic components. However, this has only been done for purposes of clarity and example. It should be understood that the devices and systems described herein can incorporate any suitable manner. Along similar lines of design alternatives, any of the illustrated components, modules, and elements of the present application can be combined in various possible configurations, all of which are clearly within the broad scope of this disclosure. In some cases, it can be easier to refer to a limited number of electrical elements to describe one or more functions of a given flow. It should be understood that the circuitry of the present figures and its teachings are readily scalable and can accommodate a large number of components, as well as more complicated or elaborate arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of circuitry potentially applied to a myriad of other architectures.

[0024] This description can use the phrases "in an embodiment," or "in embodiments," which can each refer to one or more of the same or different embodiments. The following capitalised terms are used throughout this description to denote the following: "first," "second," and "third," etc. are used to describe a common object and are merely used to distinguish different instances, unless otherwise specified, of the object, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. Various aspects of the illustrative embodiments are described using terminology that a person skilled in the art will be familiar with to convey the substance of the work to others skilled in the art. For example, the term "connected" refers to a direct electrical connection between the connected objects without any intermediate devices / components, while the term "coupled" refers to either a direct electrical connection between the connected things or an indirect connection through one or more passive or active intermediate devices / components. In another example, the term "circuitry" represents one or more passive and / or active components arranged to cooperate with each other to provide a desired function. If used, the terms "substantially," "approximately," "about," and the like can be used to generally refer to being within + / - 20% of a target value, for example, within + / - 10% of a target value, based on the context of a particular value described herein or known in the art. For the purposes of this disclosure, the phrase "A and / or B" or the symbol "A / B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used in reference to a measurement range, the term "between" includes the ends of the measurement range. As used herein, the symbol "A / B / C" means (A, B, and / or C).

[0025] The basis of a current mirror

[0026] To illustrate the current mirror arrangement with reduced input impedance achieved by including a fast, low-gain loop and a slow, high-gain loop at the input transistor of the current mirror circuit as proposed herein, it may be helpful to first understand the phenomena that may occur when mirroring current. The following basic information can be considered as the basis for a proper interpretation of this disclosure. Such information is provided for illustrative purposes only and should not be construed in any way as limiting the broad scope of this disclosure and its potential applications.

[0027] Figure 1 A circuit diagram of a simple single-ended NPN bipolar transistor implementation of a current mirror 100, wherein the current gain of the current mirror 100 is K, as is known in the art. Figure 1 As shown, the current mirror 100 may include a first transistor Q1 (which may be referred to as the "input transistor") and a second transistor Q2 (which may be referred to as the "output transistor"). Input current 102 (I IN (That is, the current to be mirrored at the output of current mirror 100 to generate output current 108) can be provided by input current source 104. Current mirror 100 can be provided first by placing transistor Q1 in a feedback state to make the current at the collector terminal 110 (or simply "collector" 110) of transistor Q1 equal to the input current 102, in feedback path 106 (node ​​N1, at...) Figure 1 A control voltage (voltage VN1) is generated on the marked (in the middle). For example... Figure 1 As shown, the emitter terminal 112 (or simply "emitter" 112) of transistor Q1 can be grounded. The base terminal 114 (or simply "base" 114) of transistor Q1 can be coupled to the base 124 of transistor Q2. The base 124 of output transistor Q2 can be driven using a voltage VN1 carrying input current information to generate an output current 108. Figure 1 The collector 120 and emitter 122 of transistor Q2 are also indicated, wherein the emitter 122 can be coupled to ground, and wherein the output current 108 is the current at the collector 120, as shown. Figure 1 As shown. When the emitter area of ​​transistor Q2 is K times that of transistor Q1, the output current is 108 (I). O It may equal K·I IN .

[0028] The following equation provides a simplified model of the collector current of a bipolar transistor:

[0029]

[0030] Where I C A, I S V BE and V tThese are the collector current, emitter area, saturation current per unit area, base-emitter voltage, and thermal voltage, respectively. Although the collector current (Ig) C ) and base-emitter voltage (V BE The relationship between (i.e., equivalent input current I) IN The relationship between I and voltage VN1 is strongly nonlinear, but the input-output current mirror relationship is linear, i.e., I... O =K·I IN .

[0031] The basic analysis given above has many shortcomings in understanding the performance degradation of current mirrors at high operating frequencies. Figure 2 A circuit diagram of an NPN implementation of the current mirror 200 is provided. The current mirror 200 and... Figure 1 The current mirror 100 is essentially the same, except that it additionally shows relevant parasitic elements for high operating frequencies. In other words, Figure 2 Significant parasitic devices that can reduce the bandwidth and linearity of the current mirror 100 are shown. It should be understood that parasitic components shown in the figures and discussed herein refer to components not intentionally created in the circuit, but rather to unintentional effects or behaviors that the circuit may exhibit as represented in the circuit diagram.

[0032] Figure 2 It has in Figure 1 The elements indicated by the reference numerals in the accompanying drawings are intended to illustrate their relationship with... Figure 1 Elements described are the same or similar to those in the original drawings; therefore, for the sake of brevity, their description will not be repeated. This applies to the other drawings in this disclosure – elements with reference numerals described with reference to one drawing may be the same or similar to elements with the same reference numerals shown in another drawing, and thus the description provided for one drawing is applicable to another drawing without needing to be repeated.

[0033] The current mirror 200 may be subject to parasitic capacitances 216, 218, 220, and 228, and a resistor 224 (which can be used to convert the output current 208 of the current mirror into a voltage), each of which can be as follows: Figure 2 The coupling is performed as shown.

[0034] Parasitic capacitance 216 can represent all the routing parasitic capacitances associated with node 106, the parasitic capacitance of the load node 106 of input current source 104, and the collector-substrate and extrinsic base parasitic capacitances of transistors Ql and Q2. Note that the bipolar transistor collector-substrate capacitance based on modern SOI technology is relatively small and can be considered linear. Parasitic capacitance 218 can represent the intrinsic base-emitter forward-biased diffusion capacitance of transistor Ql. Parasitic capacitance 220 can represent the intrinsic base-emitter forward-biased capacitance of transistor Q2 (and can be K times larger than parasitic capacitance 218 if the emitter area of transistor Q2 is K times larger than the emitter area of transistor Ql ). Parasitic capacitance 228 can represent the intrinsic base-collector junction parasitic capacitance of transistor Q2. Resistance 224 can represent the output resistance (RO) of current mirror 100 / 200.

[0035] The inventors of the present disclosure have recognized that, from an analysis of the circuit in Figure 2 The inventors of the present disclosure have recognized that, from an analysis of the circuit in Figure 2 The inventors of the present disclosure have recognized that, from an analysis of the circuit in GD The inventors of the present disclosure have recognized that, from an analysis of the circuit in

[0036] Reducing input impedance in a current mirror arrangement

[0037] Generally, different techniques can be employed to improve one or more of the above- described problems, where some trade-off in transaction performance and complexity can have to be made. As previously mentioned, the current of any of the capacitors of load node Nl can be modulated with the non-linear voltage at node Nl to the input current 102. Some of the load capacitors, such as bipolar base-emitter parasitic capacitors 218 and 220, can have the "right" non-linearity in that their current becomes linear when combined with the non-linear voltage at node Nl. All other capacitors on node Nl, such as parasitic capacitance 216, can cause non-linear modulation of input current 102 and degrade the linearity performance.

[0038] In addition to carefully adjusting device sizes and layouts to minimize such undesirable capacitors on node N1, the input side of the current mirror circuit can be modified to lower its impedance, or equivalently, to lower the N1 voltage swing. However, the inventors of the present disclosure recognize that direct solutions to reduce input impedance often result in creating other problems that compromise overall performance. For example, simply adding a transistor Q3 as shown in Figure 3 where the first terminal of transistor Q3 is coupled to a reference voltage Vref, and the second terminal of transistor Q3 is coupled to a bias current (IB), and the first terminal of transistor Q1 can reduce the impedance on node N1, but now introduces another high impedance with a non-linear voltage, namely node N2 (labeled in Figure 3 ). Thus, the non-linear voltage on node N2 modulates any capacitors that are loaded to node N2, the resulting non-linear current reaches the input node N1 through transistor Q3 and modulates the input current. Other solutions can result in low DC feedback gain, feedback current dependent on the input current, and low mirror ratio.

[0039] Embodiments of the present disclosure are based on the recognition that forming two feedback paths, where input transistor Q1 closes each feedback path to form respective loops, can provide improvements to at least some of the challenges described above. One example implementation of a current mirror arrangement with two such loops is shown in Figure 3 .

[0040] Figure 3 A circuit diagram of a current mirror arrangement 300 with reduced input impedance according to some embodiments of the present disclosure is provided. As shown in Figure 3 , as described above, the apparatus 300 includes a current mirror circuit formed by input transistor Q1 and output transistor Q2. The current mirror arrangement 300 is configured to receive an input current 302 (IB1+I IN ) from a current source 304 at the input of the current mirror formed by transistors Q1 and Q2 (e.g., at node 303), where the current of the second terminal 110 of input transistor Q1 is equal to I IN . Thus, the current source 304 can provide a bias current IB1 for the Q3 and Q4 current paths, which can be set beforehand. The bias current IB1 is the emitter current of transistor Q3 and is substantially constant. In this configuration, the collector current of input transistor Q1 (i.e., the current received at the second terminal 110 of input transistor Q1) can be substantially equal to I IN , as the portion IB1 of the original input current 302 is subtracted through the emitter connection of transistor Q3. The current I IN is the time-varying input current of transistor Q1, which is mirrored by the current mirror to produce a mirrored current (IO )108 (for example, at the second terminal 120 of the output transistor Q2). The relationship between the input current and the output current is I O =K*I IN Where K is a number greater than 0 (this value can be, but does not have to be, an integer), indicating the ratio of the emitter area of ​​transistor Q2 to the emitter area of ​​transistor Q1. In some implementations, the input current I... IN It is always positive and will not reach zero in practice to maintain circuit bias. A bias current portion IB1 must be provided in the input current 302 to distinguish this input current from the input current 102 in the conventional implementation (i.e., in the conventional current mirror, no additional bias current is required as part of the current mirror input current).

[0041] With Figures 1-2 Compared to the conventional current mirror implementation shown, the feedback path from the first terminal 114 to the second terminal 110 of transistor Q1 is modified by introducing a so-called "transistor matrix," i.e., multiple additional transistors. In some embodiments, the multiple additional transistors may include transistors Q3-Q6, such as... Figure 3 As shown. Specifically, a first subset of transistors Q3-Q6 can form a first loop 390-1 together with input transistor Q1. Figure 3 The second subset of transistors Q3-Q6 can form a second loop 390-2, as shown by dashed lines. Figure 3 As shown by the dashed lines in the image. Figure 3 As shown, the first loop 390-1 may include input transistors Q1 and Q3, while the second loop 390-2 may include input transistor Q1 and transistors Q5, Q6, and Q4. More specifically, the first loop 390-1 may include the following electrical path: a first terminal 114 of transistor Q1, a second terminal 110 of transistor Q1, a third terminal 332 of transistor Q3, and finally, the second terminal 330 of transistor Q3 coupled to the first terminal 114 of transistor Q1, thereby completing the first loop 390-1. The second loop 390-2 may include the following electrical path: a first terminal 114 of transistor Q1, a second terminal 110 of transistor Q1, a first terminal 354 of transistor Q5, a third terminal 352 of transistor Q5, a third terminal 362 of transistor Q6, a second terminal 360 of transistor Q6, a first terminal 344 of transistor Q4, and finally, the third terminal 342 of transistor Q4 coupled to the first terminal 114 of transistor Q1, thereby completing the second loop 390-2.

[0042] The first loop 390-1 can be a low-gain loop, while the second loop 390-2 can be a high-gain loop, because these loops can be designed such that the gain of the first loop 390-1 is lower than the gain of the second loop 390-2. Furthermore, the first loop 390-1 can be a fast loop, while the second loop 390-2 can be a slow loop, because the first loop 390-1 has a lower gain than the second loop 390-2. IN The second loop 390-2 dominates at higher frequencies of the input current 302 (e.g., I of the input current 302). IN (Partially) dominates at lower frequencies. Because the second loop 390-2 surrounds the first loop 390-1, the second loop can be called the "outer" loop, while the first loop can be called the "inner" loop.

[0043] Transistors Q5 and Q6 form a high-gain second loop 390-2. Since transistor Q1 disables feedback by inverting its input, the signal polarity of the high-gain path in the second loop 390-2 can be designed to be positive when the output of the high-gain path reaches the first terminal 114 of transistor Q1 to maintain negative feedback. For example... Figure 3 As shown, a reference voltage Vref can be applied to the first terminal 364 of transistor Q6, while a bias current (IB) 306 can be applied to the second terminal 360 of transistor Q6 and the first terminal 344 of transistor Q4. The bias current 306, together with the reference voltage Vref, can be configured to set the static voltage levels at nodes N1 and N3 (N3 is the node coupling the third terminal 352 of transistor Q5 and the third terminal 362 of transistor Q6). Since the static voltages of N1 and N3 are set, the static bias current of transistor Q3 is also set. The bias current of transistor Q3 can be tuned to a desired level, for example, to a bias current IB1, which, as described above, is provided as part of the input current 302 (i.e., bias current IB1 is different from bias current IB 306), by appropriately selecting the emitter area ratio of transistors Q5 and Q3. In other words, the bias current IB1 of transistor Q3 can be determined relative to the emitter area ratio of transistors Q5 and Q3 and the bias current IB 306.

[0044] Transistor Q4 can have a dual role. On one hand, it can act as a diode load for the fast inner loop 390-1, which can reduce the node N2 impedance and linearize the emitter current of transistor Q3. On the other hand, it can act as a unity-gain buffer (or simply “buffer”, also known as a unity-gain amplifier, buffer amplifier, voltage follower, or isolation amplifier) for the high-gain outer loop 390-2. Transistor Q4 effectively sums the signals in the inner loop 390-1 and the outer loop 390-2 at node N2 to drive input transistor Q1 (i.e., by applying the sum of the signals of the inner loop 390-1 and the outer loop 390-2 to the first terminal 114 of input transistor Q1).

[0045] Since the first loop 390-1 has only 2 nodes, it is essentially unconditionally stable. Because the second loop 390-2 has more nodes, in some embodiments, compensation capacitor 380 and optionally resistor 370 can be coupled to the second loop 390-2 to stabilize the loop. For example, if resistor 370 is used (which can be advantageous in terms of further improving bandwidth), a first terminal of resistor 370 can be coupled to the first terminal 344 of transistor Q4 and the second terminal 360 of transistor Q6 (i.e., to node N4), while a second terminal of resistor 370 can be coupled to ground potential (labeled “Vgnd” in Figure 3 When resistor 370 is used, a first capacitor electrode of compensation capacitor 380 can be coupled to the second terminal of resistor 370, while a second capacitor electrode of compensation capacitor 380 can be coupled to ground potential Vgnd. When resistor 370 is not used, a first capacitor electrode of compensation capacitor 380 can be coupled to the first terminal 344 of transistor Q4 and the second terminal 360 of transistor Q6 (i.e., node N4), while a second capacitor electrode of compensation capacitor 380 can be coupled to Vgnd. In some embodiments, the value of resistor 370 can be based on the transconductance of transistor Q4 (i.e., gm(Q4)), for example, the value of resistor 370 can be substantially equal to 1 / gm(Q4). The size of capacitor 380 (and thus the capacitance of capacitor 380) can be selected to achieve a desired loop phase margin.

[0046] For current mirror arrangement 300, at relatively low input frequencies, the high-gain second loop 390-2 can be configured to properly bias and accurately produce the voltage at node N2 (i.e., the voltage at the first terminal 114 of input transistor Q1), while at higher input frequencies, the fast first loop 390-1 can extend the linear operating frequency band. Thus, at lower frequencies of input signal 302 (e.g., the current portion I INat frequencies below the frequency of the input signal 302 (e.g., the current portion I IN As the frequency of the input signal 302 (e.g., the current portion I

[0047] The current mirror arrangement 300 shows an example of a current mirror arrangement with reduced input impedance, wherein the transistors Q1, Q2 and Q5 are implemented as NPN transistors, while the transistors Q3, Q4 and Q6 are implemented as PNP transistors. This implementation can be advantageous in terms of increasing the linear operating bandwidth provided by the current mirror arrangement described herein.

[0048] Summary Figure 3 Aspects of the current mirror arrangement 300 are shown, wherein, Figure 3 All base terminals of the bipolar transistors shown are referred to as “first terminals”, Figure 3 All collector terminals of the bipolar transistors shown are referred to as “second terminals”, and Figure 3 All emitter terminals of the bipolar transistors shown are referred to as “third terminals”, then the following holds. The current mirror arrangement 300 comprises a current mirror circuit comprising an input transistor Q1 and an output transistor Q2. The current mirror arrangement 300 is configured to receive an input, namely an input current 302 equal to IB1+I IN The input current 302 is applied as input to the second terminal of the input transistor Q1 and the third terminal of the transistor Q3. The current IB1 is a constant bias current of the transistor Q3, which is set with respect to a bias current IB 306 (applied to the second terminal 360 of the transistor Q6 and the first terminal 344 of the transistor Q4) and the emitter area ratio of the transistors Q5 and Q3 when the transistors Q5 and Q3 are bipolar transistors, with respect to the emitter area ratio of the transistors Q5 and Q3 when the transistors Q5 and Q3 are bipolar transistors, with respect to the aspect ratio of the transistor Q5 to the aspect ratio of the transistor Q3 when the transistors Q5 and Q3 are MOS transistors, wherein the aspect ratio of a MOS transistor is defined as the channel width divided by the channel length. The portion IB1 of the input current 302 is effectively subtracted by the transistor Q3, and then there is essentially only the portion I INThe second terminal 110 of the input transistor Q1 receives an input current. The current mirror arrangement 300 is configured to provide an output current, i.e. the output current 108, which is mirrored with a factor K, i.e. relative to the input current I IN received by the second terminal 110 of the input transistor Q1. For example, the current mirror arrangement 300 can generate an output current I O = K * I IN , where K represents the ratio of the area of the emitter of the transistor Q2 to the area of the emitter of the transistor Q1. The first terminal 114 of the transistor Q1 can be coupled to the first terminal 124 of the transistor Q2. Because the transistor Q1 of the current mirror arrangement 300 is an N-type transistor, its third terminal 112 can be coupled to a ground potential (labeled as “Vgnd” in the present figure), while its second terminal 110 can be coupled to an input current 302, which can be provided by a current source 304, which can be coupled to a supply voltage (labeled as “Vs” in the present figure). Because the transistor Q2 of the current mirror arrangement 300 is also an N-type transistor, its third terminal 122 can be coupled to a ground potential, while its second terminal 120 can be coupled to a supply voltage. The current mirror arrangement 300 further comprises a transistor matrix comprising transistors Q3-Q6. The second terminal 110 of the transistor Q1 can be coupled to each of the third terminal 332 of the transistor Q3 and the first terminal 354 of the transistor Q5. The third terminal 352 of the transistor Q5 can be coupled to the third terminal 362 of the transistor Q6. The first terminal 364 of the transistor Q6 can be coupled to a reference voltage. The second terminal 360 of the transistor Q6 can be coupled to the first terminal 344 of the transistor Q4. A first capacitor electrode of a compensation capacitor 380 can be coupled to each of the second terminal 360 of the transistor Q6 and the first terminal 344 of the transistor Q4 via a resistor 370, while a second capacitor electrode of the compensation capacitor 380 can be coupled to a ground potential. The third terminal 342 of the transistor Q4 can be coupled to each of the second terminal 330 of the transistor Q3 and the first terminal 114 of the transistor Q1, or in other words, the first terminal 114 of the transistor Q1 can be coupled to each of the second terminal 330 of the transistor Q3 and the third terminal 342 of the transistor Q4. The first terminal 334 of the transistor Q3 can be coupled to each of the third terminal 352 of the transistor Q5 and the third terminal 362 of the transistor Q6. Because the transistor Q5 of the current mirror arrangement 300 is an N-type transistor, its second terminal 350 can be coupled to a supply voltage. Because the transistor Q4 of the current mirror arrangement 300 is a P-type transistor, its second terminal 340 can be coupled to a ground potential. A bias current source 306 can be coupled between a ground potential and each of the first terminal 344 of the transistor Q4 and the second terminal 360 of the transistor Q6.

[0049] While the above description relates to bipolar implementations of transistors, in other embodiments, the current mirror arrangement may include transistors implemented using MOS technology, such as FETs. Specifically, according to some embodiments of this disclosure, Figure 4 A circuit diagram is provided for a MOS implementation of a current mirror arrangement 400 with reduced input impedance, wherein transistors Q1, Q2, and Q5 are implemented as NMOS transistors, while transistors Q3, Q4, and Q6 are implemented as PMOS transistors. The current mirror arrangement 400 is substantially similar to the current mirror arrangement 300, except that each NPN transistor (i.e., transistors Q1, Q2, and Q5) in the current mirror arrangement 300 is replaced by an NMOS transistor in the current mirror arrangement 400, and each PNP transistor (i.e., transistors Q3, Q4, and Q6) in the current mirror arrangement 300 is replaced by a PMOS transistor in the current mirror arrangement 400. In this configuration, the only difference is that the "first terminal" or "base terminal" of the bipolar transistor is changed to... Figure 4 The current mirror arrangement is outside the "gate terminal" of the 400 MOS transistor, referenced. Figure 3 The provided description is applicable; the "second terminal" or "collector terminal" of the bipolar transistor becomes... Figure 4 The current mirror arrangement of the 400 MOS transistor's "drain terminal" transforms the "third terminal" or "emitter terminal" of the bipolar transistor into... Figure 4 The current mirror arrangement 400 represents the "source terminal" of the MOS transistor. In contrast to the bipolar implementation, for the MOS implementation with the current mirror arrangement 400, K is the value indicating the ratio of the aspect ratio of transistor Q2 to that of transistor Q1. Figure 3 The reference numbers 110, 112, 114, 120, 122, and 124 for the transistor terminals of transistors Q1 and Q2 can be respectively used as... Figure 4 The reference numbers 410, 412, 414, 420, 422, and 424 are replaced by the reference numbers 410, 412, 414, 420, 422, and 424 for the current mirror arrangement of transistors Q1 and Q2. Similarly, it indicates... Figure 3 The reference numbers 330, 332, 334, 340, 342, 344, 350, 352, 354, 360, 362, and 364 for the transistor terminals of transistors Q3, Q4, Q5, and Q6 can be respectively used as... Figure 4 The reference numbers 430, 432, 434, 440, 442, 444, 450, 452, 454, 460, 462, and 464 are used to replace the reference numbers 400 for the current mirror arrangement of transistors Q3-Q6. For the sake of brevity, no further details are provided. Figure 4 A detailed description is needed, because apart from the changes noted above, it is essentially similar to... Figure 3 The description therefore does not provide any information. Figure 4 A detailed description.

[0050] Further variations of the current mirror arrangement with reduced input impedance are possible. In particular, while the description above provides for Figure 3 and Figure 4 the N-type implementation of transistors Q1, Q2 and Q5 and the P-type implementation of transistors Q3, Q4 and Q6, in other embodiments, transistors Q1, Q2 and Q5 can be implemented as P-type transistors, while transistors Q3, Q4 and Q6 can be implemented as N-type transistors, some examples of which are shown in Figure 5 and 6 .

[0051] Figure 5 A circuit diagram of a current mirror arrangement 500 with reduced input impedance according to some embodiments of the disclosure is provided. The arrangement 500 can be considered a second example of a bipolar implementation (the first example being that of Figure 3 ), in which transistors Q1, Q2 and Q5 are implemented as PNP transistors, while transistors Q3, Q4 and Q6 are implemented as NPN transistors. The current mirror arrangement 500 is substantially similar to the current mirror arrangement 300, except that each NPN transistor in the current mirror arrangement 300 (i.e. transistors Q1, Q2 and Q5) is replaced by a PNP transistor in the current mirror arrangement 500, and each PNP transistor in the current mirror arrangement 300 (i.e. transistors Q3, Q4 and Q6) is replaced by an NPN transistor in the current mirror arrangement 500. In such a configuration, the description provided with reference to Figure 3 applies to the current mirror arrangement 500, except that the NPN and PNP transistors are swapped, and the supply and current directions are reversed (i.e. compared to Figure 3 , Figure 5 the names of the supply voltages Vs and ground voltage Vgnd in Figure 5 remain the same, except that the second terminal of the capacitor 380 is still coupled to ground in the arrangement 500. In Figure 3 , the reference numerals 1 10, 1 12, 1 14, 120, 122, 124 indicating the transistor terminals of transistors Q1 and Q2 in Figure 5 may be replaced by reference numerals 510, 512, 514, 520, 522, 524 of transistors Q1 and Q2 of the current mirror arrangement 500 of Figure 3 . Similarly, the reference numerals 330, 332, 334, 340, 342, 344, 350, 352, 354, 360, 362 and 364 indicating the transistor terminals of transistors Q3, Q4, Q5 and Q6 in Figure 5the reference numbers 530, 532, 534, 540, 542, 544, 550, 552, 554, 560, 562, and 564 of the transistors Q3-Q6 of the current mirror arrangement 500 instead. For brevity, the detailed description of Figure 5 is not provided, as it is substantially similar to the description of Figure 3 , except for the changes indicated above, and thus is not repeated.

[0052] In yet another embodiment, the PNP transistors Q1, Q2, and Q5 of the current mirror arrangement 500 can be replaced with PMOS transistors, while the NPN transistors Q3, Q4, and Q6 of the current mirror arrangement 500 can be replaced with NMOS transistors, as shown in the current mirror arrangement 600 of Figure 6 , according to some embodiments of the present disclosure, Figure 6 a circuit diagram of a CMOS implementation of the current mirror arrangement 600 is provided, which has a reduced input impedance. The arrangement 600 can be considered a second example of a CMOS implementation (the first example being Figure 4 ), in which the transistors Q1, Q2, and Q5 are implemented as PMOS transistors, while the transistors Q3, Q4, and Q6 are implemented as NMOS transistors. The current mirror arrangement 600 is substantially similar to the current mirror arrangement 500, except that each NPN transistor (i.e., transistors Q3, Q4, and Q6) in the current mirror arrangement 500 is replaced by an NMOS transistor in the current mirror arrangement 600, and each PNP transistor (i.e., transistors Q1, Q2, and Q5) of the current mirror arrangement 500 is replaced by a PMOS transistor in the current mirror arrangement 600. In such a configuration, the description provided with reference to Figure 5 is applicable, except that the “first terminal” or “base terminal” of the bipolar transistor becomes the “gate terminal” of the MOS transistor of the current mirror arrangement 600 Figure 6 , the “second terminal” or “collector terminal” of the bipolar transistor becomes the “drain terminal” of the MOS transistor of the current mirror arrangement 600 Figure 6 , the “third terminal” or “emitter terminal” of the bipolar transistor becomes the “source terminal” of the MOS transistor of the current mirror arrangement 600 Figure 6 , the “source terminal” of the MOS transistor. In contrast to the bipolar implementation shown in Figure 5 , for the MOS implementation of the current mirror arrangement 600, K refers to a value indicative of the ratio of the aspect ratio of transistor Q2 to the aspect ratio of transistor Q1. It is shown that Figure 5 the reference numbers 510, 512, 514, 520, 522, 524, 530, 532, 534, 540, 542, 544, 550, 552, 554, 560, 562, and 564 of the transistor terminals of the transistors Q1-Q6 in Figure 6the transistors Q1-Q6 of the current mirror arrangement 600 of FIG. 6. For brevity, a detailed description of the current mirror arrangement 600 of FIG. 6 is not provided, as it is substantially similar to the current mirror arrangement 500 of FIG. 5, except for the changes noted above. Figure 6 Figure 5

[0053] Further variations of the current mirror arrangement with reduced input impedance are possible.

[0054] In one example, in some embodiments, a current mirror arrangement having P-type transistors Q1, Q2, and Q5 (e.g., a current mirror arrangement similar to the current mirror arrangement 300 or 400) can include a combination of PNP and PMOS transistors (i.e., one or more of the transistors Q1, Q2, and Q5 can be implemented as a PNP transistor, while one or more of the transistors Q1, Q2, and Q5 can be implemented as a PMOS transistor). In addition to or in lieu of these embodiments, a current mirror arrangement having N-type transistors Q3, Q4, and Q6 (e.g., a current mirror arrangement similar to the current mirror arrangement 300 or 400) can include a combination of NPN and NMOS transistors (i.e., one or more of the transistors Q3, Q4, and Q6 can be implemented as an NPN transistor, while one or more of the transistors Q3, Q4, and Q6 can be implemented as an NMOS transistor).

[0055] Similarly, in another example, in some embodiments, a current mirror arrangement having P-type transistors Q1, Q2, and Q5 (e.g., a current mirror arrangement similar to the current mirror arrangement 500 or 600) can include a combination of PNP and PMOS transistors (i.e., one or more of the transistors Q1, Q2, and Q5 can be implemented as a PNP transistor, while one or more of the transistors Q1, Q2, and Q5 can be implemented as a PMOS transistor). In addition to or in lieu of these embodiments, a current mirror arrangement having N-type transistors Q3, Q4, and Q6 (e.g., a current mirror arrangement similar to the current mirror arrangement 500 or 600) can include a combination of NPN and NMOS transistors (i.e., one or more of the transistors Q3, Q4, and Q6 can be implemented as an NPN transistor, while one or more of the transistors Q3, Q4, and Q6 can be implemented as an NMOS transistor).

[0056] Example system of a current mirror arrangement with reduced input impedance

[0057] ​​The various embodiments of current mirror arrangements with reduced input impedance as described above can be implemented in any kind of system that can use a current mirror. Such current mirror arrangements are particularly useful in systems that require a current mirror with both high linearity and wide signal bandwidth. According to some embodiments of the present disclosure, one example of such a system is shown in Figure 7 which provides a schematic diagram of a system 700 implementing a current mirror arrangement 712. As shown in Figure 7 the system 700 can include an analog-to-digital converter (ADC) driver 710 and an ADC 720. The ADC driver 710 can be used to provide a drive signal to drive the ADC 720 so that the ADC 720 can, for example, convert an analog electrical signal into digital form for data processing. In particular, the ADC driver 710 can include a current mirror arrangement 712, which can be implemented according to any of the embodiments of current mirror arrangements with reduced input impedance as described above. For example, as described above, the current mirror arrangement 712 can be implemented as the current mirror arrangements 300, 400, 500, or 600, or as any other embodiment of these current mirror arrangements. The ADC driver 710 can then generate the drive signal based on the output signal generated by the current mirror arrangement 712. In various embodiments, the drive signal generated by the ADC driver 710 can be used to drive the single or differential inputs of the ADC 720.

[0058] In various embodiments, the drive signal generated by the ADC driver 710 can implement / enable functionalities such as buffering, amplitude scaling, single-ended to differential and differential to single-ended conversion, common mode offset adjustment, and filtering. In other words, the ADC driver 710 can be used as a signal conditioning element in the data conversion stage and can be a key factor in enabling the ADC 720 to achieve its desired performance. The ADC 720 can be any type of ADC, such as but not limited to a successive approximation register (SAR) converter, a pipeline converter, a flash converter, or a sigma-delta converter.

[0059] Figure 7The illustrated system 700 provides only one non-limiting example in which a current mirror arrangement as described herein can be used, and various teachings relating to a current mirror arrangement with reduced input impedance as described herein are applicable to a variety of other systems. In some cases, various embodiments of a current mirror arrangement with reduced input impedance as described herein can be used in automotive systems, safety-critical industrial applications, medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which can be very accurate), and various digital processing-based systems. In other cases, various embodiments of a current mirror arrangement with reduced input impedance as described herein can be used in industrial markets that include process control systems that help improve productivity, energy efficiency, and reliability. In still other scenarios, various embodiments of a current mirror arrangement with reduced input impedance can be used in consumer applications.

[0060] In one example implementation, any number of the circuits in the present figures can be implemented on a board of an associated electronic device. The board can be a general-purpose circuit board or a dedicated circuit board tailored to the particular needs of the electronic device. The board can be provided by any suitable process, such as, but not limited to, photolithographic processes, etching processes, and / or deposition processes. In this regard, the board can be provided over a substrate, such as a silicon wafer, glass plate, or other substrate. The board can be configured to receive components of an internal electronic system of the electronic device and can provide connectors for other peripheral devices. More specifically, the board can provide electrical connections by which the other components of the system can communicate electrically. Any suitable processors (including without limitation digital signal processors, microprocessors, supporting chipsets, etc.), computer- readable non-transitory memory elements, etc. can be suitably coupled to the board as

[0061] In another example implementation, the circuits of the present figures can be implemented as a standalone module (e.g., a device with relevant components and circuitry configured to perform a particular application or function) or as an insert in a dedicated hardware of an electronic device. Note that particular embodiments of the present disclosure relating to a current mirror arrangement with reduced input impedance can be readily included in a system-on-chip (SOC) package, either in part, or in whole. An SOC represents an integrated circuit that integrates components of a computer or other electronic systems into a single chip. It can contain digital, analog, mixed-signal, and often radio-frequency functions: all of which can be provided over the single chip substrate. Other embodiments can include a multi-chip-module (MCM), with a plurality of separate ICs located together on a single module or carrier, with components that are configured to interact and work together. In a variety of further embodiments, functionality of the current mirror arrangement with reduced input impedance presented herein can be implemented in one or more silicon cores in a system on a chip (SoC), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and other semiconductor chips.

[0062] Selection example

[0063] The following paragraphs provide examples of various embodiments disclosed herein.

[0064] Example 1 provides a current mirror arrangement comprising a plurality of transistors each having a first terminal, a second terminal, and a third terminal. The plurality of transistors comprises at least transistors Q1, Q2, Q3, and Q4 arranged such that the first terminal of the transistor Q1 is coupled to the first terminal of the transistor Q2, the second terminal of the transistor Q1 is coupled to the third terminal of the transistor Q3, and the first terminal of the transistor Q1 is further coupled to the second terminal of the transistor Q3 and the third terminal of the transistor Q4.

[0065] Example 2 provides the current mirror arrangement according to example 1, wherein the second terminal of the transistor Q3 is coupled to the third terminal of the transistor Q4.

[0066] Example 3 provides the current mirror arrangement according to example 1 or 2, wherein the second terminal of the transistor Q4 is coupled to a ground potential.

[0067] Example 4 provides the current mirror arrangement according to any one of the preceding examples, wherein the plurality of transistors further comprises a transistor Q5 and a transistor Q6 arranged such that the third terminal of the transistor Q3 is coupled to the first terminal of the transistor Q5, the third terminal of the transistor Q5 is coupled to the third terminal of the transistor Q6, the second terminal of the transistor Q6 is coupled to the first terminal of the transistor Q4, and the first terminal of the transistor Q3 is coupled to the third terminal of the transistor Q5 and the third terminal of the transistor Q6.

[0068] Example 5 provides the current mirror arrangement according to example 4, wherein the first terminal of the transistor Q6 is coupled to a reference voltage.

[0069] Example 6 provides the current mirror arrangement according to example 4 or 5, wherein the second terminal of the transistor Q6 is coupled to a bias current.

[0070] Example 7 provides the current mirror arrangement according to any one of examples 4-6, wherein the second terminal of the transistor Q6 is coupled to a compensation capacitor.

[0071] Example 8 provides the current mirror arrangement according to example 7, further comprising a resistor coupled between the second terminal of the transistor Q6 and the compensation capacitor.

[0072] Example 9 provides a current mirror arrangement according to any one of the preceding examples, wherein the current mirror arrangement is configured to receive an input current (e.g. at the second terminal of transistor Ql), and to generate a mirror current (e.g. output at the second terminal of transistor Q2) based on the input current.

[0073] In further examples of the current mirror arrangement according to any one of the preceding examples, the third terminals of transistors Ql and Q2 can be coupled to a ground potential, and / or the second terminal of transistor Q5 can be coupled to a power supply (complementary to ground). In further examples of the current mirror arrangement according to any one of the preceding examples, the transistor types of transistors Ql, Q2 and Q5 can be complementary to the transistor types of transistors Q3, Q4 and Q6 (e.g. if transistors Ql, Q2 and Q5 are N-type transistors, then transistors Q3, Q4 and Q6 are P-type transistors, and vice versa).

[0074] Example 10 provides a current mirror arrangement comprising a current mirror circuit comprising an input transistor Ql and an output transistor Q2, and further comprising a transistor matrix comprising a plurality of transistors coupled between a first terminal of the input transistor Ql and a second terminal of the input transistor Ql.

[0075] Example 11 provides a current mirror arrangement according to example 10, wherein the transistor matrix comprises a transistor Q3, and the transistor Q3 and the input transistor Ql are coupled in a loop comprising the first terminal of the input transistor Ql, a second terminal of the transistor Q3, a third terminal of the transistor Q3 and the second terminal of the input transistor Ql.

[0076] In another example, the transistor matrix can further comprise a transistor Q4, such that a third terminal of the transistor Q4 is included in the loop of example 11. In such a loop, the transistor Q4 can operate like a resistive load, with a resistance that can be equal to 1 / gm(Q4).

[0077] Example 12 provides a current mirror arrangement according to example 11, wherein the loop is a first loop, the transistor matrix further comprises transistors Q4, Q5 and Q6, and the transistors Q4, Q5 and Q6 are coupled with the input transistor Ql in a second loop comprising the first terminal of the input transistor Ql, a third terminal of the transistor Q4, a second terminal of the transistor Q6, a third terminal of the transistor Q6, a third terminal of the transistor Q5, a first terminal of the transistor Q5 and the second terminal of the input transistor Ql.

[0078] Example 13 provides the current mirror arrangement according to Example 12, wherein the input transistor Ql is configured to be driven by a combination of a signal of the first loop at the second terminal of the transistor Q3 and a signal of the second loop at the third terminal of the transistor Q4 (i.e., such signal combination is applied to the first terminal of the input transistor Ql).

[0079] Example 14 provides the current mirror arrangement according to Example 12 or 13, wherein the gain of the second loop is higher than the gain of the first loop.

[0080] Example 15 provides the current mirror arrangement according to any one of Examples 12-14, wherein at lower frequencies of the input current, the gain of the current mirror arrangement is determined primarily by the gain of the second loop, and at higher frequencies of the input current, the gain of the current mirror arrangement is determined primarily by the gain of the first loop.

[0081] Example 16 provides the current mirror arrangement according to any one of Examples 12-15, further comprising a compensation capacitor coupled to the second loop (e.g., coupled to the second terminal of the transistor Q6).

[0082] Example 17 provides the current mirror arrangement according to any one of Examples 12-16, further comprising a bias current source coupled to the second loop (e.g., coupled to the second terminal of the transistor Q6).

[0083] Example 18 provides the current mirror arrangement according to any one of the preceding Examples, wherein each of the transistors Q3, Q4, and Q6 is a first type of transistor of two types of transistors, each of the transistors Ql, Q2, and Q5 is a second type of transistor of the two types of transistors, and the two types of transistors are N-type transistors (e.g., NMOS or NPN transistors) and P-type transistors (e.g., PMOS or PNP transistors).

[0084] For example, in some embodiments, the transistors Q3, Q4, and Q6 can be P-type transistors such as PMOS and / or PNP transistors, and the transistors Ql, Q2, and Q5 can be N-type transistors such as NMOS and / or NPN transistors. In other embodiments, the transistors Q3, Q4, and Q6 can be N-type transistors such as NMOS and / or NPN transistors, and the transistors Ql, Q2, and Q5 can be P-type transistors such as PMOS and / or PNP transistors.

[0085] In various other examples of the current mirror arrangement according to any one of Examples 10-18, the transistors Ql-Q6 of the current mirror arrangement according to any one of Examples 10-18 can be arranged as specified for the current mirror arrangement of any one of Examples 1-9.

[0086] Example 19 provides a current mirror arrangement including a current mirror circuit having an input transistor (Ql) and an output transistor (Q2), the current mirror circuit configured to receive an input current and generate an output current based on the input current. The current mirror arrangement further includes a plurality of other transistors, wherein a first subset of the plurality of other transistors is coupled to form a first feedback path from a first terminal of the input transistor to a second terminal of the input transistor, and a second subset of the plurality of other transistors is coupled to form a second feedback path from the first terminal of the input transistor to the second terminal of the input transistor, the second feedback path being different than the first feedback path (e.g., due to the second subset of other transistors including at least one transistor not included in the first subset, or the first subset of other transistors including at least one transistor not included in the second subset).

[0087] Example 20 provides the current mirror arrangement of Example 19, wherein a gain of a loop formed by the input transistor and the second feedback path is higher than a gain of a loop formed by the input transistor and the first feedback path.

[0088] Example 21 provides the current mirror arrangement of Example 19 or 20, wherein at lower frequencies of the input current, a loop gain of the current mirror arrangement is dominated by a gain of a loop formed by the input transistor and the second feedback path, and at higher frequencies of the input current, the loop gain of the current mirror arrangement is dominated by a gain of a loop formed by the input transistor and the first feedback path.

[0089] Example 22 provides the current mirror arrangement of any of Examples 19-21, further including a compensation capacitor coupled to a loop formed by the input transistor and the second feedback path (e.g., coupled to a second terminal of transistor Q6).

[0090] Example 23 provides the current mirror arrangement of any of Examples 19-22, further including a bias current source coupled to a loop formed by the input transistor and the second feedback path (e.g., coupled to a second terminal of transistor Q6).

[0091] In various additional examples of the current mirror arrangement according to any of Examples 19-23, the transistors can be arranged as specified for the current mirror arrangement according to any of Examples 1-18.

[0092] Example 24 provides a current mirror arrangement including an input transistor Q1 configured to receive an input current, an output transistor Q2 configured to output a mirror current based on the input current, wherein a drive signal is generated based on the mirror current; and a transistor matrix including a plurality of transistors forming a first signal loop and a second signal loop, each of the first signal loop and the second signal loop including a first terminal and a second terminal of the input transistor Q1.

[0093] Example 25 provides the current mirror arrangement of Example 24, wherein the current mirror arrangement further includes a bias current source coupled to the second loop, and a gain of the second loop is higher than a gain of the first loop.

[0094] In various other examples, the current mirror arrangement according to any one of Examples 24-25 can be the current mirror arrangement according to any one of Examples 1-23.

[0095] Example 26 provides an electronic device including an ADC configured to perform analog-to-digital conversion; further including an ADC driver configured to provide a drive signal to the ADC to enable the ADC to perform analog-to-digital conversion, the ADC driver including the current mirror arrangement according to any one of the preceding examples.

[0096] Example 27 provides the electronic device of Example 24, wherein the electronic device is or is included in automated test equipment, test equipment, military radar / LIDAR, civilian radar / LIDAR, automotive radar / LIDAR, industrial radar / LIDAR, cellular base station, high-speed wired or wireless communication transceiver, or high-speed digital control system.

[0097] In other embodiments, in addition to being included in an ADC driver, the current mirror arrangement according to any one of the preceding examples can be incorporated in other kinds of components of an electronic device. Examples of other components that can incorporate the current mirror arrangement according to any one of the preceding examples include amplifiers, mixers, and filters, e.g., high-speed amplifiers, high-speed mixers, and high-speed filters. In turn, such components can be included in devices such as automated test equipment, test equipment, military radar / LIDAR, civilian radar / LIDAR, automotive radar / LIDAR, industrial radar / LIDAR, cellular base station, high-speed wired or wireless communication transceiver, or high-speed digital control system.

Claims

1. An electronic device comprising a current mirror arrangement, the current mirror arrangement comprising: a current mirror circuit including an input transistor (Q1) and an output transistor (Q2), the current mirror circuit configured to receive an input current and generate an output current based on the input current; and a plurality of further transistors, including a first subset of the further transistors and a second subset of the further transistors; wherein the transistors in the first subset are coupled to provide a first feedback path connecting from a first terminal of the input transistor (Q1) to a second terminal of the input transistor (Q1), wherein the first subset of the further transistors includes a third transistor (Q3) having a first terminal coupled to the first terminal of the input transistor (Q1); and wherein the transistors in the second subset are coupled to provide a second feedback path connecting from the first terminal of the input transistor (Q1) to the second terminal of the input transistor (Q1), wherein the second feedback path is different from the first feedback path and includes the second subset of the further transistors, wherein the second subset includes at least a fourth transistor (Q4) having a first terminal coupled to the first terminal of the input transistor (Q1).

2. The electronic device of claim 1, wherein a gain of the second feedback path is higher than a gain of the first feedback path, wherein the second subset further comprises: a fifth transistor (Q5) having a first terminal coupled to the second terminal of the input transistor (Q1); and a sixth transistor (Q6) coupled between the fourth transistor (Q4) and the fifth transistor (Q5). 3.The electronic device of claim 1, wherein, At lower frequencies of the input current, the loop gain of the current mirror arrangement is mainly determined by the input transistor (Q1) and the gain of the second feedback path, while at higher frequencies of the input current, the loop gain of the current mirror arrangement is mainly determined by the input transistor (Q1) and the gain of the first feedback path.

4. The electronic device of claim 1, further comprising a compensation capacitor coupled to a circuit loop formed by the input transistor (Q1) and the second feedback path.

5. The electronic device of claim 1, further comprising a bias current source coupled to a circuit loop formed by the input transistor (Q1) and the second feedback path.

6. The electronic device of claim 1, wherein the current mirror arrangement is comprised in a driver for an analog-to-digital converter.

7. The electronic device of any of claims 1-6, wherein the electronic device is a system comprising an analog-to-digital converter and a driver for the analog-to-digital converter, and wherein the current mirror arrangement is comprised in the driver for the analog-to-digital converter.

8. An electronic device comprising a current mirror arrangement, the current mirror arrangement comprising: a plurality of transistors, each transistor having a first terminal, a second terminal, and a third terminal, the plurality of transistors including at least a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), and a fourth transistor (Q4); wherein the first transistor (Q1) has a first terminal coupled to a first terminal of the second transistor (Q2) and a second terminal coupled to a first terminal of the third transistor (Q3), and wherein the second transistor (Q2) has a second terminal coupled to a second terminal of the third transistor (Q3) and a third terminal coupled to a second terminal of the fourth transistor (Q4). a first feedback loop comprising a first transistor (Q1) and a first feedback path connected from a first terminal (114) of the first transistor (Q1) to a second terminal (110) of the first transistor (Q1); and a second feedback loop comprising the first transistor (Q1) and a second feedback path connected from the first terminal (114) of the first transistor (Q1) to the second terminal (110) of the first transistor (Q1), wherein: the first terminal (114) of the first transistor (Q1) is coupled to a first terminal (124) of the second transistor (Q2), the second terminal (110) of the first transistor (Q1) is coupled to a third terminal (332) of the third transistor (Q3), the first terminal (114) of the first transistor (Q1) is further coupled to each of a second terminal (330) of the third transistor (Q3) and a third terminal (342) of the fourth transistor (Q4), and wherein the first feedback path comprises the third transistor (Q3) and the second feedback path comprises at least the fourth transistor (Q4), and wherein the first feedback loop has a different gain than the second feedback loop.

9. The electronic device of claim 8, wherein the second terminal of the third transistor (Q3) is coupled to the third terminal of the fourth transistor (Q4).

10. The electronic device of claim 8, wherein the second terminal of the fourth transistor (Q4) is coupled to a ground potential.

11. The electronic device of claim 8, wherein the plurality of transistors further comprises a fifth transistor (Q5) and a sixth transistor (Q6), the fifth transistor (Q5) and the sixth transistor (Q6) being included in the second feedback path, arranged such that: the third terminal of the third transistor (Q3) is coupled to a first terminal of the fifth transistor (Q5), a third terminal of the fifth transistor (Q5) is coupled to a third terminal of the sixth transistor (Q6), a second terminal of the sixth transistor (Q6) is coupled to a first terminal of the fourth transistor (Q4), and the first terminal of the third transistor (Q3) is coupled to each of the third terminal of the fifth transistor (Q5) and the third terminal of the sixth transistor (Q6).

12. The electronic device of claim 11, wherein the first terminal of the sixth transistor (Q6) is coupled to a reference voltage.

13. The electronic device of claim 11 or 12, wherein the second terminal of the sixth transistor (Q6) is coupled to a bias current.

Images