A power module and a method for calculating the error between its pin voltage and chip voltage

Abstract

This invention provides a power module and a method for calculating the error between its pin voltage and chip voltage. Based on finite element simulation, the method calculates the self-inductance and mutual inductance of the parasitic inductance of each module segment. Specifically, the parasitic inductance of the upper and lower bridge commutation circuits is calculated separately, followed by the mutual inductance between the pin circuit and the chip commutation circuit. Finally, the measurement error between the power module pin voltage and the actual chip voltage is calculated based on the current change rate. This measurement error can accurately assess the difference between the measured pin value during shutdown and the actual voltage across the chip, improving the selection accuracy of the power module's drive resistors and preventing over-design of the module and the electric drive system.

Description

Technical Field

[0001] The present invention relates to the technical field of power modules, and in particular to a power module and a method for calculating the error between a pin voltage and a chip voltage thereof. Background Art

[0002] See attached Figure 1 、 3 Due to the voltage difference caused by the parasitic inductance of the commutation circuit and the coupling inductance between the measurement pin and the power circuit, the pin measured voltage is smaller than the actual voltage across the chip, which causes the RBSOA (reverse bias safe operating area) area of ​​the power module to be smaller than the RBSOA area of ​​the chip.

[0003] See attached Figure 2 、 3 Due to the different chip packaging forms, the distance between the measurement pin and the chip varies, and the distance is generally far. As a result, the chip-pin voltage difference cannot be evaluated using the same standard. If a direct measurement method is used, the module packaging structure will be damaged and online detection will be impossible. Summary of the Invention

[0004] In order to overcome the above technical deficiencies, the present invention aims to provide a power module that can theoretically calculate the error between the pin voltage and the chip voltage during the design phase, and a method for calculating the error between the pin voltage and the chip voltage.

[0005] The present invention discloses a method for calculating the error between the power module pin voltage measurement and the chip actual voltage measurement, which calculates the parasitic inductance L of the chip commutation circuit, including the drain parasitic inductance and the source parasitic inductance and the mutual inductance between the drain and the source; calculates the mutual inductance M between the pin circuit and the chip commutation circuit, including the drain mutual inductance and the source mutual inductance; obtains the current change rate dI / dt, calculates the difference Δx between the parasitic inductance L and the mutual inductance M, and calculates the difference Δx between the parasitic inductance L and the mutual inductance M according to the formula Gets the error between the pin voltage measurement and the actual chip voltage measurement.

[0006] Preferably, the error calculation method is used for a two-level power module; the two-level power module includes an upper bridge chip and a lower bridge chip;

[0007] The calculation of the parasitic inductance L of the chip commutation loop includes: calculating the upper bridge parasitic inductance of the chip commutation loop: L up =L upD +L upS +2M upD-upS +M upD-lowS +M upD-lowD +M upS-lowD +M upS-lowS ; Calculate the lower bridge parasitic inductance of the chip commutation circuit: L low =LlowD +L lowS +2M lowD-upS +M lowD-upS +M lowD-upD +M lowS-upD +M lowS-upS ; Where: D represents the chip drain, S represents the chip source, M a-b Represents the mutual inductance between a and b.

[0008] Preferably, the calculation of the mutual inductance M between the pin loop and the chip commutation loop includes:

[0009] Calculate the mutual inductance between the drain pin loop of the upper bridge and the chip commutation loop:

[0010] M st-upD =M upDT-upD +M upDT-upS +M upDT-lowD +M upDT-lowS

[0011] Calculate the mutual inductance between the upper bridge source pin loop and the chip commutation loop:

[0012] M st-upS =M upST-upD +M upST-upS +M upST-lowD +M upST-lowS

[0013] Calculate the mutual inductance between the lower bridge drain pin loop and the chip commutation loop:

[0014] M st-lowD =M lowDT-lowD +M lowDT-lowS +M lowDT-upD +M lowDT-upS

[0015] Calculate the mutual inductance between the pin loop of the lower bridge source and the chip commutation loop:

[0016] M st-lowS =M lowST-lowD +M lowST-lowS +M lowST-upD +M lowST-upS ;

[0017] Among them: DT represents the pin drain, ST represents the pin source.

[0018] Preferably, the difference Δx between the parasitic inductance L and the mutual inductance M is calculated according to the formula The error between the pin voltage measurement and the actual chip voltage measurement includes: The error between the upper bridge pin voltage measurement and the actual chip voltage measurement is: The error between the voltage measurement of the upper bridge pin and the actual voltage measurement of the chip is: in Indicates the rate of change of upper bridge current; Indicates the rate of change of the lower bridge current.

[0019] Preferably, the current change rate dI / dt is 0-20A / ns.

[0020] Preferably, the current change rate dI / dt is 15-20A / ns.

[0021] The present invention discloses a power module, wherein a driving resistor of a corresponding resistance value of the power module is selected according to an error value between a pin voltage measurement and an actual chip voltage measurement calculated by the above-mentioned error calculation method.

[0022] Compared with the existing technology, the above technical solution has the following beneficial effects:

[0023] 1. Accurately evaluate the difference between the measured voltage at the shutdown transient pin and the actual voltage across the chip (i.e., the measurement error of the pin measurement). This measurement error is related to the resistance of the drive resistor. Therefore, the present invention can improve the selection accuracy of the power module drive resistor by calculating this measurement error, thereby avoiding over-design of the module and the electric drive system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A comparison of the RBSOA areas of the power module and the chip is shown;

[0025] Figure 2 This is a schematic diagram of the chip layout structure of the power module;

[0026] Figure 3 Schematic diagram of the measured voltage on the pin and the actual voltage across the chip;

[0027] Figure 4 This is a schematic diagram of the chip commutation circuit and measurement pin circuit of the dual-level power module provided by the present invention. DETAILED DESCRIPTION

[0028] The advantages of the present invention are further described below with reference to the accompanying drawings and specific embodiments.

[0029] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0030] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining."

[0032] In the description of the present invention, it should be understood that the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0033] In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal communication between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.

[0034] In the following description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention and have no specific meaning. Therefore, "module" and "component" can be used interchangeably.

[0035] Based on finite element simulation, the self-inductance and mutual inductance of the parasitic inductance of each module section are calculated; the parasitic inductance of the upper and lower bridge commutation circuits are calculated separately; the mutual inductance of the pin circuit and the commutation circuit is calculated; and the measurement error between the power module pin voltage and the actual chip voltage is calculated analytically.

[0036] See attached Figure 4The chip commutation circuit includes the DC+ terminal, DC- terminal, AC terminal and power semiconductor module, and the measurement pins are the Upper-D terminal near the DC+ terminal, the Lower-S terminal near the DC- terminal, and the Upper-S terminal and Lower-D terminal near the AC terminal. In the upper bridge chip commutation circuit, there is an inductor L upD , L upS In the commutation circuit of the lower bridge chip, there is an inductor L lowD , L lowS ; In the upper bridge measurement pin loop, there is an inductor L upDT , L upST In the commutation circuit of the lower bridge chip, there is an inductor L lowDT , L lowST .

[0037] The present invention provides a method for calculating the error between the power module pin voltage measurement and the chip actual voltage measurement. Based on finite element simulation, the parasitic inductance L of the chip commutation circuit is first calculated, and then the mutual inductance M between the pin circuit and the chip commutation circuit is calculated. Then, the "set" (current circuit) current change rate dI / dt is obtained, and the difference Δx between the parasitic inductance L and the mutual inductance M is calculated. According to the formula Gets the error between the pin voltage measurement and the actual chip voltage measurement.

[0038] It should be noted that the current change rate dI / dt here is related to many factors, such as load voltage, load current, temperature, drive resistance, etc. It should be understood that it can be considered to "set" (give) the circuit a current change rate dI / dt. Under the working conditions of the set current change rate dI / dt, the error between the pin voltage measurement and the actual chip voltage measurement is measured.

[0039] Preferably, the current change rate dI / dt is set to 0-20 A / ns. For some severe conditions, the current change rate dI / dt may also be set to 15-20 A / ns.

[0040] The following is a two-level power module (see Appendix) of the preferred embodiment of the present invention. Figure 4 ), calculate the error between the pin voltage measurement and the actual chip voltage measurement.

[0041] 1. First calculate the parasitic inductance L of the chip commutation circuit:

[0042] 1) Calculate the parasitic inductance of the upper bridge of the chip commutation circuit:

[0043] L up =L upD +L upS +2M upD-upS +M upD-lowS+M upD-lowD +M upS-lowD +M upS-lowS ;

[0044] 2) Calculate the lower bridge parasitic inductance of the chip commutation circuit:

[0045] L low =L lowD +L lowS +2M lowD-upS +M lowD-upS +M lowD-upD +M lowS-upD +M lowS-upS .

[0046] Where: D represents the chip drain, S represents the chip source, M a-b Represents the mutual inductance between a and b.

[0047] 2. Calculate the mutual inductance M between the pin loop and the chip commutation loop:

[0048] 1) Calculate the mutual inductance between the drain pin loop of the upper bridge and the chip commutation loop:

[0049] M st-upD =M upDT-upD +M upDT-upS +M upDT-lowD +M upDT-lowS

[0050] 2) Calculate the mutual inductance between the upper bridge source pin loop and the chip commutation loop:

[0051] M st-upS =M upST-upD +M upST-upS +M upST-lowD +M upST-lowS

[0052] 3) Calculate the mutual inductance between the lower bridge drain pin loop and the chip commutation loop:

[0053] M st-lowD =M lowDT-lowD +M lowDT-lowS +M lowDT-upD +M lowDT-upS

[0054] 4) Calculate the mutual inductance between the lower bridge source pin loop and the chip commutation loop:

[0055] M st-lowS =M lowST-lowD +M lowST-lowS +M lowST-upD +M lowST-upS .

[0056] Among them: DT represents the pin drain, ST represents the pin source.

[0057] 3. Calculate the error between the pin voltage measurement and the actual chip voltage measurement:

[0058] 1) The error between the voltage measurement of the upper bridge pin and the actual voltage measurement of the chip is:

[0059]

[0060] 2) The error between the voltage measurement of the upper bridge pin and the actual voltage measurement of the chip is:

[0061]

[0062] in Indicates the rate of change of upper bridge current; Indicates the rate of change of the lower bridge current.

[0063] It should be noted that although the preferred embodiment of the present invention is directed to a two-level power module, it can also be applied to a three-level or multi-level power module. For a three-level or multi-level power module, the commutation circuit schematic diagram is different from Figure 4 However, the calculation principles of parasitic inductance and mutual inductance are the same, so the error calculation between the pin voltage measurement and the actual chip voltage measurement can also be directly applied.

[0064] The present invention discloses a power module. The driving resistor of the power module with the corresponding resistance value is selected according to the error value between the pin voltage measurement and the actual chip voltage measurement calculated by the above-mentioned error calculation method. This can improve the selection accuracy of the driving resistor of the power module and avoid over-design of the module and the electric drive system.

[0065] It should be noted that the embodiments of the present invention have better practicability and do not impose any form of limitation on the present invention. Any technician familiar with the field may use the technical content disclosed above to change or modify it into an equivalent effective embodiment. However, any modification or equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for calculating the error between the power module pin voltage measurement and the chip actual voltage measurement, wherein the chip is a power module chip, the chip actual voltage is the chip actual shutdown voltage, and the pin is near the DC+ terminal. Terminals, near the DC-terminal Terminals, and those near the AC terminal Terminals and Terminal, pin voltage is the pin measurement shutdown voltage, characterized in that, Calculate the parasitic inductance of the chip commutation circuit , including drain parasitic inductance and source parasitic inductance as well as the mutual inductance between drain and source; Calculate the mutual inductance between the pin loop and the chip commutation loop , including drain mutual inductance and source mutual inductance; Get the current change rate , calculate the parasitic inductance Mutual Induction The difference between , according to the formula Gets the error between the pin voltage measurement and the actual chip voltage measurement.

2. The error calculation method according to claim 1, characterized in that: The calculated parasitic inductance Mutual Induction The difference between , according to the formula The error between the pin voltage measurement and the actual chip voltage measurement includes: The error between the upper bridge pin voltage measurement and the actual chip voltage measurement is: The error between the voltage measurement of the upper bridge pin and the actual voltage measurement of the chip is: ； in Indicates the rate of change of upper bridge current; Indicates the rate of change of the lower bridge current.

3. The error calculation method according to claim 1, characterized in that: Current change rate The value range is 0-20A / ns.

4. The error calculation method according to claim 3, characterized in that: Current change rate The value is 15-20A / ns.

5. A power module, characterized in that: The driving resistor of the power module with the corresponding resistance value is selected according to the error value between the pin voltage measurement and the actual chip voltage measurement calculated by the error calculation method according to any one of claims 1 to 4.

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