Display panel, driving circuit and method thereof, and display device

Abstract

The display panel and the driving circuit, the driving method and the display device are provided, wherein the driving circuit comprises a power management integrated circuit, a timing controller and a control circuit, a fault signal output interface of the power management integrated circuit and a general signal input / output interface of the timing controller are connected to the control circuit, and a control output end of the control circuit is connected to the power management integrated circuit; the power management integrated circuit is configured to send a first feedback signal to the control circuit according to a working state of the power management integrated circuit; the timing controller is configured to send a second feedback signal to the control circuit according to a working state of the timing controller; and the control circuit is configured to restart the power management integrated circuit when detecting that the working state of the power management integrated circuit and / or the timing controller is abnormal based on the first feedback signal and the second feedback signal. The driving circuit can detect and repair display abnormalities caused by the timing controller being unresponsive.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and its driving circuit, driving method and display device. Background Technology

[0002] Display products may fail to display properly for various reasons during actual use. Currently, the common solution for display malfunctions is manual inspection or repair. However, manual repair cannot detect and resolve the problem immediately, leading to a lower yield rate for the product and impacting customer satisfaction. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a display panel and its driving circuit, driving method and display device, which can detect and repair display abnormalities caused by the timing controller TCON being unresponsive in the first instance.

[0004] In a first aspect, this disclosure provides the following technical solution through an embodiment:

[0005] A driving circuit for a display panel includes a power management integrated circuit, a timing controller, and a control circuit. The fault signal output interface of the power management integrated circuit and the general signal input / output interface of the timing controller are connected to the control circuit, and the control output terminal of the control circuit is connected to the power management integrated circuit.

[0006] The power management integrated circuit is configured to send a first feedback signal to the control circuit according to the operating state of the power management integrated circuit;

[0007] The timing controller is configured to send a second feedback signal to the control circuit according to the operating state of the timing controller;

[0008] The control circuit is configured to restart the power management integrated circuit when it detects that the operating state of the power management integrated circuit and / or the timing controller is abnormal, based on the first feedback signal and the second feedback signal.

[0009] In some embodiments, the first feedback signal includes a first high-level signal or a first low-level signal; the first high-level signal is used to indicate that the power management integrated circuit is operating normally, and the first low-level signal is used to indicate that the power management integrated circuit is operating abnormally.

[0010] The second feedback signal includes a second high-level signal or a second low-level signal; the second high-level signal is used to indicate that the timing controller is operating normally, and the second low-level signal is used to indicate that the timing controller is operating abnormally.

[0011] The control circuit is configured to restart the power management integrated circuit when the first low-level signal and / or the second low-level signal are detected.

[0012] In some embodiments, the control circuit includes an AND circuit and a controller, wherein a first input terminal of the AND circuit is connected to the fault signal output interface, a second input terminal is connected to the general signal input / output interface, the output terminal of the AND circuit is connected to the controller, and the control output terminal of the controller is connected to the power management integrated circuit.

[0013] The circuit is configured to output a third low-level signal upon receiving the first low-level signal and / or the second low-level signal;

[0014] The controller is configured to restart the power management integrated circuit when the third low-level signal is detected.

[0015] In some embodiments, the controller is configured to detect the third low-level signal based on a set time interval, the set time interval not exceeding 60 seconds.

[0016] In some embodiments, the first feedback signal includes a first high-level signal or a first low-level signal; the first high-level signal is used to indicate that the power management integrated circuit is in an abnormal operating state, and the first low-level signal is used to indicate that the power management integrated circuit is in a normal operating state.

[0017] The second feedback signal includes a second high-level signal or a second low-level signal; the second high-level signal is used to indicate that the timing controller is in an abnormal operating state, and the second low-level signal is used to indicate that the timing controller is in a normal operating state.

[0018] The control circuit is configured to restart the power management integrated circuit based on the first high-level signal and / or the second high-level signal.

[0019] In some embodiments, the control circuit includes an OR circuit and a controller, wherein a first input terminal of the OR circuit is connected to the fault signal output interface, a second input terminal is connected to the general signal input / output interface, an output terminal of the OR circuit is connected to the controller, and a control output terminal of the controller is connected to the power management integrated circuit.

[0020] The OR circuit is configured to output a third high-level signal upon receiving the first high-level signal and / or the second high-level signal;

[0021] The controller is configured to restart the power management integrated circuit when the third high-level signal is detected.

[0022] In some embodiments, the controller is a graphics generator or a display controller.

[0023] In some embodiments, the control circuit includes a counter for acquiring the number of times the control circuit restarts the power management integrated circuit;

[0024] The control circuit is configured as follows:

[0025] After the power management integrated circuit is restarted N times consecutively, if the working state of the power management integrated circuit and / or the timing controller is detected to be abnormal based on the first feedback signal and the second feedback signal, the restart of the power management integrated circuit is prohibited and a warning message is generated; the value of N ranges from 2 to 5.

[0026] Secondly, based on the same inventive concept, this disclosure provides the following technical solution through an embodiment:

[0027] A method for driving a display panel, comprising:

[0028] Acquire a first feedback signal sent by the power management integrated circuit according to the working state of the power management integrated circuit, and acquire a second feedback signal sent by the timing controller according to the working state of the timing controller;

[0029] Based on the first feedback signal and the second feedback signal, when the operating state of the power management integrated circuit and / or the timing controller is detected to be abnormal, the power management integrated circuit is restarted.

[0030] Thirdly, based on the same inventive concept, this disclosure provides the following technical solution through an embodiment:

[0031] A display panel including any of the driving circuits provided in the first aspect embodiment.

[0032] Fourthly, based on the same inventive concept, this disclosure provides the following technical solution through an embodiment:

[0033] A display device includes a display panel provided in a third aspect embodiment.

[0034] Through one or more technical solutions disclosed herein, this disclosure has the following beneficial effects or advantages:

[0035] The driving circuit of the display panel provided in this disclosure can detect whether the working state of the power management integrated circuit and / or the timing controller is abnormal by controlling the circuit based on the first feedback signal of the power management integrated circuit and the second feedback signal of the timing controller. If either of them is in an abnormal state, the power management integrated circuit is restarted, which in turn causes the timing controller to restart as well. In this way, it is possible to detect whether the display product has a power management integrated circuit or timing controller malfunction in the first instance, and then eliminate the display abnormality caused by the fault by controlling the power management integrated circuit to restart, thereby reducing the failure rate of the display product when used by customers and improving the market competitiveness of the display product.

[0036] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0037] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0038] In the attached diagram:

[0039] Figure 1 A schematic diagram of a drive circuit provided according to an embodiment of the present disclosure is shown;

[0040] Figure 2 A schematic diagram of a drive circuit including an AND circuit is shown according to an embodiment of the present disclosure;

[0041] Figure 3 A schematic diagram of a drive circuit including an OR circuit is shown according to an embodiment of the present disclosure;

[0042] Figure 4 A schematic flowchart of a driving method provided according to an embodiment of this disclosure is shown;

[0043] Figure 5 A schematic diagram of a display device provided according to an embodiment of the present disclosure is shown. Detailed Implementation

[0044] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0045] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0046] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0047] In the context of this disclosure, unless otherwise specified, the light-emitting side of the display panel is referred to as the "top side" or "upper side," and its opposite side as the "bottom side" or "lower side," to facilitate the description of relative directions. Accordingly, the direction from the bottom side to the top side is the thickness direction of the display panel, and the direction perpendicular to the thickness direction is the "planar direction" or "extension direction" of the display panel. It should be understood that these directions are relative directions rather than absolute directions.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0049] Research indicates that for medium to large-sized displays, such as those no smaller than 10 inches, the driving circuitry involves a timing controller IC (TCON), a power management IC (PMIC), and a source driver IC. Taking OLED (Organic Light-Emitting Diode) displays as an example, the PMIC primarily generates voltage signals such as Vcore 0.9V, VDD 1.8V, VGMP, VGSP, VGH, VGL, VINT1, VINT2, and VINT3. Vcore 0.9V and VDD 1.8V are the startup voltages for the TCON IC. After being enabled by the VCC 3.3V signal output from the pattern generator (PG), the PMIC normally generates Vcore 0.9V, VDD 1.8V, and other voltage signals. Once the TCON receives the Vcore 0.9V and VDD 1.8V voltage signals, it immediately begins normal operation. However, in actual use, there are occasional instances where the PMIC outputs Vcore 0.9V and VDD 1.8V signals normally, but the TCON fails to function properly. Since the TCON is the most complex and difficult-to-implement integrated circuit IC in the entire driver circuit module, the display device will be unable to display anything when the TCON does not respond and has no normal output.

[0050] Currently, there are no other signal connections between the PMIC and TCON besides Vcore 0.9V, VDD 1.8V, and I2C. Therefore, it is impossible to determine whether the TCON is working properly, nor can this situation be repaired. One possible solution is to notify technicians to determine if the TCON is malfunctioning when the display product exhibits a display abnormality. If so, the PMIC is powered off and restarted, thereby restarting the TCON. However, this solution cannot immediately detect and resolve display problems caused by TCON malfunctions, and to some extent exposes product defects to customers, reducing customer satisfaction.

[0051] In order to resolve the display product malfunction caused by TCON abnormality as soon as possible, firstly, in an optional embodiment, please refer to... Figure 1 A driving circuit for a display panel is provided, including: a power management integrated circuit (PMIC), a timing controller (TCON), and a control circuit 100. The fault signal output interface of the power management integrated circuit (PMIC) and the general signal input / output interface of the timing controller (TCON) are connected to the control circuit 100, and the control output terminal of the control circuit 100 is connected to the power management integrated circuit (PMIC).

[0052] The power management integrated circuit (PMIC) is configured to send a first feedback signal to the control circuit 100 based on the operating state of the PMIC; the timing controller (TCON) is configured to send a second feedback signal to the control circuit 100 based on the operating state of the timing controller (TCON); and the control circuit 100 is configured to restart the power management integrated circuit (PMIC) when it detects that the operating state of the power management integrated circuit (PMIC) and / or the timing controller (TCON) is abnormal, based on the first and second feedback signals.

[0053] Specifically, the first feedback signal indicates whether the power management integrated circuit (PMIC) is in a normal or abnormal state. A normal state means that the PMIC can work normally, that is, it can output various voltage signals normally. An abnormal state means that the PMIC cannot continue to work or is unresponsive, that is, it cannot output various voltage signals normally.

[0054] The second feedback signal indicates whether the timing controller TCON is in a normal or abnormal state. Similar to the PMIC, a normal state means that the TCON can work normally and output various timing control signals, such as STV, OEV, CPV, STH, CPH, OEH, PLC, etc. An abnormal state means that the TCON cannot continue to work or is in an unresponsive state, unable to output various timing control signals.

[0055] In addition, PMIC and TCON can be configured according to actual needs to output the first and second feedback signals indicating abnormal operation only when a set type of fault condition occurs, such as a fault that affects the display effect. When a fault condition that does not belong to the set type occurs, the first and second feedback signals indicating normal operation will be output.

[0056] In this embodiment, the fault signal output interface of the PMIC is the fault signal port built into the PMIC circuit board, which can be used to output fault signals. The general signal input / output interface of the TCON is the GPIO (General Purpose Input / Output) interface of the TCON circuit board. Any available GPIO port on the TCON circuit board can be selected to connect to the control circuit 100, such as GPIO port A, GPIO port B, etc.

[0057] Therefore, based on the first and second feedback signals, it can be determined whether the PMIC and TCON in the display panel are abnormal or in a non-responsive state. If the PMIC is in an abnormal state, it cannot output the Vcore0.9V and VDD1.8V signals normally, causing the TCON to enter a non-responsive state, resulting in display panel abnormalities. If the PMIC is in a normal state and can output the Vcore0.9V and VDD1.8V signals normally, but the TCON is in a non-responsive abnormal state, it will also cause display panel abnormalities. Therefore, the control circuit 100 is configured to restart the PMIC when either the first or second feedback signal is detected as an abnormal signal. The reason for restarting the PMIC is that the PMIC also synchronously restarts the TCON when it restarts, thus resolving display abnormalities caused by PMIC or TCON non-responsiveness.

[0058] Therefore, the driving circuit of the display panel provided in this embodiment detects or determines whether the working state of the PMIC and / or TCON is abnormal based on the first feedback signal of the PMIC and the second feedback signal of the TCON by the control circuit 100. If either of them is in an abnormal state, the PMIC is controlled to restart, which in turn causes the TCON to restart as well. In this way, it is possible to detect whether the display product has a PMIC or TCON malfunction in the first instance, and then eliminate the display abnormality caused by the fault by controlling the PMIC to restart, thereby reducing the failure rate of the display product when used by customers and improving the market competitiveness of the display product.

[0059] The information content of the first and second feedback signals may include judgment information indicating whether the corresponding circuit's operating state is normal or abnormal, or it may include specific fault information of the corresponding circuit. Since the operating states of the PMIC and TCON only include Boolean values ​​of "normal" and "abnormal," in some embodiments, the first feedback signal includes a first high-level signal or a first low-level signal; the first high-level signal indicates that the power management integrated circuit (PMIC) is operating normally, and the first low-level signal indicates that the PMIC is operating abnormally; the second feedback signal includes a second high-level signal or a second low-level signal; the second high-level signal indicates that the timing controller (TCON) is operating normally, and the second low-level signal indicates that the TCON is operating abnormally; the control circuit 100 is configured to restart the power management integrated circuit (PMIC) when the first low-level signal and / or the second low-level signal is detected.

[0060] In other words, the control circuit 100 can logically determine whether there is a low-level signal in the first feedback signal and the second feedback signal. If so, it can determine that there is an abnormality in the current PMIC or TCON, and then repair the display product abnormality caused by the TCON abnormality or no response by restarting the PMIC.

[0061] For an alternative method, please refer to Figure 2 The control circuit 100 includes an interconnect circuit 120 and a controller 110. The first input terminal of the interconnect circuit 120 is connected to a fault signal output interface, and the second input terminal is connected to a general signal input / output interface. The output terminal of the interconnect circuit 120 is connected to the controller 110, and the control output terminal of the controller 110 is connected to a power management integrated circuit (PMIC). The interconnect circuit 120 is configured to output a third low-level signal when it receives a first low-level signal and / or a second low-level signal.

[0062] Specifically, considering that the first and second feedback signals are "high-level signals" and "low-level signals" respectively, possessing Boolean properties, an AND circuit 120 is set as a judge in the control circuit 100. The AND circuit 120 has at least two inputs and one output. Its characteristic is that when all inputs are simultaneously high (logic 1), the output is high; otherwise, the output is low (logic 0). Specifically, this involves the following three cases:

[0063] 1) When the PMIC is not working properly due to protection, i.e. it is in an abnormal state, the Fault signal output by the fault signal output interface is low level. The TCON is also not working properly due to the PMIC not working properly, and is in an abnormal state. The GPIO signal output by its general signal input / output interface is also low level. At this time, the circuit 120 outputs a third low level signal.

[0064] 2) When the PMIC is working normally, the Fault signal output by the fault signal output interface is high, but the TCON is not working normally, and the GPIO signal output by its general signal input / output interface is low. At this time, the circuit 120 outputs a third low-level signal.

[0065] 3) When the PMIC is working normally, the output Fault signal is high level. When the TCON is also working normally, the output GPIO signal is high level. At this time, the circuit 120 outputs the third high level signal.

[0066] Therefore, controller 110 is configured to restart the PMIC upon detecting a third low-level signal to resolve display abnormalities caused by a PMIC or TCON malfunction. The PMIC can be restarted by re-sending the VCC 3.3V signal from controller 110 to the PMIC.

[0067] In some embodiments, the first high-level signal can also be used to indicate that the power management integrated circuit (PMIC) is in an abnormal operating state, and the first low-level signal can be used to indicate that the PMIC is in a normal operating state; the second high-level signal can be used to indicate that the timing controller (TCON) is in an abnormal operating state, and the second low-level signal can be used to indicate that the timing controller (TCON) is in a normal operating state; the control circuit 100 is configured to restart the power management integrated circuit (PMIC) according to the first high-level signal and / or the second high-level signal.

[0068] In other words, the control circuit 100 can logically determine whether there is a high-level signal in the first feedback signal and the second feedback signal. If so, it can determine that there is an abnormality in the current PMIC or TCON, and then fix the display product abnormality caused by the TCON abnormality or no response by restarting the PMIC.

[0069] For an alternative method, please refer to Figure 3 The control circuit 100 includes either circuit 130 and controller 110, or circuit 130 has a first input terminal connected to a fault signal output interface and a second input terminal connected to a general signal input / output interface, or circuit 130 has an output terminal connected to controller 110 and controller 110 has a control output terminal connected to a power management integrated circuit (PMIC); or circuit 130 is configured to output a third high-level signal when it receives a first high-level signal and / or a second high-level signal.

[0070] Alternatively, the control logic of circuit 130 is such that the output signal is high (logic "1") as long as there is at least one high level (logic "1") in the input signal; the output signal is low (logic "0") only when all input signals are low (logic "0"). Specifically, this involves the following three cases:

[0071] 1) When the PMIC is not working properly due to protection, i.e. it is in an abnormal state, the Fault signal output by the fault signal output interface is high level. The TCON is also not working properly due to the PMIC not working properly, and is in an abnormal state. The GPIO signal output by its general signal input / output interface is also high level. At this time, circuit 130 outputs a third high level signal.

[0072] 2) When the PMIC is working normally, the Fault signal output by the fault signal output interface is low, but the TCON is not working normally, and the GPIO signal output by its general signal input / output interface is high. At this time, circuit 130 outputs a third high-level signal.

[0073] 3) When the PMIC is working normally, the output Fault signal is low level. When the TCON is also working normally, the output GPIO signal is low level. At this time, circuit 130 outputs a third low level signal.

[0074] Therefore, the controller 110 is configured to restart the power management integrated circuit PMIC when a third high-level signal is detected, in order to resolve the display abnormality problem caused by the PMIC or TCON being unresponsive.

[0075] In some alternative embodiments, the first feedback signal may further include a fault code of the PMIC, the second feedback signal may further include a fault code of the TCON, and the control circuit 100 may be configured to determine that the PMIC is malfunctioning and restart the PMIC when it receives either a fault code of the PMIC or the TCON.

[0076] In the above embodiments, the controller 110 may be a pattern generator (PG) or a display controller. The display controller refers to a controller or integrated chip mounted on the display motherboard.

[0077] In the above embodiments, the controller 110 can be configured to detect either a third low-level signal output by the circuit 120 or a third high-level signal output by the circuit 130 based on a set time interval. The set time interval should not be too long, otherwise it will reduce the speed of the controller 110's self-test and prevent the immediate resolution of display abnormalities. Optionally, the set time interval should not exceed 60 seconds.

[0078] In some embodiments, the control circuit 100 includes a counter for acquiring the number of times the control circuit 100 restarts the power management integrated circuit (PMIC). The control circuit 100 is configured to: after N consecutive restarts of the power management integrated circuit (PMIC), if the operating state of the power management integrated circuit (PMIC) and / or the timing controller (TCON) is detected to be abnormal based on a first feedback signal and a second feedback signal, then the restart of the power management integrated circuit (PMIC) is prohibited and a warning message is generated. The value of N ranges from 2 to 5.

[0079] Specifically, after multiple restarts, if the power management integrated circuit (PMIC) and / or the timing controller (TCON) are malfunctioning—for example, if controller 110 detects that circuit 120 is still outputting a low-level signal, or circuit 130 is still outputting a high-level signal—it indicates that restarting the PMIC cannot resolve the current display issue, or that the current display malfunction is caused by other reasons. In this case, repeated PMIC restarts should be prohibited to avoid affecting the user experience, and a corresponding warning signal should be generated to alert the user. The preferred value for N is 3, meaning that restarting the PMIC should be prohibited after three consecutive restarts. The warning information can be preset image or sound warning information in the display device; no specific restrictions are placed on it here.

[0080] Based on the same inventive concept as the first aspect of the embodiment, in the second aspect, in another optional embodiment, please refer to... Figure 4 A method for driving a display panel is provided, including:

[0081] S401: Obtain the first feedback signal sent by the power management integrated circuit according to the working state of the power management integrated circuit, and obtain the second feedback signal sent by the timing controller according to the working state of the timing controller;

[0082] S402: Based on the first feedback signal and the second feedback signal, when the operating state of the power management integrated circuit and / or the timing controller is detected to be abnormal, the power management integrated circuit is restarted.

[0083] Specifically, based on the first and second feedback signals, it can be determined whether the working state of the power management integrated circuit and / or the timing controller is abnormal. If either of them is in an abnormal state, the power management integrated circuit is restarted, which in turn causes the timing controller to restart as well. In this way, it is possible to detect whether the power management integrated circuit or the timing controller of the display product is malfunctioning in the first instance, and to eliminate the display abnormality caused by the fault by controlling the restart of the power management integrated circuit. This reduces the failure rate of the display product when used by customers and improves the market competitiveness of the display product.

[0084] In some embodiments, the first feedback signal includes a first high-level signal or a first low-level signal; the first high-level signal is used to indicate that the power management integrated circuit is operating normally, and the first low-level signal is used to indicate that the power management integrated circuit is operating abnormally; the second feedback signal includes a second high-level signal or a second low-level signal; the second high-level signal is used to indicate that the timing controller is operating normally, and the second low-level signal is used to indicate that the timing controller is operating abnormally.

[0085] Based on the first and second feedback signals, when an abnormal operating state of the power management integrated circuit and / or timing controller is detected, the power management integrated circuit is restarted, including:

[0086] The power management integrated circuit is restarted upon detection of a first low-level signal and / or a second low-level signal.

[0087] In some embodiments, restarting the power management integrated circuit upon detecting a first low-level signal and / or a second low-level signal includes:

[0088] Upon receiving a first low-level signal and / or a second low-level signal, a third low-level signal is generated; upon detecting the third low-level signal, the power management integrated circuit is restarted.

[0089] In some embodiments, the first feedback signal includes a first high-level signal or a first low-level signal; the first high-level signal is used to indicate that the power management integrated circuit is in an abnormal operating state, and the first low-level signal is used to indicate that the power management integrated circuit is in a normal operating state; the second feedback signal includes a second high-level signal or a second low-level signal; the second high-level signal is used to indicate that the timing controller is in an abnormal operating state, and the second low-level signal is used to indicate that the timing controller is in a normal operating state.

[0090] Based on the first and second feedback signals, when an abnormal operating state of the power management integrated circuit and / or timing controller is detected, the power management integrated circuit is restarted, including:

[0091] Restart the power management integrated circuit based on the first high-level signal and / or the second high-level signal.

[0092] In some embodiments, restarting the power management integrated circuit based on a first high-level signal and / or a second high-level signal includes:

[0093] Upon receiving a first high-level signal and / or a second high-level signal, a third high-level signal is generated; upon detecting the third high-level signal, the power management integrated circuit is restarted.

[0094] In some embodiments, the control method further includes:

[0095] After N consecutive restarts of the power management integrated circuit, if the working state of the power management integrated circuit and / or the timing controller is detected to be abnormal based on the first feedback signal and the second feedback signal, the restart of the power management integrated circuit is prohibited and a warning message is generated; the value of N ranges from 2 to 5.

[0096] Thirdly, based on the same inventive concept, in another optional embodiment, a display panel is provided, including any of the driving circuits provided in the first aspect embodiment. The driving circuit is formed in the wiring area or border area of ​​the array substrate. The type of driving panel can be medium to large size, such as LED panels, OLED panels, QLED (Quantum Dot Light Emitting Diodes) panels, MLED (including Mini LED and Micro LED) panels, etc., which are not less than 10 inches, or medium to large size LCD panels, as long as the driving circuit includes independent PMIC circuit boards and TCON circuit boards.

[0097] Fourthly, based on the same inventive concept, in another alternative embodiment, please refer to... Figure 5 A display device is provided, including a display panel provided in a third aspect embodiment.

[0098] The technical effects of the third and fourth aspect embodiments are the same as those of the first aspect embodiment, and the relevant content in the first aspect embodiment can be referred to.

[0099] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0100] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A driving circuit for a display panel, characterized in that, It includes a power management integrated circuit, a timing controller, and a control circuit. The fault signal output interface of the power management integrated circuit and the general signal input / output interface of the timing controller are connected to the control circuit, and the control output terminal of the control circuit is connected to the power management integrated circuit. The power management integrated circuit is configured to send a first feedback signal to the control circuit according to the operating state of the power management integrated circuit; The timing controller is configured to send a second feedback signal to the control circuit according to the operating state of the timing controller; The control circuit is configured to restart the power management integrated circuit based on the first feedback signal and the second feedback signal when it detects that the operating states of both the power management integrated circuit and the timing controller are abnormal, or when the operating state of the power management integrated circuit is normal and the operating state of the timing controller is abnormal. The first feedback signal includes a fault code of the power management integrated circuit, and the second feedback signal includes a fault code of the timing controller; the control circuit is configured to determine, upon receiving either the fault code of the power management integrated circuit or the fault code of the timing controller, that the operating state of the power management integrated circuit and the timing controller is abnormal, or that the operating state of the power management integrated circuit is normal and the operating state of the timing controller is abnormal.

2. The driving circuit as described in claim 1, characterized in that, Alternatively, the first feedback signal may include a first high-level signal or a first low-level signal; the first high-level signal is used to indicate that the power management integrated circuit is operating normally, and the first low-level signal is used to indicate that the power management integrated circuit is operating abnormally. The second feedback signal includes a second high-level signal or a second low-level signal; the second high-level signal is used to indicate that the timing controller is operating normally, and the second low-level signal is used to indicate that the timing controller is operating abnormally; the control circuit is configured to restart the power management integrated circuit when the first low-level signal and the second low-level signal are detected, or when the first high-level signal and the second low-level signal are detected.

3. The driving circuit as described in claim 2, characterized in that, The control circuit includes an AND circuit and a controller. The first input terminal of the AND circuit is connected to the fault signal output interface, the second input terminal is connected to the general signal input / output interface, the output terminal of the AND circuit is connected to the controller, and the control output terminal of the controller is connected to the power management integrated circuit. The circuit is configured to output a third low-level signal when it receives the first low-level signal and the second low-level signal or when it receives the first high-level signal and the second low-level signal; The controller is configured to restart the power management integrated circuit when the third low-level signal is detected.

4. The driving circuit as described in claim 3, characterized in that, The controller is configured to detect the third low-level signal based on a set time interval, the set time interval not exceeding 60 seconds.

5. The driving circuit as described in claim 1, characterized in that, Alternatively, the first feedback signal may include a first high-level signal or a first low-level signal; the first high-level signal is used to indicate that the power management integrated circuit is in an abnormal operating state, and the first low-level signal is used to indicate that the power management integrated circuit is in a normal operating state. The second feedback signal includes a second high-level signal or a second low-level signal; the second high-level signal is used to indicate that the timing controller is in an abnormal operating state, and the second low-level signal is used to indicate that the timing controller is in a normal operating state. The control circuit is configured to restart the power management integrated circuit based on the first high-level signal and the second high-level signal, or the first low-level signal and the second high-level signal.

6. The driving circuit as described in claim 5, characterized in that, The control circuit includes an OR circuit and a controller. The first input terminal of the OR circuit is connected to the fault signal output interface, the second input terminal is connected to the general signal input / output interface, the output terminal of the OR circuit is connected to the controller, and the control output terminal of the controller is connected to the power management integrated circuit. The OR circuit is configured to output a third high-level signal when it receives the first high-level signal and the second high-level signal, or the first low-level signal and the second high-level signal; The controller is configured to restart the power management integrated circuit when the third high-level signal is detected.

7. The driving circuit as described in claim 3 or 6, characterized in that, The controller is a graphics generator or a display controller.

8. The driving circuit as described in claim 1, characterized in that, The control circuit includes a counter, which is used to obtain the number of times the control circuit restarts the power management integrated circuit; The control circuit is configured as follows: After the power management integrated circuit is restarted N times consecutively, if the operating state of the power management integrated circuit and the timing controller is detected to be abnormal based on the first feedback signal and the second feedback signal, or the operating state of the power management integrated circuit is normal and the operating state of the timing controller is abnormal, then restarting the power management integrated circuit is prohibited and a warning message is generated; the value of N is in the range of 2 to 5.

9. A driving method for a display panel, characterized in that, include: Acquire a first feedback signal sent by the power management integrated circuit according to the working state of the power management integrated circuit, and acquire a second feedback signal sent by the timing controller according to the working state of the timing controller; Based on the first feedback signal and the second feedback signal, when it is detected that the working states of the power management integrated circuit and the timing controller are both abnormal, or when the working state of the power management integrated circuit is normal and the working state of the timing controller is abnormal, the power management integrated circuit is restarted. The first feedback signal includes a fault code of the power management integrated circuit, and the second feedback signal includes a fault code of the timing controller; the method further includes: when receiving any one of the fault codes of the power management integrated circuit and the timing controller, determining that the operating state of the power management integrated circuit and the timing controller is abnormal, or that the operating state of the power management integrated circuit is normal and the operating state of the timing controller is abnormal.

10. A display panel, characterized in that, Includes the driving circuit as described in any one of claims 1 to 8.

11. A display device, characterized in that, Includes the display panel as described in claim 10.

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