A high energy-efficient in-memory computing circuit and method based on approximate computing

Abstract

The application provides a high-energy-efficiency SRAM in-memory computing circuit based on approximate calculation, comprising: an SRAM in-memory computing array, which comprises a plurality of SRAM units arranged in an array, each SRAM unit internally integrating a number of two-input NOR gates which can be adjusted; in the SRAM in-memory computing array, all partial products required by multi-bit multiplication calculation can be completed in one cycle; an approximate multiplier, a plurality of SRAM units arranged in a row are equipped with an approximate multiplier; a near-memory adder, the outputs of all rows of approximate multipliers are taken as the inputs of a near-memory adder tree circuit; all partial products pass through the approximate multiplier and the near-memory adder, and the output is a multiply-accumulate result. The application is based on the fault tolerance of neural networks, and through the fusion of approximate calculation and in-memory calculation, an approximate in-memory multiplier circuit with configurable precision is designed, the circuit complexity inside the multiplier is effectively reduced, the performance, energy efficiency and integration are greatly improved while meeting the precision requirements of neural networks.

Description

Technical Field

[0001] This invention relates to the field of SRAM in-memory computing, and more specifically, to a high-efficiency SRAM in-memory computing circuit and method based on approximate calculation. Background Technology

[0002] With the continuous development of artificial intelligence algorithms, neural networks are widely used in many fields, such as image recognition and natural language processing. To meet the ever-increasing application demands, the scale of neural networks is constantly expanding, requiring the storage of weights up to gigabytes in size. In the traditional von Neumann architecture, data storage units and computation units are separate. During computation, data is repeatedly moved between the two, resulting in significant power consumption and performance loss. In-memory computing technology integrates data processing functions into memory or places them in near-memory computing units, minimizing the overhead of data movement between memory and processing units, achieving high-efficiency, high-performance large-scale data processing. Currently, there are various in-memory computing design schemes based on different storage media in academia, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Non-volatile Memory. Among these different in-memory computing schemes, SRAM-based in-memory computing is considered the most promising circuit technology to be the first to enter industrialization because it can use the most advanced manufacturing processes and is naturally compatible with peripheral auxiliary computing circuits. Currently, there are three main methods for in-memory computing based on SRAM: bit serial, analog domain in-memory computing, and full-precision digital domain in-memory computing. Different circuit structures can be designed for different application scenarios and requirements.

[0003] When the bit-serial circuit structure performs an operation, it activates two columns in the array to be operated on. Based on the data values ​​stored in the array, the results of the "AND" and "OR" logic calculations of the two selected memory cells in each row are reflected in the voltage magnitudes of the calculation bit line and the inverted bit line, respectively. The two logic calculation results are then used to perform more complex logic calculations in the near-memory computing unit. The calculation results of the near-memory circuit unit are written back to the designated column of SRAM within the same cycle. In this computing mode, a highly configurable data processing paradigm can be achieved by configuring the external near-memory computing circuit. However, since only two columns of the array can be activated for calculation at a time, the data processing performance and energy efficiency are very limited. Therefore, this in-memory computing method is more suitable for scenarios with higher configuration requirements, such as CPUs, rather than dedicated high-performance, high-energy-efficiency scenarios.

[0004] The circuit structure for analog-domain in-memory computation can achieve highly parallel multiply-accumulate operations based on capacitive coupling or Kirchhoff's current law. The calculation result is reflected in the voltage of the computation bit line, and the result after passing through an analog-to-digital converter (ADC) is the final multiply-accumulate output. However, in this circuit implementation, the calculation result, expressed as an analog voltage, is affected by various factors such as process technology, power supply voltage, and temperature. Furthermore, the conversion accuracy of the ADC also significantly impacts the accuracy of the calculation result. Since these interference conditions are usually random, the overall accuracy of the calculation result is poorly controllable. In addition, the analog-domain calculation result relies on the ADC for analog-to-digital conversion, and the presence of the ADC significantly reduces the overall computational energy efficiency.

[0005] The circuitry for full-precision digital in-memory computation performs single-bit multiplication within a single cell, while adding an addition tree circuit near the memory to accumulate results from different rows. Digital in-memory computation inherently offers advantages in high performance and low power consumption, while eliminating the energy-intensive and area-intensive ADC circuitry found in analog in-memory computation. Therefore, this computational approach combines the high performance of analog in-memory computation with the high energy efficiency of digital computation. However, in this circuit, only a single-bit multiplication is performed in memory per cycle, and multiple input bits still rely on external shift and accumulation circuits, requiring further improvement in parallelism. Furthermore, neural network algorithms inherently possess excellent fault tolerance, and using full-precision computation in the circuit cannot fully leverage their energy efficiency advantages. Additionally, full-precision computation circuitry occupies a significant amount of cell area, substantially increasing chip manufacturing costs. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a high-efficiency SRAM in-memory calculation circuit and method based on approximate calculation.

[0007] According to one aspect of the present invention, a high-efficiency SRAM in-memory computing circuit based on approximate calculation is provided, comprising:

[0008] The SRAM in-memory computing array comprises multiple SRAM cells arranged in an array, each SRAM cell integrating an adjustable number of two-input NOR gates; within the SRAM in-memory computing array, all partial products required for multi-bit computation can be completed in one cycle;

[0009] An approximate multiplier is provided for a plurality of SRAM cells arranged in a row;

[0010] The nearest-store adder takes the outputs of all rows' approximate multipliers as inputs to the nearest-store adder tree circuit; all partial products pass through the approximate multipliers and the nearest-store adder to output the multiply-accumulate result.

[0011] Preferably, the SRAM in-memory computing array comprises:

[0012] A 6T SRAM storage unit, wherein the 6T SRAM storage unit is used to store data;

[0013] The 6T SRAM has eight two-input NOR gates, and the storage data node Q is connected to the first input port of the eight two-input NOR gates in a fan-out configuration. The eight two-input NOR gates and the 6T SRAM storage cell are connected in the layout as a basic storage and computing unit.

[0014] Eight input word lines are connected to the second input ports of the eight two-input NOR gates, respectively.

[0015] The storage and computing basic units are arranged in groups of eight to form a row, and are equipped with one of the approximate multiplication circuits;

[0016] All NOR gate outputs of the eight basic in-memory computing units serve as inputs to the in-memory approximate multiplication circuit.

[0017] The output of the in-memory approximate multiplication circuit is used as the input of the near-memory adder tree circuit.

[0018] The output of the near-store addition tree is used as the overall system output.

[0019] Preferably, in the SRAM in-memory computing array, adjusting the number of two input NOR gates connected to the 6T SRAM storage unit adjusts the calculation precision of the partial product, thereby enabling the system to output multiply-accumulate results with configurable precision.

[0020] Preferably, in the SRAM in-memory computing array, the number of NOR gates placed in adjacent basic computing units is different; the storage weight is positively correlated with the number of NOR gates connected to the SRAM unit of the bit.

[0021] Preferably, the approximate multiplier calculation process includes a half adder, a full adder, an exact 4:2 compressor, and an approximate 4:2 compressor.

[0022] Preferably, the low bits of the approximate multiplier are compressed using the approximate 4:2 compressor;

[0023] The high bits of the approximate multiplier are compressed using the precise 4:2 compressor.

[0024] The approximate multiplier uses different precision configurations when processing different layers of the neural network.

[0025] Preferably, the precise 4:2 compressor uses x1-x4 as input data, T inS is the input carry signal, and C and T are the output sum signals. out To output the carry signal;

[0026] The circuitry in the precise 4:2 compressor is composed of two full adders.

[0027] Preferably, the approximate 4:2 compressor has only x1-x4 as circuit inputs, eliminating carry input signals, and the output signal becomes a sum signal and a carry output signal.

[0028] Preferably, the 6T SRAM storage unit includes:

[0029] Six transistors are connected end-to-end to store a single bit of data;

[0030] Word lines, bit lines, and inverted bit lines are used to implement the SRAM's own access functions.

[0031] The two storage nodes are denoted as Q and QB, respectively.

[0032] When representing multi-bit data, multiple 6T SRAM memory units will be used;

[0033] According to a second aspect of the present invention, a high-performance SRAM in-memory computation method based on approximate calculation includes:

[0034] The eight input word lines simultaneously input multiple bits of the neural network's input data (activation);

[0035] The weights of the neural network are stored in the SRAM array;

[0036] The input data and weight data are subjected to a single-bit multiplication operation in the NOR gate array to obtain all the partial product data required for the multiplication calculation within one cycle.

[0037] All the partial product data are connected to the in-memory approximate multiplication circuit to complete the multiplication calculation of 8-bit input and 8-bit weight;

[0038] The result of the multiplication circuit is input to the near-memory addition tree circuit to perform the accumulation process, and the result of the neural network calculation is obtained.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] This invention integrates approximate computation and in-memory computation, taking advantage of the fault-tolerant nature of neural networks, to design an approximate in-memory multiplier circuit with configurable accuracy. This effectively reduces the internal circuit complexity of the multiplier, achieving significant improvements in performance, energy efficiency, and integration while meeting the accuracy requirements of neural networks.

[0041] Furthermore, by changing the computational parallelism, all multiplicative partial products can be calculated within one cycle, eliminating the peripheral shift and accumulation circuits in the original circuit and effectively improving data processing throughput. Attached Figure Description

[0042] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0043] Figure 1 This is a circuit diagram of a basic memory computing unit according to an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of a high-efficiency SRAM in-memory computing circuit based on approximate calculation according to a preferred embodiment of the present invention;

[0045] Figure 3 for Figure 2 The diagram shows the structure of the approximate multiplier in the embodiment shown.

[0046] Figure 4 for Figure 3 The diagrams shown in the embodiments are structural diagrams of a precise 4:2 compressor and an approximate 4:2 compressor.

[0047] Figure 5 This is a circuit diagram of a high-efficiency SRAM in-memory calculation based on approximate calculation, which is another preferred embodiment of the present invention. Detailed Implementation

[0048] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0049] This invention provides an embodiment of a high-efficiency SRAM in-memory computing circuit based on approximate calculation, comprising: an SRAM cell integrating several adjustable number of two-input NOR gates, and multiple SRAM cells forming an SRAM in-memory computing array; within the SRAM in-memory computing array, all partial products required for multi-bit calculation can be completed within one cycle, and the multiply-accumulate result can be directly output.

[0050] like Figure 1The diagram shows a further optimized in-memory computing unit based on the above embodiment; it includes a transistor, a word line (WL), a bit line (BL), and an inverted bit line (BLB); the SRAM cell stores single-bit data internally through inverters connected end-to-end, with two storage nodes denoted as Q and QB respectively. When representing multi-bit data, multiple SRAM cells are required. The word line, bit line, and inverted bit line are used to implement the SRAM's own access functions.

[0051] When the data quantization bit width is 8 bits, the 6T SRAM storage cell is closely connected to 8 two-input NOR2 gates. The SRAM storage node QB is fan-out connected to the first input data port of the 8 NOR2 gates. One SRAM and 8 NOR2 gates form a basic storage and computing unit.

[0052] The in-memory computing unit circuit can be directly applied to other computing systems where multiplication is dominant, such as image signal processing and Hadamard product calculation.

[0053] like Figure 2 The diagram shown illustrates the structure of a high-efficiency SRAM in-memory computing circuit based on approximate calculation provided by this invention. This circuit is used to perform vector-matrix multiplication between the input vector and the weight matrix in the SRAM array when performing multiply-accumulate calculations in a neural network. In this embodiment, an 8-bit data quantization width is used as an example. The 8 bits of each element in the input vector are connected in a row-shared manner to the second input ports of the eight NOR gates in the basic in-memory unit of a single row.

[0054] The result of the 8x8 NOR gate array in the 8 basic computational storage units is the partial product of the multi-bit multiplication. This partial product result is then input into the nearest-memory tree multiplier to complete the multi-bit multiplication calculation. After the multi-bit multiplication is complete, the result is input into the nearest-memory addition tree to perform precise accumulation, thus realizing the complete multiplication-accumulation calculation process.

[0055] The calculation process in this embodiment can be directly extended to other quantization bit width cases.

[0056] like Figure 3 The diagram shown is a schematic of a near-memory tree multiplier in a preferred embodiment of the present invention. In this tree multiplier, each point represents a bit of the partial product, and the calculation process includes a half adder, a full adder, an exact 4:2 compressor, and an approximate 4:2 compressor.

[0057] By changing the circuit structure of the approximate 4:2 compressor, as well as the proportion and distribution strategy of the approximate compressor during partial product compression, different computational accuracies can be achieved.

[0058] When performing neural network computations, different layers of the neural network have different requirements for data processing accuracy. Specifically, for layers with lower accuracy requirements, the proportion of approximate multipliers can be larger to achieve higher energy efficiency; for layers with higher accuracy requirements, fewer approximate multipliers are used to achieve higher computational accuracy. By configuring different network layers, high energy efficiency, high performance, and high integration can be achieved while ensuring the overall accuracy of the neural network.

[0059] Furthermore, the bit width of the computation to be performed varies. For example, high precision uses 8 bits for computation, while low precision uses 4 bits. When performing neural network computation using SRAM in-memory computing, the weight data is stored in the SRAM array, and the input data is input from the outside and connected to NOR gates. When implementing different bit widths, the weight precision can be changed by modifying the data storage mode; the input precision can be achieved by adjusting the number of computation lines and correspondingly correcting the number of NOR gates.

[0060] Furthermore, the computational precision varies after the calculations are performed. When the bit width of the data to be processed remains the same, different precision configurations can be achieved by adjusting the approximate multiplier strategy. Specifically, this involves: adjusting the number of NOR gates in the circuit, i.e., adjusting the partial product precision; adjusting the proportion of the approximate 4-2 compressor in the multiplier; and adjusting the circuit structure of the approximate 4-2 compressor.

[0061] The present invention provides a preferred embodiment of a precise 4:2 compressor and an approximate 4:2 compressor.

[0062] Figure 4 (a) is a diagram of the precise 4:2 compressor structure, where x1-x4 are the input data, T in S is the input carry signal, and C and T are the output sum signals. out To output the carry signal. The circuit in the precise 4:2 compressor is composed of two full adders, which has huge area and power consumption costs.

[0063] Figure 4 (b) is a schematic diagram of an approximate 4:2 compressor structure. In this structure, only x1-x4 are used as circuit inputs, eliminating carry input signals. Simultaneously, the output signal becomes a sum signal and a carry output signal. Through approximate multiplier design, configurable output accuracy can be achieved, satisfying the accuracy requirements of neural networks while achieving significantly higher computational energy efficiency and area efficiency. Similar to adjusting the proportion of the approximate 4:2 compressor in the multiplier, different approximate 4:2 compressor structures can be used for neural network layers with different accuracy requirements. The optimal approximate multiplier configuration can be found through a search process.

[0064] To obtain partial products with different levels of precision, the present invention provides a preferred embodiment, such as... Figure 5The figure shows another schematic diagram of the in-memory computing unit structure provided by the present invention. As shown in the figure, the number of NOR gates placed adjacent to the SRAM memory cells in the computing unit varies. In this embodiment, the number decreases sequentially from left to right, namely 8, 8, 7, 6, 5, 4, 3, and 2. In other embodiments, other numbers can be arranged.

[0065] SRAM storing low-weight bits requires fewer NOR gates. By configuring the number of NOR gates, partial products of different precisions can be obtained. When the precision of the partial product is lower, the overhead of the peripheral near-memory multiplier will also be reduced accordingly, further improving the performance, energy efficiency, and integration of the computing circuit.

[0066] Based on the same concept as the above embodiments, the present invention provides another embodiment: a high-performance SRAM in-memory computation method based on approximate calculation, comprising:

[0067] S100, 8 input word lines simultaneously input multiple bits of the neural network's input data (activation);

[0068] S200, the weights of the neural network are stored in an SRAM array;

[0069] S300: Input data and weight data perform a single-bit multiplication operation in an NOR gate array to obtain all the partial product data required for multiplication calculation within one cycle;

[0070] S400 connects all partial product data to the in-memory approximate multiplication circuit to complete the multiplication calculation of 8-bit input and 8-bit weight;

[0071] S500: The result of the multiplication circuit is input to the near-store addition tree circuit to perform the accumulation process and obtain the neural network calculation result.

[0072] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention. The above preferred features can be used in any combination without conflict.

Claims

1. A high-efficiency SRAM in-memory computing circuit based on approximate calculation, characterized in that, include: The SRAM in-memory computing array comprises multiple SRAM cells arranged in an array, each SRAM cell integrating an adjustable number of two-input NOR gates; within the SRAM in-memory computing array, all partial products required for multi-bit multiplication calculations can be completed in one cycle; An approximate multiplier is provided for a plurality of SRAM cells arranged in a row; The nearest-store adder takes the outputs of the approximate multipliers for all rows as its input. The partial products are processed by the approximate multiplier and the near-store adder to output the multiply-accumulate result. The SRAM in-memory computing array includes: A 6T SRAM storage unit, wherein the 6T SRAM storage unit is used to store data; The 6T SRAM has eight two-input NOR gates, and the storage data node Q is connected to the first input port of the eight two-input NOR gates in a fan-out configuration. The eight two-input NOR gates and the 6T SRAM storage cell are connected in the layout as a basic storage and computing unit. Eight input word lines are connected to the second input ports of the eight two-input NOR gates, respectively. The storage and computing basic units are grouped into rows of eight, and each is equipped with one of the approximate multiplier circuits. All NOR gate outputs of the eight basic in-memory computing units serve as inputs to the in-memory approximate multiplication circuit. The output of one of the in-memory approximate multiplication circuits is used as the input of the near-memory adder circuit; The output of the near-store addition tree is used as the overall system output.

2. The high-efficiency SRAM in-memory computing circuit based on approximate calculation according to claim 1, characterized in that, In the SRAM in-memory computing array, adjusting the number of two input NOR gates connected to the 6T SRAM storage unit adjusts the calculation precision of the partial product, thereby enabling the overall system to output multiply-accumulate results with configurable precision.

3. The high-efficiency SRAM in-memory computing circuit based on approximate calculation according to claim 2, characterized in that, In the SRAM in-memory computing array, the number of NOR gates placed in adjacent basic computing units is different; the storage weight is positively correlated with the number of NOR gates connected to the SRAM unit of a bit.

4. The high-efficiency SRAM in-memory computing circuit based on approximate calculation according to claim 1, characterized in that, The circuit structure of the approximate multiplier includes a half adder, a full adder, an exact 4:2 compressor, and an approximate 4:2 compressor.

5. The high-efficiency SRAM in-memory computing circuit based on approximate calculation according to claim 4, characterized in that, The low bits of the approximate multiplier are compressed using the approximate 4:2 compressor. The high bits of the approximate multiplier are compressed using the precise 4:2 compressor. The approximate multiplier uses different precision configurations when processing different layers of the neural network.

6. The high-efficiency SRAM in-memory computing circuit based on approximate calculation according to claim 4, characterized in that, The precise 4:2 compressor takes x1-x4 as input data, T in S is the input carry signal, and C and T are the output "sum" signals. out To output the carry signal; The circuitry in the precise 4:2 compressor is composed of two full adders.

7. The high-efficiency SRAM in-memory computing circuit based on approximate calculation according to claim 4, characterized in that, The approximate 4:2 compressor uses only x1-x4 as circuit inputs, eliminating carry input signals, and simultaneously outputs a sum signal and a carry output signal.

8. The high-efficiency SRAM in-memory computing circuit based on approximate calculation according to claim 2, characterized in that, The 6T SRAM storage unit includes: Six inverters are connected end-to-end to store single-bit data; Word lines, bit lines, and inverted bit lines are used to implement the SRAM's own access functions. The two storage nodes are denoted as Q and QB, respectively. When representing multi-bit data, multiple 6T SRAM memory units will be used.

9. A high-performance SRAM in-memory calculation method based on approximate calculation, using the circuit described in any one of claims 1-8, characterized in that, include: Eight input word lines simultaneously input multiple bits of the input data into the neural network; The weights of the neural network are stored in the SRAM in-memory computing array; The input data and weight data are subjected to a single-bit multiplication operation in the NOR gate array consisting of eight two-input NOR gates, and all the partial product data required for the multiplication calculation are obtained in one cycle. All the partial product data are connected to the in-memory approximate multiplication circuit to complete the multiplication calculation of 8-bit input and 8-bit weight; The multiplication result is input to the near-memory adder circuit to perform the accumulation process, and the neural network calculation result is obtained.

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