Ferroelectric reconfigurable transistor and memory computing circuit
By leveraging the polarization characteristics of ferroelectric reconfigurable transistors, switching between N-type and P-type transistors was achieved. By combining storage and computation, the problems of insufficient stability and energy consumption control in in-memory computing were solved, realizing efficient in-memory computing integration.
Patent Information
- Application Number
- CN202511882699.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-15
- Publication Date
- 2026-03-17
AI Technical Summary
In existing in-memory computing technologies, the stability, consistency, and energy consumption control of storage circuits are insufficient, and the logic functions are fixed, making it difficult to achieve dynamic logic reconfiguration and multi-functional operations.
By employing ferroelectric reconfigurable transistors and adjusting the polarization direction of the ferroelectric layer, the switching between N-type and P-type transistors can be achieved. Combined with storage and computing functions, an in-memory computing circuit is designed.
It reduces data transmission power consumption, improves computing efficiency, realizes the reconfigurability and multifunctionality of logic functions, solves the problem of storage-computation separation, and reduces the power consumption of circuits and chips.
Smart Images
Figure CN121692707A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of transistor devices, and in particular to ferroelectric reconfigurable transistors and in-memory computing circuits. Background Technology
[0002] With the rapid development of applications such as artificial intelligence and big data, the traditional Von Neumann architecture, which separates computing and storage units, has gradually revealed performance bottlenecks. Frequent data transfers between the processor and memory lead to high energy consumption, high latency, and limited bandwidth, forming the so-called "memory wall" problem. To overcome this limitation, "in-memory computing" has gained widespread attention as a new computing paradigm. Its core idea is to execute logical and arithmetic operations directly within the storage array, thereby reducing data movement and achieving high-energy-efficiency computing.
[0003] However, existing in-memory computing implementations still face several challenges: First, memory circuits mostly use resistive RAM (RRAM), phase-change memory (PCM), and other devices, which still have shortcomings in terms of stability, consistency, and power consumption control; second, in most solutions, the logic functions are fixed, making it difficult to achieve dynamic logic reconfiguration and multi-functional operations on the same hardware structure.
[0004] Against this backdrop, ferroelectric reconfigurable transistors (Fe-RFETs) have emerged as a highly promising solution. Ferroelectric materials possess reversible polarization and non-volatility characteristics. By controlling the polarization direction of the ferroelectric layer, the carrier type of the channel can be altered or the barrier height adjusted, thereby achieving n-type / p-type switching or multi-state storage characteristics within the same device. This characteristic enables Fe-RFETs to simultaneously possess logic function reconfigurability and data storage capabilities, providing new device support for "in-memory computing" architectures.
[0005] Therefore, in-memory computing technology based on ferroelectric reconfigurable transistors can significantly reduce data transmission power consumption, improve computing efficiency, and possess good scalability and programmability, providing key support for future artificial intelligence accelerators, edge computing chips, and low-power systems. This field is still in its early stages of development and has high research and innovation value and application prospects. Summary of the Invention
[0006] To address the problems mentioned in the background section, the present invention provides the following technical solution:
[0007] A ferroelectric reconfigurable transistor, characterized in that the ferroelectric reconfigurable transistor includes a substrate, a first dielectric layer, a first gate, a second gate, a first ferroelectric layer, a semiconductor channel layer, a first electrode, a second electrode, a second ferroelectric layer, and a third gate;
[0008] The substrate and the first dielectric layer together serve as the substrate of the ferroelectric reconfigurable transistor, with the first dielectric layer covering the substrate;
[0009] The first gate and the second gate are covered on the first dielectric layer, serving as two input ports;
[0010] The first ferroelectric layer covers the first gate and the second gate, controlling the polarity of the semiconductor channel layer;
[0011] The semiconductor channel layer covers the first ferroelectric layer;
[0012] The first electrode and the second electrode cover the semiconductor channel layer and serve as the source and drain of the transistor;
[0013] The second ferroelectric layer covers the semiconductor channel layer and serves as the gate dielectric layer, controlling the selection of the intermediate channel;
[0014] The third gate is covered on the second ferroelectric layer;
[0015] The first gate, the second gate, and the third gate can each control the selection of a segment of the channel region of the semiconductor channel layer;
[0016] When a positive pulse voltage is applied to the first gate and the second gate, and then removed, the polarization state of the ferroelectric material is maintained, thus realizing the function of an N-type transistor.
[0017] When a negative pulse voltage is applied to the first gate and the second gate, and then removed, the polarization state of the ferroelectric material is maintained, thus realizing the function of a P-type transistor.
[0018] An in-memory computing circuit based on the aforementioned ferroelectric reconfigurable transistor includes:
[0019] A P-type transistor (PMOS) and a ferroelectric reconfigurable transistor; wherein the gate of the PMOS transistor is grounded, the source is connected to the power supply voltage (Vdd), and the drain is connected to the first electrode of the ferroelectric reconfigurable transistor as an output; the first gate, second gate, and third gate of the ferroelectric reconfigurable transistor are connected to the input signals G1, G2, and G3 respectively, and the second electrode of the ferroelectric reconfigurable transistor is connected to ground (GND).
[0020] or,
[0021] A P-type transistor (PMOS) and a ferroelectric reconfigurable transistor; wherein the gate of the PMOS transistor is grounded, the source is connected to ground (GND), and the drain is connected to the first electrode of the ferroelectric reconfigurable transistor as an output; the first gate, second gate, and third gate of the ferroelectric reconfigurable transistor are connected to input signals G1, G2, and G3 respectively, and the second electrode of the ferroelectric reconfigurable transistor is connected to the power supply voltage (Vdd).
[0022] Furthermore, the storage operation of the in-memory computing circuit is implemented through a ferroelectric nonvolatile polarization mechanism.
[0023] Furthermore, the storage operation specifically includes the following steps:
[0024] The in-memory computing circuit applies a pulse voltage to the first gate, while the second and third gates are grounded; or...
[0025] The in-memory computing circuit applies a pulse voltage to the second gate, while the first and third gates are grounded; or...
[0026] The in-memory computing circuit applies a pulse voltage at the third gate, while the first and second gates are grounded.
[0027] Furthermore, applying a positive pulse voltage to the input stores a "1" state; applying a negative pulse voltage to the input stores a "0" state.
[0028] Furthermore, the in-memory computing circuit, during the calculation process, specifically:
[0029] The source of the PMOS transistor is connected to the power supply voltage (Vdd), and the second electrode of the ferroelectric reconfigurable transistor is connected to ground (GND). If the first gate stores a "1" state, and the second and third gates are connected to input signal A and input signal B respectively, then the output signal is... This is the AND-NOT logic; if the first gate stores a "0" state, and the second and third gates are connected to input signal A and input signal B respectively, then the output signal is... If the second gate stores a "1" state, and the first and third gates are connected to input signal A and input signal B respectively, then the output signal is: If the second gate stores a "0" state, and the first and third gates are connected to input signal A and input signal B respectively, then the output signal is: This is an OR logic; if the third gate stores a "1" state, and the first and second gates are connected to input signal A and input signal B respectively, then the output signal is... If the third gate stores a "0" state, and the first and second gates are connected to input signal A and input signal B respectively, then the output signal is A.
[0030] or,
[0031] The source of the PMOS transistor is connected to ground (GND), and the second electrode of the ferroelectric reconfigurable transistor is connected to the power supply voltage (Vdd). If the first gate is stored in a "1" state, and the second and third gates are connected to input signals A and B respectively, the output signal is AB, i.e., AND logic. If the first gate is stored in a "0" state, and the second and third gates are connected to input signals A and B respectively, the output signal is... If the second gate stores a "1" state, and the first and third gates are connected to input signal A and input signal B respectively, then the output signal is: If the second gate stores a "0" state, and the first and third gates are connected to input signal A and input signal B respectively, then the output signal is: The output signal is either OR or NOT; if the third gate is stored in a "1" state, and the first and second gates are connected to input signal A and input signal B respectively, the output signal is B; if the third gate is stored in a "0" state, and the first and second gates are connected to input signal A and input signal B respectively, the output signal is _____. .
[0032] Compared with traditional CMOS logic circuits, the beneficial effects of this invention are:
[0033] The ferroelectric reconfigurable transistor and in-memory computing circuit proposed in this invention utilize the non-volatile polarization characteristics of ferroelectric materials to achieve more logic functions with fewer transistors, reducing circuit complexity. At the same time, by combining storage and computing, it is expected to solve the problem of storage-computation separation and further reduce the power consumption of circuits and chips. Attached Figure Description
[0034] Figure 1 This is a schematic diagram of the ferroelectric reconfigurable transistor of the present invention;
[0035] In the figure: 1-substrate; 2-first dielectric layer; 3-first gate; 4-second gate; 5-first ferroelectric layer; 6-semiconductor channel layer; 7-first electrode; 8-second electrode; 9-second ferroelectric layer; 10-third gate;
[0036] Figure 2 This is a schematic diagram of the transfer curve of the ferroelectric reconfigurable transistor of the present invention;
[0037] Figure 3 This is a schematic diagram of the output curve of the ferroelectric reconfigurable transistor of the present invention;
[0038] Figure 4 This is a circuit diagram of the internal computing circuit of the present invention;
[0039] Figure 5 This is a schematic diagram of the in-memory computing circuit of the present invention;
[0040] Figure 6 The waveform diagrams show the different logic implementations of the in-memory computing circuit of this invention. Detailed Implementation
[0041] To make the technical means, creative features, objectives and effects of this invention easier to understand, the following description, in conjunction with the accompanying drawings and specific embodiments, further explains how this invention is implemented.
[0042] This invention provides an in-memory computing circuit based on a ferroelectric reconfigurable transistor, wherein the structure of the ferroelectric reconfigurable transistor is as follows: Figure 1 As shown, it includes a substrate 1, a first dielectric layer 2, a first gate 3, a second gate 4, a first ferroelectric layer 5, a semiconductor channel layer 6, a first electrode 7, a second electrode 8, a second ferroelectric layer 9, and a third gate 10.
[0043] A first dielectric layer 2 covers the substrate 1; a first gate 3 and a second gate 4 cover the first dielectric layer 2 and are located on the left and right sides respectively, for controlling the selection of the semiconductor channel layers on both sides; a first ferroelectric layer 5 covers the first dielectric layer 2; a semiconductor channel layer 6 covers the first ferroelectric layer 5 and provides conductivity; a first electrode 7 and a second electrode 8 cover the semiconductor channel layer and serve as the source and drain of the transistor respectively; a second ferroelectric layer 9 covers the semiconductor channel layer 6; and a third gate 10 covers the second ferroelectric layer 9 and is used to control the selection of the middle semiconductor channel layer.
[0044] Furthermore, if a positive pulse voltage is applied to the first gate 3 and the second gate 4, the ferroelectric material regions controlled by these two gates are polarized upwards, thereby attracting electrons in the semiconductor channel layer. The electron concentration is higher near the first and second gate regions, but lower in the middle channel. At this time, the transistor is in the off state, similar to an NPN junction. After the pulse voltage is removed, due to the non-volatility of the ferroelectric polarization, the polarization is maintained. When the voltage of the third gate 10 is scanned in the positive direction, the transistor changes from the off state to the on state, exhibiting the characteristics of an N-type transistor. If a negative pulse voltage is applied to the first gate 3 and the second gate 4, the ferroelectric material regions controlled by these two gates are polarized downwards, thereby attracting holes in the semiconductor channel layer. The hole concentration is higher near the first and second gate regions, but lower in the middle channel. At this time, the transistor is in the off state, similar to a PNP junction. After the pulse voltage is removed, due to the non-volatility of the ferroelectric polarization, the polarization is maintained. When the voltage of the third gate 10 is scanned in the negative direction, the transistor changes from the off state to the on state, exhibiting the characteristics of a P-type transistor.
[0045] Figure 2 , Figure 3 The transfer characteristic curves and output characteristic curves of the ferroelectric reconfigurable transistor are shown respectively, verifying its reconfigurable characteristics.
[0046] Figure 4 The circuit diagram for in-memory computation consists of a PMOS transistor and the proposed ferroelectric reconfigurable transistor, with two connection methods: The first method involves grounding the gate of the PMOS transistor, connecting its source to the power supply voltage (Vdd), and connecting its drain to the first electrode 3 of the ferroelectric reconfigurable transistor, together forming the output. Simultaneously, the first gate 3, second gate 4, and third gate 10 of the ferroelectric reconfigurable transistor are connected to the input signals G1, G2, and G3 respectively as inputs, with its source grounded (GND). The second method involves grounding both the gate and source of the PMOS transistor, with its drain connected to the first electrode 3 of the ferroelectric reconfigurable transistor, together forming the output. Simultaneously, the first gate 3, second gate 4, and third gate 10 of the ferroelectric reconfigurable transistor are connected to G1, G2, and G3 respectively as inputs, with its source connected to the power supply voltage (Vdd).
[0047] Based on the storage location, the in-memory computing circuit unit based on the ferroelectric reconfigurable transistor has three storage options. The first is to store data at the first gate 3 of the ferroelectric reconfigurable transistor, i.e., by applying a pulse voltage at G1; the second is to store data at the second gate 4 of the ferroelectric reconfigurable transistor, i.e., by applying a pulse voltage at G2; and the third is to store data at the third gate 10 of the ferroelectric reconfigurable transistor, i.e., by applying a pulse voltage at G3. The relationship between the storage state and the pulse voltage is shown in [the diagram]. Figure 5 .
[0048] The in-memory computing circuit unit based on ferroelectric reconfigurable transistors has three input methods for logic operations, similar to storage operations. The first method is to input signals A and B at the second gate 4 and the third gate 10 of the ferroelectric reconfigurable transistor, i.e., G2 and G3, respectively. The second method is to input signals A and B at the first gate 3 and the third gate 10 of the ferroelectric reconfigurable transistor, i.e., G1 and G3, respectively. The third method is to input signals A and B at the first gate 3 and the second gate 4 of the ferroelectric reconfigurable transistor, i.e., G1 and G2, respectively.
[0049] The logic function implemented by the in-memory computing circuit unit based on ferroelectric reconfigurable transistors is related to the connection method, the storage location of the previous moment, and the stored value, as detailed in Table 1.
[0050] Table 1
[0051]
[0052] Figure 6 Waveform diagrams for implementing different logics in the in-memory computing circuit unit are shown. The final summary of the achievable logic functions and the comparison with the number of traditional CMOS transistors are shown in Table 2.
[0053] Table 2
[0054]
[0055] In summary, the in-memory computing circuit unit based on ferroelectric reconfigurable transistors provided by this invention utilizes the non-volatile storage characteristics of ferroelectric materials to first achieve the switching capability of a single transistor between n-type and p-type operating modes. Simultaneously, the final logic function implemented in the in-memory computing circuit unit is related to the storage location, stored value, and connection method during the storage process. This achieves in-memory computing at the circuit unit level, reducing circuit complexity, further reducing circuit power consumption, and realizing an integrated in-memory computing architecture.
Claims
1. A ferroelectric reconfigurable transistor, comprising: The ferroelectric reconfigurable transistor comprises a substrate (1), a first dielectric layer (2), a first gate (3), a second gate (4), a first ferroelectric layer (5), a semiconductor channel layer (6), a first electrode (7), a second electrode (8), a second ferroelectric layer (9) and a third gate (10); The substrate (1) and the first dielectric layer (2) are used as the substrate of the ferroelectric reconfigurable transistor together, and the first dielectric layer (2) is covered on the substrate (1); The first gate (3) and the second gate (4) are covered on the first dielectric layer (2) and used as two input ports; The first ferroelectric layer (5) is covered on the first gate (3) and the second gate (4) and controls the polarity of the semiconductor channel layer (6); The semiconductor channel layer (6) is covered on the first ferroelectric layer (5); The first electrode (7) and the second electrode (8) are covered on the semiconductor channel layer (6) and used as the source and the drain of the transistor; The second ferroelectric layer (9) is covered on the semiconductor channel layer (6) and used as the gate dielectric layer to control the gating of the intermediate channel; The third gate (10) is covered on the second ferroelectric layer (9); The first gate (3), the second gate (4) and the third gate (10) can control the gating of a channel region of the semiconductor channel layer (6) respectively; When a positive pulse voltage is applied at the first gate (3) and the second gate (4), the polarization state of the ferroelectric material is maintained after the voltage is removed, and the N-type transistor function is realized; When a negative pulse voltage is applied at the first gate (3) and the second gate (4), the polarization state of the ferroelectric material is maintained after the voltage is removed, and the P-type transistor function is realized.
2. An in-memory computing circuit based on the ferroelectric reconfigurable transistor of claim 1, wherein, It comprises: a P-type transistor PMOS and one ferroelectric reconfigurable transistor; wherein the gate of the transistor PMOS is connected to the ground, the source is connected to the power voltage Vdd, the drain is connected to the first electrode (7) of the ferroelectric reconfigurable transistor as the output; the first gate (3), the second gate (4) and the third gate (10) of the ferroelectric reconfigurable transistor are connected to the input signals G1, G2 and G3 respectively, and the second electrode (8) of the ferroelectric reconfigurable transistor is connected to the ground GND.
3. An in-memory computing circuit based on the ferroelectric reconfigurable transistor of claim 1, wherein, It comprises: a P-type transistor PMOS and one ferroelectric reconfigurable transistor; wherein the gate of the transistor PMOS is connected to the ground, the source is connected to the ground GND, the drain is connected to the first electrode (7) of the ferroelectric reconfigurable transistor as the output; the first gate (3), the second gate (4) and the third gate (10) of the ferroelectric reconfigurable transistor are connected to the input signals G1, G2 and G3 respectively, and the second electrode (8) of the ferroelectric reconfigurable transistor is connected to the power voltage Vdd.
4. The in-memory computing circuit according to claim 2 or 3, wherein, The storage operation of the in-memory computing circuit is realized through the ferroelectric non-volatile polarization mechanism.
5. The in-memory computing circuit of claim 4, wherein, The storage operation specifically comprises the following steps: The in-memory computing circuit applies a pulse voltage at the first gate (3), and the second gate (4) and the third gate (10) are connected to the ground; or The in-memory computing circuit applies a pulse voltage at the second gate (4), and the first gate (3) and the third gate (10) are connected to the ground; or The in-memory computing circuit applies a pulse voltage at the second gate (4), and the first gate (3) and the third gate (10) are connected to the ground. The in-memory computing circuit applies a pulse voltage at the third gate (10), the first gate (3) and the second gate (4) being grounded.
6. The in-memory computing circuit unit of claim 5, wherein, A positive pulse voltage is applied at the input, i.e. a "1" state is stored; a negative pulse voltage is applied at the input, i.e. a "0" state is stored.
7. The computing-in-memory circuit of claim 2, wherein, The in-memory computing circuit, when performing a computation process, in particular: The PMOS transistor source is connected with the power voltage Vdd, and the second electrode (8) of the ferroelectric reconfigurable transistor is connected with the ground GND. If the first gate (3) stores the "1" state, the second gate (4) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is , that is, the NAND logic; if the first gate (3) stores the "0" state, the second gate (4) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is ; if the second gate (4) stores the "1" state, the first gate (3) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is ; if the second gate (4) stores the "0" state, the first gate (3) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is , that is, the OR logic. If the third gate (10) stores the "1" state, the first gate (3) and the second gate (4) are connected to the input signal A and the input signal B respectively, then the output signal is A; if the third gate (10) stores the "0" state, the first gate (3) and the second gate (4) are connected to the input signal A and the input signal B respectively, then the output signal is A.
8. The computing-in-memory circuit of claim 3, wherein, The in-memory computing circuit, when performing a computation process, in particular: The in-memory computing circuit, when performing a computation process, in particular: The PMOS transistor source is connected with the ground GND, and the second electrode (8) of the ferroelectric reconfigurable transistor is connected with the power voltage Vdd. If the first gate (3) stores the "1" state, the second gate (4) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is AB, that is, the AND logic. If the first gate (3) stores the "0" state, the second gate (4) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is . If the second gate (4) stores the "1" state, the first gate (3) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is . If the second gate (4) stores the "0" state, the first gate (3) and the third gate (10) are connected with the input signal A and the input signal B respectively, and the output signal is , that is, the NOR logic. If the third gate (10) stores the "1" state, the first gate (3) and the second gate (4) are connected with the input signal A and the input signal B respectively, and the output signal is B. If the third gate (10) stores the "0" state, the first gate (3) and the second gate (4) are connected with the input signal A and the input signal B respectively, and the output signal is .