Method and apparatus for initializing resistive memory devices

Abstract

Methods and apparatus for initializing resistive memory devices are disclosed. The apparatus includes a parallel initialization circuit; and a memory array coupled to the parallel initialization circuit, the memory array including a plurality of memory cells, the memory cells including a variable resistance material, the parallel initialization circuit to: apply a first voltage on the variable resistance material of the memory cells to form an initial filament; for each memory cell in the memory array, perform operations including: applying a second voltage having a first polarity on the variable resistance material of the memory cell to place the variable resistance material in a first resistance state; and applying a third voltage having a second polarity on the variable resistance material of the memory cell to place the variable resistance material in a second resistance state, the second polarity different from the first polarity; for each memory cell, verify a resistance of the variable resistance material in the first resistance state and / or the second resistance state; and in response to a failure of the verification, repeat performing the operations for each memory cell.

Description

[0001] This application is a divisional application of patent application No. 201780058313.4, filed on August 22, 2017, entitled "Technology for Initializing Resistive Storage Devices". Background Technology

[0002] Non-volatile memory (NVM) is a type of storage device that retains information even after power loss. NVM devices can be read-only memory (ROM) or random access memory (RAM) and can utilize various technologies. One category of NVM is resistive RAM, which includes technologies such as filament resistive random access memory (RRAM or ReRAM) cells, interface RRAM cells, magnetoresistive RAM (MRAM) cells, phase-change memory (PCM) cells (e.g., chalcogenides comprising alloys of germanium, antimony, and tellurium), memristor storage elements, and programmable metallized cells (e.g., conductive bridged RAM (CBRAM) cells). RRAM cells, which incorporate metal oxide electrolytes for both bipolar and unipolar operation, are promising NVM devices for embedded and standalone applications due to their short operating times and low power consumption. However, RRAM cells can exhibit large resistance variations in the storage array, ranging from kilobits (Kbits) to gigabits (Gbits) (or even terabits (Tbits)). The resistance variation can result in a wide resistance distribution between the low-resistance state (LRS) and high-resistance state (HRS) of the RRAM cell. This resistance variation can also result in a wide resistance distribution for the intermediate states used in multi-level cell states (MLC). This wide resistance distribution can make the design and use of the memory array difficult. Summary of the Invention

[0003] According to a first aspect of the present invention, an apparatus is disclosed comprising: a parallel initialization circuit; and a memory array coupled to the parallel initialization circuit, the memory array comprising a plurality of memory cells, the memory cells comprising a variable resistive material, wherein the parallel initialization circuit performs operations comprising: for each memory cell in the memory array, applying a first voltage to the variable resistive material of the memory cell to form an initial filament; for each memory cell in the memory array, performing an operation comprising the steps of: applying a second voltage having a first polarity to the variable resistive material of the memory cell to place the variable resistive material in a first resistive state; and applying a third voltage having a second polarity to the variable resistive material of the memory cell to place the variable resistive material in a second resistive state, wherein the second polarity is different from the first polarity; for each memory cell in the memory array, verifying the resistance of the variable resistive material in the first resistive state and / or the second resistive state; and repeating the operation for each memory cell in the memory array in response to a failure of the verification.

[0004] According to a second aspect of the present invention, a method for initializing an array of memory cells is disclosed, the method comprising: for each memory cell in the array, applying a first voltage to a variable resistive material of the memory cell to form an initial filament; for each memory cell in the array, performing an operation comprising the steps of: applying a second voltage having a first polarity to the variable resistive material of the memory cell to place the variable resistive material in a first resistive state; and applying a third voltage having a second polarity to the variable resistive material of the memory cell to place the variable resistive material in a second resistive state, wherein the second polarity is different from the first polarity; for each memory cell in the array, verifying the resistance of the variable resistive material in the first resistive state and / or the second resistive state; and repeating the operation for each memory cell in the array in response to a failure of the verification. Attached Figure Description

[0005] The invention is illustrated by way of example rather than limitation in the accompanying drawings.

[0006] Figure 1 This is a block diagram illustrating RRAM cells at different manufacturing and operation stages according to one embodiment.

[0007] Figure 2 It is a graph showing the wide resistance distribution of a memory array with conventional filamentary characteristics according to one implementation method.

[0008] Figure 3 This is a method for initializing a non-volatile memory device using a current-limiting FORM operation and multiple filament-strengthening cycles, according to one embodiment.

[0009] Figure 4 This is a graph illustrating a narrower resistance distribution of a memory array with stronger filamentary characteristics, according to one embodiment.

[0010] Figure 5 This is a circuit diagram illustrating a parallel forming test mode of a non-volatile memory device according to one embodiment.

[0011] Figure 6 This is a method for initializing a non-volatile memory device using a current-limiting FORM operation and multiple filament-strengthening cycles, according to another embodiment.

[0012] Figure 7 This is a method for initializing a non-volatile memory device using a current-limiting FORM operation and multiple filament-strengthening cycles, according to another embodiment.

[0013] Figure 8This is a method for initializing a non-volatile memory device using a current-limiting FORM operation and multiple filament-strengthening cycles, according to another embodiment. Detailed Implementation

[0014] This document describes a technique for enhancing the filamentary characteristics of non-volatile memory cells by initializing them with the FORM algorithm. As mentioned above, RRAM cells exhibit large resistance variations, resulting in a wide resistance distribution of the LRS and HRS of the non-volatile memory cells in the array. The embodiments described herein can narrow this resistance distribution. In particular, the embodiments described herein control the tail bit distribution of the resistance distribution of the HRS, LRS, IMS, or any combination thereof. Although various embodiments are described herein with respect to RRAM cells, other embodiments can also be used with different filamentary RAM technologies, such as CBRAM cells, programmable metallized cells, etc. Similarly, the embodiments shown can be used in other variable resistance cells, including, for example, interface RRAM cells, MRAM cells, PCM cells, or other programmable metallized cells. Moreover, although the various embodiments described herein are for RRAM in non-volatile memory devices, in other embodiments, the techniques described herein can be used in memory devices that do not require data retention (such as in non-volatile memory devices).

[0015] Figure 1 This is a block diagram illustrating an RRAM cell at different manufacturing and operating stages according to one embodiment. The RRAM cell is a discrete, non-volatile, rewritable resistive memory cell made of any number of materials. In the depicted embodiment, the RRAM cell is manufactured as an initial cell 100, which includes a variable resistive material disposed in an oxide layer 102 between a top electrode 104 and a bottom electrode 106. The variable resistive material can be a dielectric material and other materials with different resistive states, such as various metal oxides like hafnium dioxide (HfO2) or titanium dioxide (TiOx). In one embodiment, the oxide layer 102 comprises a single oxide. In another embodiment, the oxide layer 102 comprises multiple oxides. Furthermore, it should be noted that although in Figure 1 A single oxide layer is shown, but in other embodiments, multiple oxide layers may be used. The top electrode 104 may include a conductive material, such as a metal, a metal-containing composition, a conductive-doped semiconductor material, etc. The top electrode 106 may also include a conductive material. In the depicted embodiment, the bottom electrode 106 may include titanium nitride (TiN). Alternatively, other conductive materials or barrier metals may be used.

[0016] Typically, during manufacturing testing, after the initial cell 100 is manufactured, a forming operation (also referred to herein as a FORM operation) is performed on the initial cell 100 to generate cell 108 after the FORM operation. During the forming operation, a voltage is applied to the resistive material in the oxide layer 102 to form an initial filament 109. During subsequent use of cell 108 after the FORM operation, another voltage can be applied to the oxide layer 102 in a reset operation (also referred to herein as a RESET operation) to cause the filament to break, as shown by the broken filament 111 of cell 110 after the RESET operation. Cell 110 after the RESET operation is in HRS. During subsequent use of cell 108 after the FORM operation, another voltage can be applied to the oxide layer 102 in a set operation (also referred to herein as a SET operation) to cause the filament to reformat, as shown by the reformatized filament 113 of cell 112 after the SET operation. Cell 112 after the SET operation is in LRS. It should be noted that although Figure 1 The initial filament 109 shown is a single filament at a specific filament gap location, but in other embodiments, the filament gap can appear anywhere in the switching layer, and multiple filaments can be formed in the oxide layer 102.

[0017] FORM operations can generate an oxide layer, typically an insulator, which is fabricated to conduct electricity through filaments (conduction paths) formed after a voltage is applied. Conventionally, a sufficiently high voltage is used to form the initial filament. As described herein, the FORM operations of the embodiments described herein can employ lower voltages or lower currents compared to conventional FORM operations. It should be noted that the embodiments described herein are described relative to applying a voltage to the oxide layer. In other embodiments, different FORM conditions, such as voltage limits or current limits, may be employed. The filament 109 can be formed by the migration of vacancies or metal defects. In one embodiment where the oxide layer 102 comprises HfO2, the FORM operation generates defects called oxygen vacancies in the oxide layer 102, where oxygen is removed from the bonding sites. These oxygen vacancies can be charged and driven under an electric field. Oxygen ions and oxygen vacancies operate in a manner similar to the concepts of electrons and holes in other semiconductor technologies, but the physical mechanism of the movement of oxygen vacancies in the dielectric film differs from the physical mechanism of electrons / holes in semiconductor devices. After the filament 109 is formed, it can be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance). It should be noted that multiple filaments (or conduction paths) can be formed during the FORM and SET operations.

[0018] Conventionally, filament-based RRAM cells (e.g., HfO2-based RRAM cells) require a forming operation to initially form the filaments. This forming operation is performed to enable the use of the RRAM cell to store data. This forming operation only needs to be performed once and is typically done during manufacturing testing. Conventionally, this forming operation is slow compared to normal write operations. For example, a conventional FORM operation can take hundreds of microseconds (μs) per address. Because the forming operation is slow compared to normal write operations, the testing time involved is a problem for the feasibility of these RRAM technologies. Moreover, the techniques described herein are based on a parallel testing mode, which can significantly reduce the overall forming time, thereby resulting in faster forming operations during manufacturing testing.

[0019] Furthermore, the filaments formed using conventional FORM operations are not uniform and can exhibit undesirably large resistance variations. Specifically, the resistance distribution is controlled by the device's operating method. A voltage is applied to the RRAM cell to activate the memory device by forming a weakly conductive filament in the medium between the top and bottom electrodes. During formation, the filaments are not uniform and can exhibit undesirably large resistance variations. As described above, these resistance variations result in a wide resistance distribution in the LRS and HRS, such as... Figure 2 As shown.

[0020] Figure 2 This is a graph 200 illustrating the wide resistance distribution of a memory array with conventional filamentary characteristics, according to one implementation. Graph 200 shows the cumulative percentage of resistance of a memory array with conventional filamentary characteristics relative to any unit (AU). Using a conventional FORM operation, all cells of the array are set using a SET operation, and the resulting cells are tested to determine their resistance. As shown, when the resistance is between 1 and 1.7 AU, the cumulative percentage of the memory cells measured at LRS is 100%. From this position, the cumulative percentage gradually decreases with a so-called LRS tail distribution 202. Furthermore, the cells of the array are reset using a RESET operation, and the resulting cells are tested to determine their resistance. As shown, above 4.5 AU, the measured cumulative percentage is at HRS. At HRS, the cumulative percentage also gradually decreases with a so-called HRS tail distribution 204. Figure 2 As shown, the tail bit distribution of HRS and LRS may be problematic, and a better resistance distribution is needed for RRAM to be manufactured for reliable applications. Resistance variations can also affect the resistance distribution of the IMS states of multi-level cells.

[0021] The embodiments described herein, incorporating the proposed FORM algorithm, provide control over the tail-end distribution of the resistance profile of HRS, LRS, IMS, or any combination thereof. The proposed FORM algorithm can be used to control the resistance profile. In some embodiments, a voltage is applied to the RRAM cell to activate the memory device by forming a weakly conductive filament in the dielectric (e.g., oxide layer) between the top and bottom electrodes. Initially, the filament may not be uniform during forming and may have large resistance variations. After the initial forming operation, a series of operations for strengthening the conductive filament (e.g., SET operations) and operations for breaking the filament (RESET operations) can be performed to shape and strengthen the filament, thereby generating a narrower resistance profile of HRS, LRS, and IMS. The series of operations may consist of several SET operations followed by several RESET operations. SET and RESET operations can be performed at uniform or non-uniform frequencies. The number of SET and RESET operations can vary from 1 to any number (e.g., 1000 or more). After undergoing this series of operations, the storage device can typically operate similarly to a conventional RRAM cell, but the tail bit distribution in the storage array will be improved to achieve improved bit yield or improved device characteristics such as retention time or durability.

[0022] Figure 3 and Figures 6 to 8 Several implementations of the FORM operation are illustrated, including a current-limiting FORM operation (also known as a partial FORM operation) and multiple filament strengthening cycles to enhance the filament properties of the initial filament to obtain filament properties stronger than the initial filament. The filament strengthening cycle may also be referred to as a filament conditioning or filament forming cycle.

[0023] Figure 3 This is a method 300 for initializing a non-volatile memory device according to one embodiment, using a current-limiting FORM operation 302 (initial partial FORM operation) and multiple filament strengthening cycles 303. The method 300 begins with the current-limiting FORM operation 302. The current-limiting partial FORM operation 302 may include applying a first voltage to a variable resistive material of the non-volatile memory cell to form an initial filament having a first current limit (e.g., less than 50 microamps (μA)), such as... Figure 1The initial filament 109 is shown. Method 300 also includes a plurality of filament strengthening cycles 303. Each of the filament strengthening cycles 303 includes a first operation 304 to apply a second voltage having a first polarity to the resistive material, and a second operation 306 to apply a third voltage having a second polarity different from the first polarity to the dielectric resistive material. In another embodiment, the second voltage and the third voltage also have different magnitudes. When the first voltage is applied to the resistive material in the initial current-limiting FORM operation 302, a first current flowing through the resistive material is limited to less than a second current limit (e.g., greater than 50 μA) flowing through the resistive material when the second voltage is applied. In the depicted embodiment, the first operation 304 is performed before the second operation 306. In other embodiments, the order may be changed such that the second operation 306 is performed before the first operation 304. In some embodiments, a series of first operations 304 may be performed, followed by a series of second operations 306, or vice versa. In some cases of the FORM operation of method 300, the first operation 304 and the second operation 306 of the filament strengthening cycle 303 use a pre-SET operation and a pre-RESET operation, respectively. Using a pre-SET operation can be similar to a SET operation used during actual use of the memory cell, as shown in cell 112 after the RESET operation. For example, using a pre-SET operation may use a current similar to or smaller than that used during actual use of the SET operation. Using a pre-RESET operation can be similar to a RESET operation used during actual use of the memory cell and may use a current similar to or smaller than that used during actual use of the RESET operation, as shown in cell 110 after the RESET operation. However, in other cases, the first operation 304 and the second operation 306 of one of the filament strengthening cycles 303 do not necessarily need to actually set or reset the filament. In other cases, regular SET and RESET operations can be used for the first operation 304 and the second operation 306. In other embodiments, using a pre-SET operation may use the exact same voltage (current or other characteristics) as that used during the SET operation during actual use of the memory cell. In one embodiment, the execution of method 300 generates a voltage (current or other characteristics) similar to that used during actual use of the memory cell. Figure 1 The initial filament 109 shown is cell 108. After the initial filament 109 is formed using method 300, subsequent RESET and SET operations can be performed during use to generate cell 110 after the RESET operation and cell 112 after the SET operation, respectively, as shown. Figure 1 As shown.

[0024] like Figure 3As further shown, method 300 includes a verification operation 308 to verify the unit resistances of HRS and LRS. If the verification operation fails, the cycle can be repeated by one or more additional filament reinforcement cycles 303. Moreover, in some cases where a SET operation, a pre-SET operation, a RESET operation, and a pre-RESET operation are used, these operations can be verified by verification operation 308. Alternatively, verification operation 308 is optional.

[0025] In some implementations, the SET operation is used to set or form a filament, while the RESET operation causes the filament to break or fracture. The implementations described herein are not limited to multiple SET and RESET operations in multiple filament strengthening cycles 303, but may include a first operation 304 and a second operation 306 applying voltages of opposite polarity (opposite electric fields) to strengthen and weaken the filament formed in a portion of the FORM operation 302. More specifically, the first operation 304 increases, enhances, or otherwise strengthens the conductivity of the initial filament formed in a portion of the FORM operation 302, regardless of whether the filament is considered to be set. Similarly, the second operation 306 decreases, reduces, weakens, or otherwise weakens the conductivity of the initial filament formed in a portion of the FORM operation 302, regardless of whether the filament is considered to be reset (or broken). Repeated cycles of the first and second operations (or specifically, in some cases, forming or breaking the filament) establish stronger filament characteristics. Stronger filament characteristics improve the resistance distribution, as described below regarding... Figure 4 As shown and described.

[0026] In some cases, the first operation 304 and the second operation 306 are part of manufacturing testing. In such cases, the first operation 304 can be considered a pre-use SET operation, which uses a similar current or less than that used in a SET operation during the use of the memory cell, and the second operation 306 can be considered a pre-use RESET operation, which uses a similar current or less than that used in a RESET operation during the use of the memory cell. In other cases, the first operation 304 and the second operation 306 are part of the first use of the memory cell before it is available for storing information during normal operation (e.g., during the first startup of the memory array). In other embodiments, some or all of the FORM operations presented in method 300 may be performed by BIST circuitry.

[0027] For contrast, in Figure 2 The resistance distribution of a typical form operation is shown in the figure, and... Figure 4 The above text shows... Figure 3The resistance distribution of the FORM operation proposed in Method 300. Under a series of operations in the proposed FORM operation, the tail bits of the memory array are well controlled, such as... Figure 4 As shown. Specifically, graph 400 shows the cumulative percentage of a memory array with conventional filamentary characteristics relative to the resistance of any unit (AU). Using the FORM operation proposed in method 300, all cells of the array are set using a SET operation, and the resulting cells are tested to determine their resistance. As shown, when the resistance is between 1 and 1.5 AU, the cumulative percentage of the memory cells measured under LRS is 100%. From this position, the cumulative percentage gradually decreases with a so-called LRS tail distribution 402. The LRS tail distribution 402 is much larger than... Figure 2 The LRS tail distribution 202 is more compact (or narrower). Furthermore, the HRS tail distribution 404 is much denser than... Figure 2 The HRS tail distribution 204 is more compact (or narrower). For example... Figure 4 As shown, the tail position distributions of HRS and LRS can be more compact due to the stronger filament characteristics of the FORM operation proposed in method 300. The strong filament characteristics result in less resistance variation, such as... Figure 4 The curve is shown in graph 400.

[0028] It should be noted that the data shown in graphs 200 and 400 are from a 1-transistor-1-resistor (1T1R) memory array structure. The proposed FORM operation improves the tail bit distribution of 1-selector-1-resistor (1S1R) and 1TnR / 1SnR memory arrays. Similarly, as described in the embodiments herein, the FORM operation can be applied to other filament resistor cells. It should be noted that the proposed FORM operation can be controlled by a controller or by a built-in self-test circuit (BIST) during manufacturing testing. The BIST circuit can be integrated into the same integrated circuit chip as one or more memory cells. Alternatively, the BIST circuit can be integrated into a memory subsystem having multiple integrated circuits with memory cells. In some embodiments, a read operation can be used during the FORM operation cycle. Alternatively, a read operation is not required during the cycle. Similarly, the cell resistor can be verified after a certain number of cycles or during each cycle. Verification operations in each cycle can increase test time, but verification operations after a certain number of cycles can verify the cell resistor with minimal additional test time. Alternatively, validation operations may not be required during the FORM operation cycle.

[0029] In another embodiment of the method for initializing a non-volatile memory device, a first voltage is applied to a variable resistor material of the non-volatile memory cell to form an initial filament. Then, in a first cycle for breaking or reforming the initial filament, a second voltage of a first polarity is applied to the variable resistor material, and a third voltage of a second polarity is applied. The second voltage may be greater than the first voltage in absolute value. Similarly, the third voltage may be greater than the first voltage in absolute value. In other embodiments, the second voltage may be less than the first voltage in absolute value. Moreover, in other embodiments, a current limit is changed during the application of the second voltage (e.g., the current limit is higher than during the application of the first voltage). After the first cycle, one or more additional cycles are used to break or reform the initial filament. Repeated cycles reinforce the filament properties. In one embodiment, a second voltage is applied to place the variable resistor material in an LRS, and a third voltage is applied to place the variable resistor material in an HRS. In another embodiment, as part of a SET operation (or a pre-SET operation), a second voltage is applied to set the variable resistance material in the LRS, and as part of a RESET operation (or a pre-RESET operation), a third voltage is applied to set the variable resistance material in the HRS. In another embodiment, the SET operation, the RESET operation, or both can be verified. In another embodiment, if at least one of the SET or RESET operations fails, at least one additional cycle is performed to break or reform the initial filament.

[0030] As described herein, the application of a first voltage and multiple cycles in which a second and third voltage are applied can be part of a FORM operation during manufacturing testing. This technique can be used to shape one or more filaments after a specific functional cycle to achieve better distribution, thereby extending cell lifetime. Alternatively, the FORM operation can be performed at or before the first actual use of the non-volatile memory cell. The application of the first voltage can also be considered part of a current-limiting FORM operation or an initial partial FORM operation. A current-limiting FORM operation can reduce the current through the variable resistor material to less than 50 microamps (50 μA). Other operations of repeated cycles of the FORM operation can reduce the current to between the current equal to that of the current-limiting FORM operation and up to the typical current for SET and RESET operations of the memory cell, such as between 50 μA and 100 μA. Moreover, as described herein, the non-volatile memory cell is an RRAM cell, and the variable resistor material can be a dielectric material, such as hafnium dioxide (HfO2). Alternatively, the non-volatile memory cell can be other filament-based resistive memory technologies (e.g., CBRAM, programmable metallized cells, etc.), and the variable resistive material can be other types of solid materials in which one or more filaments or other conductive paths can be formed.

[0031] In another embodiment, the non-volatile memory device includes multiple bit lines and multiple word lines. Non-volatile memory cells can be connected to bit lines and word lines. In one embodiment, during the proposed FORM operation, a bit line may be activated together with one or more additional bit lines. In another embodiment, during normal array access, the additional bit lines are in addition to the bit lines activated by normal read or write operations. Alternatively, during the proposed FORM operation, a word line may be activated together with one or more additional word lines. This is also referred to as a parallel shaping test mode. In another embodiment, the additional word lines are connected to cells on the same bit line. The following section discusses… Figure 5 This describes one implementation of a circuit for a parallel forming test mode.

[0032] In another embodiment of the method for initializing a filamentary RRAM cell, a first current is caused to flow through the oxide layer of the filamentary RRAM cell to form an initial filament having a first set of filamentary characteristics. A first electric field of a first polarity is applied to the oxide layer in a first cycle, and a second electric field of a second polarity is applied to the oxide layer in the same first cycle. After the first cycle, this process is repeated, thereby applying the first electric field of the first polarity and the second electric field of the second polarity in one or more additional cycles to form a filamentary RRAM cell having a second set of filamentary characteristics greater than the first set of filamentary characteristics. In other words, the first cycle and one or more additional cycles enhance the initial filament to have the second set of filamentary characteristics. The filamentary characteristics may include data retention characteristics, persistence characteristics, delay characteristics for subsequent SET and RESET operations, conduction gap distance, retention, post-cycle retention, resistance distribution (including LRS tail bit distribution and HRS tail bit distribution), etc. The first current flowing through the oxide layer when forming the initial filament is limited to a second current limit when the first electric field is applied to the oxide layer.

[0033] In another embodiment, a first current can flow in parallel through a plurality of filamentary RRAM cells of the RRAM device. A second set of characteristics of the filamentary RRAM cells can reduce the resistance variation of at least one of the HRS or LRS. The reduced resistance variation results in a better resistance distribution. In particular, the RRAM device may have a better HRS tail position distribution, a better LRS tail position distribution, a better IMS tail position distribution, or any combination thereof.

[0034] Figure 5This is a circuit diagram illustrating a parallel shaping test mode of a non-volatile memory device 500 according to one embodiment. The non-volatile memory device 500 includes an RRAM memory array 502 having multiple RRAM cells. Each RRAM cell is 1T / 1R. The non-volatile memory device 500 may include some or all of the parallel initialization circuitry 501. The non-volatile memory device 500 also includes a row decoder / driver 504 and a column decoder / BL-SL MUX 506. The row decoder / driver 504 receives and decodes a control signal including a row address (ROWADD), and activates one cell in the row based on the decoded row address. The row decoder / driver 504 may also be referred to as a word line decoder. The column decoder / BL-SL MUX 506 receives and decodes a control signal including a column address (COLADD), and activates one cell in the column based on the decoded column address. The column decoder / BL-SL MUX 506 also receives a bit line signal (VBL) to control multiplexers of bit lines and source lines connected to the RRAM cells. The column decoder / BL-SL MUX 506 can be divided into multiple circuits including a column decoder and bit line (BL) and source line (SL) multiplexers.

[0035] like Figure 5 As shown, the non-volatile memory device 500 also includes a word line current limiting circuit 508 to limit current during FROM operation and subsequent SET operation during use of the RRAM memory array 502. The RRAM can be designed to use the current limiting circuit during FORM and SET operations to control filament forming and create a better resistance profile as described herein. It should be noted that the WL current limiting circuit 508 can limit current to both the word line and the source line. The depicted embodiment illustrates one current limiting technique. In other embodiments, other current limiting techniques and corresponding circuits may be used.

[0036] In one implementation, these current-limiting techniques are combined with additional circuitry of the parallel initialization circuit 501 to enable the simultaneous formation of multiple word lines and / or multiple bit lines, wherein each RRAM cell is limited to the same value. Figure 5In the depicted implementation, additional circuitry can be added to the row decoder / driver 504 and the column decoder / BL-SL MUX 506. For example, logic gates can be added to the row decoder / driver 504 and to the column decoder / BL-SL MUX 506 to allow multiple word lines to be activated in parallel in response to a first control signal (ROWGRP signal) and / or multiple bit lines to be activated in parallel in response to a second control signal (COLGRP signal). The maximum number of cells formed in parallel can be limited only by the amount of current received when each cell is formed. The proposed implementation of the FORM algorithm uses extremely low current limiting for the initial forming operation (partial FORM operation), thereby allowing a large number of rows, columns, or both to be activated in parallel. In some cases, the entire chip can be activated for the initial forming operation due to low current. In some implementations, the current limit can be programmed using one or more configuration registers, one or more fuses, etc. (e.g., I...). FORM I SET The number of word lines, bit lines, or both activated in parallel is also programmable. In other embodiments, the current-limiting circuit may limit only the current of the word lines. In other embodiments, the current-limiting circuit may limit only the current of the source lines. The low current of the FORM operation allows the test mode to form many cells in parallel, thereby reducing the overall forming time. This reduction in overall forming time can result in shorter test times when the FORM operation is part of manufacturing testing.

[0037] Moreover, such as Figure 5 As shown, the non-volatile memory device 500 may be controlled by a controller 510. The controller 510 may be part of an apparatus or system that executes a FORM algorithm during manufacturing testing to form the RRAM cells of the RRAM memory array 502, as described herein. In one embodiment, the controller 510 is external to the non-volatile memory device 500 and externally initializes and / or controls circuitry for parallel initialization of the RRAM cells of the RRAM memory array 502 as part of a FORM algorithm, as described herein, including the methods 600, 700, and 800 described below. In one embodiment, the controller 510 is part of a BIST circuitry integrated on the same integrated circuit chip as the non-volatile memory device 500. The parallel initialization circuitry 511 may be referred to as including the controller 510 and additional circuitry to control the initialization of the RRAM cells of the RRAM memory array 502 as part of a FORM algorithm. The parallel initialization circuitry may be initiated externally by the controller 510, such as when implemented as an internal BIST circuitry, or internally by the controller 510. The BIST circuitry may include logic for executing the FORM algorithm. The BIST circuit may include additional circuitry with logic to control the parallel initialization circuitry 501 in order to allow parallel initialization of a plurality of RRAM cells of the RRAM memory array 502 as described herein.

[0038] In one embodiment, controller 510 executes a FORM algorithm to: in a current-limiting FORM operation, apply a first voltage to the variable resistor material of the non-volatile memory cell to form an initial filament having a first current; and execute a plurality of filament strengthening cycles to strengthen the filament characteristics of the initial filament so as to obtain a filament in the non-volatile memory cell with stronger filament characteristics than the initial filament. Each of the filament strengthening cycles may include a first operation to apply a second voltage having a first polarity to the variable resistor material, and a second operation to apply a third voltage having a second polarity to the variable resistor material. A first current flowing through the variable resistor material when the first voltage is applied is less than a second current flowing through the variable resistor material when the second voltage is applied. In some embodiments, the first current is less than 50 μA. As described herein, the first operation may be a pre-use SET operation and the second operation may be a pre-use RESET operation. The current-limiting FORM operation, the pre-use SET operation, and the pre-use RESET operation of the FORM algorithm may be executed before the volatile memory cell is used for the first time to store information.

[0039] In another embodiment, as part of the FORM algorithm, the controller 510 activates multiple bit lines in parallel while applying a first voltage to the variable resistive material. Similarly, the controller 510 can activate multiple bit lines and multiple word lines in parallel while applying the first voltage and while performing a first and second operation in a repetitive cycle. In another embodiment, additional word lines are connected to cells on the same bit line. As part of the FORM algorithm, the controller 510 can verify at least one of the first or second operation, and execute at least one additional filament reinforcement cycle if at least one of the first or second operation fails.

[0040] Figure 6 This is a method 600 for initializing a non-volatile memory device using a current-limited FORM operation and multiple filamentary reinforcement cycles, according to another embodiment. Method 600 executes a FORM algorithm to begin with a current-limited FORM operation (block 602). The current-limited FORM operation at block 602 can be considered as the initial partial FORM because the filaments are rapidly formed under a limited current and once the filaments are formed (such as...) Figure 1The initial filament 109 shown then shuts off the current. It can also be said that the initial filament formed at block 602 has the characteristics of the first set of filaments. Block 602 is repeated for all addresses of the memory array. Alternatively, this can be done for all parallel addresses. After all addresses or parallel addresses have been addressed, the FORM algorithm of method 600 performs multiple filament reinforcement loops, including using a pre-SET operation (block 604), followed by a pre-RESET operation (block 606). Blocks 604 and 606 can be repeated N times, where N is a positive integer. In some cases, N can be a predetermined number. In other cases, N is programmable. After repeating blocks 604 and 606 N times, the FORM algorithm of method 600 performs a verification operation (block 608) to verify the SET or RESET from the multiple loops using the pre-SET and pre-RESET operations in blocks 604 and 606. If the verification operation fails at box 608, the FORM algorithm of method 600 returns to one or more additional loops executing boxes 604 and 606 until the verification operation succeeds. Assuming the verification operation succeeds at box 608, the FORM algorithm of method 600 repeats this process for all addresses, returning to box 604 to execute the pre-use SET and pre-use RESET operations at boxes 604 and 606 for the next address. After all addresses have been processed, method 600 terminates. In one implementation, the execution of method 600 generates... Figure 1 The initial filament 109 shown is cell 108. After the initial filament 109 is formed using method 600, subsequent RESET and SET operations can be performed during use to generate cell 110 after the RESET operation and cell 112 after the SET operation, respectively, as shown. Figure 1 As shown.

[0041] It should be noted that the pre-use SET operation at box 604 and the pre-use RESET operation at box 606 can use similar or smaller currents compared to those used in conventional SET and RESET operations. The pre-use SET operation at box 604 and the pre-use RESET operation at box 606 may not require the actual setting or resetting of the filament as in conventional SET and RESET operations. More importantly, the pre-use SET operation and the pre-use RESET operation apply electric fields of opposite polarities to strengthen the initial filament formed at box 602. Repeated cycles of the pre-use SET operation and the pre-use RESET operation strengthen the filament into a second set of filament characteristics superior to those of the first set of filaments. These second set of filament characteristics are also superior to those of filaments formed using conventional FORM operations as described herein.

[0042] Figure 7This is method 700 for initializing a non-volatile memory device using a current-limiting FORM operation and multiple filament-strengthening cycles according to another embodiment. Method 700 executes a FORM algorithm to begin with a current-limiting FORM operation (block 702). The current-limiting FORM operation at block 702 can be considered as an initial partial FORM because the filaments are rapidly formed under limited current and the current is turned off as soon as the filaments are formed. It can also be referred to as the initial filaments formed at block 702 having first-set filament characteristics. In some embodiments, block 702 is repeated for all addresses of the memory array. Alternatively, this can be done for all parallel addresses. After all addresses or parallel addresses have been addressed, the FORM algorithm of method 700 executes multiple filament-strengthening cycles, including using a pre-SET operation (block 704), followed by a pre-RESET operation (block 706). Blocks 704 and 706 can be repeated for all addresses. After repeating boxes 604 and 606 for all addresses, the FORM algorithm of method 700 performs a verification operation (box 708) to verify the SET or RESET operations from boxes 704 and 706 using the pre-SET and pre-RESET operations. If the verification operation fails at box 708, the method returns to the operations in boxes 704 and 706 until the verification operation succeeds. Assuming the verification operation succeeds at box 708, method 700 repeats this process N times, where N is a positive integer. In some cases, N can be a predetermined number. In other cases, N is programmable. Specifically, for each of the N loops, method 700 returns to box 704. After the above process has been repeated N times, method 700 terminates. In one implementation, the execution of method 700 generates... Figure 1 The initial filament 109 shown is cell 108. After the initial filament 109 is formed by method 700, subsequent RESET and SET operations can be performed during use to generate cell 110 after the RESET operation and cell 112 after the SET operation, respectively, as shown. Figure 1 As shown.

[0043] Figure 8This is method 800 for initializing a non-volatile memory device using a current-limited FORM operation and multiple filament-strengthening cycles according to another embodiment. Method 800 executes a FORM algorithm to begin entering FORM mode (block 802). The FORM algorithm initializes the selection of a set of parallel word lines and a set of parallel bit lines, and initializes the row and column address registers (block 804). The FORM algorithm of method 800 performs a current-limited FORM operation (block 806). The current-limited FORM operation at block 806 can be considered as an initial partial FORM because the filament is rapidly formed under limited current and the current is turned off as soon as the filament is formed. It can also be said that the initial filament formed at block 806 has the characteristics of a first set of filaments. At block 808, the address is incremented, and block 806 is repeated for all addresses in the memory array. After all addresses are completed, the FORM algorithm of method 800 initializes the row and column address registers (block 810). Then, the FORM algorithm of method 800 executes multiple filament-strengthening cycles. One loop includes a pre-SET operation (box 812) and a pre-RESET operation (box 814). After boxes 812 and 814, the FORM algorithm increments the address at box 816 and returns to box 812 in the next loop. Boxes 812, 814, and 816 may be repeated N times, where N is a positive integer (programmable or predetermined). The FORM algorithm of method 800 initializes the row and column address registers (box 818). Then, the FORM algorithm of method 800 performs a verification operation (box 820) to verify the SET or RESET from boxes 812 and 814 using the pre-SET and pre-RESET operations. At box 822, the FORM algorithm determines whether the verification operation passed. If the verification operation failed, the FORM algorithm may repeat the loop, indicating the address as undesirable, performing a repair operation (e.g., remapping the address with the failed bit to a redundant memory cell), or any combination thereof. If the verification operation for the corresponding address passed, the FORM algorithm returns to box 818 to repeat the process for all addresses in the memory array. For example, when the verification operation passes at box 822, the address can be incremented before returning to box 820. After repeating the process for all addresses, method 800 ends. In another embodiment, the verification operation is performed after boxes 812 and 814. In one embodiment, the execution of method 800 generates... Figure 1 The initial filament 109 shown is cell 108. After the initial filament 109 is formed using method 800, subsequent RESET and SET operations can be performed during use to generate cell 110 after the RESET operation and cell 112 after the SET operation, respectively, as shown. Figure 1 As shown.

[0044] Numerous details have been set forth in the foregoing description. However, those skilled in the art who will benefit from the invention will readily understand that embodiments of the invention can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form rather than in detail to avoid obscuring this specification.

[0045] The terms “example” or “exemplary” are used herein to mean an instance, situation, or illustration. Any aspect or design described herein as an “example” or “exemplary” is not necessarily considered preferred or advantageous over other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present concepts in a specific manner. As used in this invention, the term “or” is intended to mean inclusive rather than exclusive. That is, unless otherwise specified or clear from the context, “X includes A or B” is intended to mean any natural inclusion arrangement. That is, “X includes A or B” is satisfied if X includes A; X includes B; or X includes both A and B. Furthermore, unless otherwise specified or clear from the context, the article “a” as used in this invention and the appended claims is generally considered to mean “one or more”. Moreover, the use of the terms “implementation” or “an implementation” or “a mode of implementation” is not intended to refer to the same implementation or mode of implementation unless so described.

[0046] The foregoing description sets forth numerous specific details (such as examples of specific systems, components, methods, etc.) to provide a good understanding of several implementations. However, those skilled in the art will readily understand that at least some implementations can be practiced without these specific details. In other instances, well-known components or methods are not described in detail or presented in a single block diagram format to avoid unnecessarily obscuring the embodiments of the invention. Therefore, the specific details set forth are merely exemplary. Specific implementations may differ from these exemplary details and are still contemplated within the scope of the embodiments of the invention.

[0047] The foregoing description includes specific terminology and reference numerals to provide a thorough understanding of embodiments of the invention. In some cases, terminology and reference numerals may refer to specific details that are not essential to practicing embodiments of the invention. For example, in alternative embodiments, any specific number of bits, signal path widths, signal conduction or operating frequencies, component circuits or devices, etc., may differ from those described above. Moreover, interconnections between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single-conductor signal links may alternatively be multi-conductor signal links. Signals or signal conduction paths shown or described as single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, signals described or depicted as having a high-state active level or a low-state active level may have opposite logic levels. Component circuits within an integrated circuit device may be implemented using metal-oxide-semiconductor (MOS) technology, bipolar technology, or any other technology in which logic circuits and analog circuits can be implemented. Regarding terminology, a signal is referred to as an "assertion" when it is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a specific condition. Conversely, a signal can be referred to as "de-asserted" to indicate that the signal is driven to a state different from the asserted state (including high or low logic states, or floating states that may occur when the signal driver circuit transitions to a high-impedance condition (such as an open-drain or open-collector condition)). When a signal driver circuit asserts a signal on a signal line connected between the signal driver circuit and the signal receiver circuit, the signal driver circuit can be said to be "outputting" the signal to the signal receiver circuit. A signal line can be referred to as "active" when the signal is asserted on the signal line, and as "deactivated" when the signal is de-asserted. Additionally, the prefix symbol " / " attached to the signal name indicates that the signal is a low-state active signal (i.e., the asserted state is a logic low state). The line above the signal name (e.g., ...) is also used. The term "connection" is used herein to refer to both direct connections and connections via one or more intervention circuits or structures. "Programming" an integrated circuit device may include, for example, but not limited to, loading control values ​​into registers or other storage circuitry within the device in response to host instructions and thus controlling aspects of the device's operation; establishing a device configuration or controlling aspects of the device's operation through a single programming operation (e.g., blowing a fuse within a configuration circuit during device manufacturing); and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also known as bundling) to establish a specific device configuration or aspect of the device's operation. The term "exemplary" is used to express an example, not a preference or requirement. While embodiments of the invention have been described with reference to specific details of the invention, it will be readily understood that various modifications and variations may be made to these embodiments without departing from the broader spirit and scope of the invention. For example, a feature or aspect of any of the embodiments of the invention may be combined with or substituted for any other of the embodiments of the invention, at least where practically feasible. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0048] It should be understood that the foregoing description is intended to be illustrative rather than restrictive. Many other embodiments will be readily understood by those skilled in the art after reading and understanding the foregoing description. Therefore, the scope of embodiments of the invention should be determined by referring to the full scope of the appended claims and their equivalents.

[0049] While embodiments of the invention have been described with reference to specific details, it will be readily understood that various modifications and variations can be made to these embodiments without departing from the broader spirit and scope of the invention. For example, any feature or aspect of an embodiment of the invention may be combined with or substituted for any other feature or aspect of an embodiment of the invention, at least where practically feasible. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

Claims

1. A resistive storage device, characterized in that, include: Parallel initialization circuit; as well as A storage array is connected to the parallel initialization circuit, the storage array comprising a plurality of storage cells, the storage cells comprising a variable resistive material, wherein the parallel initialization circuit performs the following operations: For each memory cell in the memory array, a first voltage is applied to the variable resistive material of the memory cell to form an initial filament. Applying the first voltage to the variable resistive material of the memory cell to form the initial filament is part of a forming operation during manufacturing testing, and the initial filament is used to be shaped and strengthened in subsequent operations of applying a second voltage with a first polarity and a third voltage with a second polarity. For each storage cell in the storage array, the following steps are performed: Applying a second voltage of the first polarity to the variable resistive material of the storage cell to cause the variable resistive material to be in a first resistive state; and A third voltage having a second polarity is applied to the variable resistive material of the storage cell to cause the variable resistive material to be in a second resistive state, wherein the second polarity is different from the first polarity; For each memory cell in the memory array, verify the resistance of the variable resistivity material in the first resistive state and / or the second resistive state; and In response to the failure of the verification of one storage cell in the storage array, the operation is repeated for one of the plurality of storage cells.

2. The resistive memory device as claimed in claim 1, characterized in that, The first resistance state is a low resistance state, and the second resistance state is a high resistance state.

3. The resistive memory device as claimed in claim 1, characterized in that: Applying the second voltage having the first polarity includes, as part of a setting operation, applying the second voltage having the first polarity to the variable resistance material, wherein the first resistance state is a low resistance state; as well as Applying the third voltage having the second polarity includes, as part of a reset operation, applying the third voltage having the second polarity to the variable resistive material, wherein the second resistive state is a high-resistivity state.

4. The resistive memory device as claimed in claim 3, characterized in that, The operation also includes: Verify at least one of the setting operation or the reset operation.

5. The resistive memory device as claimed in claim 4, characterized in that, The operation also includes: If at least one of the setting operation or the reset operation fails, the initial filament is broken and reformed.

6. The resistive memory device as claimed in claim 1, characterized in that, Applying the first voltage to the variable resistance material of the storage cell to form the initial filament is part of the forming operation performed when the storage cell is first used.

7. The resistive memory device as claimed in claim 1, characterized in that, Applying the first voltage to the variable resistive material of the storage cell to form the initial filament is part of a current-limiting forming operation, wherein the current passing through the variable resistive material during the current-limiting forming operation is less than 50 microamps.

8. The resistive memory device as claimed in claim 1, characterized in that, The storage unit is a resistive random access memory unit.

9. The resistive memory device as claimed in claim 1, characterized in that, The variable resistance material is a metal oxide.

10. The resistive memory device as claimed in claim 9, characterized in that, The metal oxide is at least one of hafnium dioxide or titanium dioxide.

11. The resistive memory device as claimed in claim 1, characterized in that, Also includes: Multiple bit lines, each memory cell in the memory array being coupled to one of the multiple bit lines, wherein the operation further includes activating multiple bit lines during the application of the first voltage.

12. The resistive memory device as claimed in claim 1, characterized in that, Also includes: Multiple word lines, each memory cell in the memory array being coupled to one of the multiple word lines, wherein the operation further includes activating multiple word lines during the application of the first voltage.

13. The resistive memory device as claimed in claim 1, characterized in that, The storage unit is a non-volatile storage unit.

14. The resistive memory device as claimed in claim 1, characterized in that, For each memory cell in the memory array, verifying the resistance of the variable resistive material in the first resistive state and / or the second resistive state includes: verifying the resistance of the variable resistive material in the first resistive state and the second resistive state.

15. A method for initializing a memory array of a resistive memory device, the memory array comprising a plurality of memory cells, the memory cells comprising a variable resistive material, characterized in that, The method includes: For each memory cell in the memory array, a first voltage is applied to the variable resistive material of the memory cell to form an initial filament. Applying the first voltage to the variable resistive material of the memory cell to form the initial filament is part of a forming operation during manufacturing testing, and the initial filament is used to be shaped and strengthened in subsequent operations of applying a second voltage with a first polarity and a third voltage with a second polarity. For each storage cell in the storage array, the following steps are performed: Applying a second voltage of the first polarity to the variable resistive material of the storage cell to cause the variable resistive material to be in a first resistive state; and A third voltage having a second polarity is applied to the variable resistive material of the storage cell to cause the variable resistive material to be in a second resistive state, wherein the second polarity is different from the first polarity; For each memory cell in the memory array, verify the resistance of the variable resistivity material in the first resistive state and / or the second resistive state; and In response to the failure of the verification of one storage cell in the storage array, the operation is repeated for one of the plurality of storage cells.

16. The method as described in claim 15, characterized in that, The first resistance state is a low resistance state, and the second resistance state is a high resistance state.

17. The method as described in claim 15, characterized in that: Applying the second voltage having the first polarity includes, as part of a setting operation, applying the second voltage having the first polarity to the variable resistance material, wherein the first resistance state is a low resistance state; as well as Applying the third voltage having the second polarity includes, as part of a reset operation, applying the third voltage having the second polarity to the variable resistive material, wherein the second resistive state is a high-resistivity state.

18. The method as described in claim 17, characterized in that, Also includes: Verify at least one of the setting operation or the reset operation.

19. The method as described in claim 18, characterized in that, Also includes: If at least one of the setting operation or the reset operation fails, the initial filament is broken and reformed.

20. The method as described in claim 15, characterized in that, For each memory cell in the memory array, verifying the resistance of the variable resistive material in the first resistive state and / or the second resistive state includes: verifying the resistance of the variable resistive material in the first resistive state and the second resistive state.

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