Stacked hybrid photosensor wafer level package structure and method

Abstract

The application relates to a stacked hybrid light sensor wafer level packaging structure and method, which comprises a first wafer level packaging body provided with a plurality of chips and a light sensor, a second wafer level packaging body arranged on the first wafer level packaging body and provided with a laser emitter on the top surface, and a black plastic packaging layer arranged on the first wafer level packaging body and located at the periphery of the second wafer level packaging body, and the black plastic packaging layer is provided with a through hole corresponding to the light sensor to expose the light sensor. The packaging structure of the application separates the light sensor and the laser emitter by arranging the black plastic packaging layer, and the optical sensor and the laser emitter are not arranged in the same plane and have a height difference, so that the light emitted by the laser emitter cannot directly irradiate on the light sensor, a natural light barrier is formed, and interference between the optical sensor and the laser emitter is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a stacked hybrid optical sensor wafer-level packaging structure and method. Background Art

[0002] The packaging structure of traditional optical sensors is as follows Figure 1 As shown, the packaging structure includes a first optical chip 5 disposed in a first cavity 3, and a second optical chip 6 disposed in a second cavity 4; a first optical window 7 corresponding to the first cavity 3, and a second optical window 8 corresponding to the second cavity 4 are disposed on the housing 2; a light-transmitting cover plate 9 covering the first optical window 7 and the second optical window 8 is also mounted on the housing 2, and the light-transmitting cover plate 9 is formed with a first convex lens structure 10 and a second convex lens structure 11 at the positions of the first optical window 7 and the second optical window 8, respectively. The first optical chip 5 and the second optical chip 6 are placed on the substrate 1, and the first cavity 3 and the second cavity 4 where the first optical chip 5 and the second optical chip 6 are located are separated by a spacer 12. The housing 2 and the backing plate 1 need to be bonded together using epoxy resin glue, which cannot completely block the penetration of light, so interference will occur between the two optical chips. Summary of the Invention

[0003] The purpose of the present invention is to overcome the defects of the prior art and provide a stacked hybrid optical sensor wafer-level packaging structure and method to solve the problem that the epoxy resin glue used in the existing optical sensor packaging structure cannot 100% block the penetration of light, thereby causing interference between the two optical chips.

[0004] The technical solution to achieve the above purpose is:

[0005] The present invention provides a stacked hybrid optical sensor wafer-level packaging structure, comprising:

[0006] A first wafer-level package body has an opening on its top surface, a plurality of chips are disposed in the opening, a light sensor disposed near the opening is further disposed on the top surface of the first wafer-level package body, and a first solder ball is disposed on the bottom of the first wafer-level package body;

[0007] a second wafer-level package provided at the opening of the first wafer-level package, wherein a laser emitter is provided on the top surface of the second wafer-level package, and a second solder ball is provided on the bottom of the second wafer-level package, wherein the second solder ball is connected to the chip at the opening; and

[0008] A black plastic packaging layer is provided on the first wafer-level package and located outside the second wafer-level package. The black plastic packaging layer is provided with a through hole corresponding to the light sensor to expose the light sensor.

[0009] The packaging structure of the present invention isolates the light sensor and the laser emitter by providing a black plastic layer, and the optical sensor and the laser emitter are not arranged in the same plane. There is a height difference between the two, which can prevent the light emitted by the laser emitter from directly hitting the light sensor, forming a natural light barrier and avoiding interference between the optical sensor and the laser emitter.

[0010] A further improvement of the stacked hybrid optical sensor wafer-level packaging structure of the present invention is that the through hole is a variable cross-section structure, and the size of the hole close to the light sensor is smaller than the size of the hole far from the light sensor.

[0011] A further improvement of the stacked hybrid optical sensor wafer-level packaging structure of the present invention is that the first wafer-level packaging body further includes a transparent plastic packaging layer, and the transparent plastic packaging layer wraps the light sensor.

[0012] A further improvement of the stacked hybrid optical sensor wafer-level packaging structure of the present invention is that the first wafer-level packaging body also includes a first carrier board arranged on the first solder ball, a first redistribution layer is formed in the first carrier board, and the first redistribution layer is electrically connected to the first solder ball.

[0013] A further improvement of the stacked hybrid optical sensor wafer-level packaging structure of the present invention is that the first wafer-level packaging body also includes a first silicon interposer arranged on the first carrier board, and a plurality of silicon vias are provided in the first silicon interposer, and conductive columns are provided in the silicon vias, and the conductive columns are electrically connected to the first redistribution layer.

[0014] The present invention also provides a packaging method for a stacked hybrid optical sensor wafer-level packaging structure, comprising the following steps:

[0015] Prepare a first wafer-level package, wherein a plurality of chips are arranged at an opening on a top surface of the obtained first wafer-level package, a light sensor is arranged near the opening, and a first solder ball is arranged at the bottom;

[0016] Prepare a second wafer-level package, place a second solder ball at the bottom of the second wafer-level package at the opening of the first wafer-level package, and connect the second solder ball to the chip;

[0017] A black plastic sealant is provided on the first wafer-level package to form a black plastic layer provided on the first wafer-level package and located around the second wafer-level package, and a through hole is formed on the black plastic layer corresponding to the light sensor to expose the light sensor.

[0018] A further improvement of the packaging method of the present invention is that, when providing the black plastic sealant, a mold is provided on the first wafer-level package body, and a placeholder column is provided in the mold at a position corresponding to the light sensor. The placeholder column has a variable cross-section structure, and the size of one end connected to the mold is larger than the size of the other end.

[0019] Black plastic encapsulation glue is injected into the mold to form the black plastic encapsulation layer, and the through hole is formed in the black plastic encapsulation layer through the placeholder column. The formed through hole has a variable cross-section structure, and the hole size close to the light sensor is smaller than the hole size away from the light sensor.

[0020] A further improvement of the packaging method of the present invention is that the step of preparing the first wafer-level package includes:

[0021] placing a first carrier plate on a glass plate;

[0022] forming a first redistribution layer in the first carrier board;

[0023] Disposing a first silicon interposer on the first carrier, and disposing a plurality of through silicon vias in the first silicon interposer;

[0024] Disposing a conductive column in the TSV and electrically connecting the conductive column to the first redistribution layer;

[0025] Arranging a plurality of chips and light sensors on the first silicon interposer, and electrically connecting the arranged chips and light sensors to corresponding conductive pillars;

[0026] A transparent plastic layer is disposed on the first carrier board and the first silicon interposer. The transparent plastic layer wraps the light sensor and forms openings at positions corresponding to the plurality of chips to expose the plurality of chips.

[0027] A further improvement of the packaging method of the present invention is that when arranging a plurality of chips, the plurality of chips are arrayed on the first silicon interposer.

[0028] A further improvement of the packaging method of the present invention is that when arranging multiple chips, the multiple chips are stacked on the first silicon interposer, and the light sensor is arranged on the chip located on the top. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The packaging structure of the traditional light sensor

[0030] Figure 2 Schematic diagram of the stacked hybrid optical sensor wafer-level packaging structure of the present invention.

[0031] Figures 3 to 6 and Figure 9 Schematic diagram of the decomposed steps of the manufacturing process of the first wafer-level package body in the stacked hybrid optical sensor wafer-level packaging structure of the present invention.

[0032] Figure 7 It is a structural schematic diagram of an embodiment of chip arrangement in the stacked hybrid optical sensor wafer-level packaging structure of the present invention.

[0033] Figure 8 Schematic diagram of another embodiment of chip arrangement in the stacked hybrid optical sensor wafer-level packaging structure of the present invention.

[0034] Figure 10 Schematic diagram of the structure of the stacked hybrid optical sensor wafer-level packaging structure of the present invention, in which the second wafer-level packaging body is arranged on the first wafer-level packaging body.

[0035] Figure 11 For Figure 10 Schematic diagram of the structure of setting a black plastic sealing layer on the basis of. DETAILED DESCRIPTION

[0036] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0037] See Figure 2 The present invention provides a stacked hybrid optical sensor wafer-level packaging structure and method, which is used to solve the problem that the existing optical sensor packaging structure uses epoxy resin glue to stick the shell and cannot achieve 100% blocking of light penetration, thereby causing interference between the two optical chips. The packaging structure of the present invention can form a natural barrier for the light sensor, and the light sensor and the laser emitter are set by utilizing the stacking height difference, so that the light sensor and the laser emitter are not in the same layer, which can prevent light from directly hitting the light sensor. A black plastic layer is set above the light sensor and on the outside of the laser emitter. The black plastic layer can prevent the light generated by the laser emitter from hitting the light sensor. Furthermore, the through hole set on the black plastic layer corresponding to the light sensor is a variable cross-section structure. The closer to the light sensor, the thicker the black plastic layer is, thereby forming a good light barrier. The stacked hybrid optical sensor wafer-level packaging structure and method of the present invention are described below with reference to the accompanying drawings.

[0038] See Figure 2 , shows the structural diagram of the stacked hybrid optical sensor wafer level packaging structure of the present invention. Figure 2 , the stacked hybrid optical sensor wafer-level packaging structure of the present invention is described.

[0039] like Figure 2As shown, the stacked hybrid optical sensor wafer-level packaging structure of the present invention includes a first wafer-level packaging body 21, a second wafer-level packaging body 22 and a black plastic layer 23, combined with Figure 9 As shown, the top surface of the first wafer-level package 21 is provided with an opening 2141, where multiple chips are disposed. The top surface of the first wafer-level package 21 is also provided with a light sensor 31 disposed near the opening 2141, and the bottom of the first wafer-level package 21 is provided with a first solder ball 215. The second wafer-level package 22 is provided at the opening 2141, and a laser emitter 32 is disposed on the top surface of the second wafer-level package 22. The bottom of the second wafer-level package 22 is provided with a second solder ball 221, which is connected to the chips in the opening 2141. The black plastic layer 23 is provided on top of the first wafer-level package 21 and is located on the periphery of the second wafer-level package 22. The black plastic layer 23 has a through hole 231 corresponding to the light sensor 31 to expose the light sensor 31.

[0040] The light sensor 31 can receive light from the outside through the through hole 231 and make corresponding responses according to different light signals received.

[0041] The second wafer-level package of the present invention is located above the first wafer-level package, placing the laser emitter and light sensor in different structural layers. This creates a height difference between the two, preventing the laser light from directly hitting the light sensor. Furthermore, a black plastic layer is placed on the side of the laser emitter, forming a light barrier to prevent light from passing through.

[0042] In a specific embodiment of the present invention, Figure 2 As shown, the through hole 231 is a variable cross-section structure, and the size of the hole close to the light sensor 31 is smaller than the size of the hole far from the light sensor 31 .

[0043] The cross section of the through hole 231 is in an inverted trapezoidal shape. The structure of the through hole 231 allows the black plastic layer to be thicker closer to the light sensor 31 , thereby forming a good light barrier.

[0044] Specifically, the through hole 231 passes through the top surface and the bottom surface of the black plastic packaging layer 23 .

[0045] Preferably, the black plastic sealing layer 23 is formed by plastic sealing adhesive, and the plastic sealing adhesive can be CEL-9240HF10TR-Q(53C)16*6.8 plastic sealing adhesive produced by Hitachi Chemical.

[0046] In a specific embodiment of the present invention, Figure 9 As shown, the first wafer-level package 21 further includes a transparent plastic layer 214 , which wraps the light sensor 31 .

[0047] Preferably, the transparent plastic sealing layer 214 is an epoxy resin layer.

[0048] An opening 2141 is formed in the transparent plastic layer 214 . The opening 2141 corresponds to the chip to expose pins on the chip for connection with the second wafer-level package 22 .

[0049] In a specific embodiment of the present invention, Figure 2 and Figure 3 As shown, the first wafer-level package 21 further includes a first carrier 212 disposed on the first solder balls 215 . A first redistribution layer 2121 is formed in the first carrier 212 . The first redistribution layer 2121 is electrically connected to the first solder balls 215 .

[0050] Specifically, if Figure 3 As shown, when preparing the first redistribution layer 2121 of the first wafer-level package 21, firstly place the first carrier 212 on a glass plate 211, and then combine Figure 4 As shown, a first redistribution layer 2121 (ie, RDL (redistribution layer) structure) is formed in the first carrier 212. After the structure on the first carrier 212 is prepared, the first redistribution layer 2121 is formed in the first carrier 212. Figure 11 and Figure 2 As shown, the glass plate 211 is removed by laser irradiation to expose the first redistribution layer 2121 to the solder pads, and the first solder balls 215 are soldered to the solder pads. Preferably, the first carrier plate 212 is a polyimide plate.

[0051] Furthermore, if Figure 5 As shown, the first wafer-level package 21 further includes a first silicon interposer 213 disposed on the first carrier 212 , wherein the first silicon interposer 213 is provided with a plurality of through silicon vias 2131 (TSVs), and within the through silicon vias 2131 there are conductive pillars 2132 , which are electrically connected to the first redistribution layer 2121 .

[0052] In a specific embodiment of the present invention, Figure 6 and Figure 7 As shown, a plurality of chips are arranged on the first silicon interposer 213 and are electrically connected to corresponding conductive pillars 2132 .

[0053] In this embodiment, the chips disposed on the first silicon interposer 213 include a logic chip 33, a MEMS chip 34, a radio frequency chip 35, and a memory chip 36. These chips are arrayed on the first silicon interposer 213 and electrically connected to the first redistribution layer 2121 via conductive posts 2132. The optical sensor wafer-level packaging structure is a 2.5D package.

[0054] Preferably, the pins on the chip are connected to the corresponding pins on the light sensor by wire bonding, and the light sensor is also connected to the corresponding conductive pillars 2132 by wire bonding.

[0055] In a specific embodiment of the present invention, Figure 6 and Figure 8 As described above, the multiple chips are stacked on the first silicon interposer 213 and electrically connected to the corresponding conductive pillars 2132 .

[0056] In this embodiment, the chips disposed on the first silicon interposer 213 include a logic chip 33 , a memory chip 36 disposed on the logic chip 33 , a MEMS chip 34 disposed on the memory chip 36 , a RF chip 35 disposed on the MEMS chip 34 , and a light sensor 31 .

[0057] The light sensor 31 is disposed on the chip at the top. In this case, the light sensor wafer level packaging structure is a 3D packaging.

[0058] Preferably, the pins on the chip are connected to the corresponding pins on the light sensor by wire bonding, and the light sensor is also connected to the corresponding conductive pillars 2132 by wire bonding.

[0059] The first wafer-level package 21 of the present invention is a fan-out wafer-level package (Fan-Out WLP) structure.

[0060] In a specific embodiment of the present invention, the second solder balls 221 on the second wafer-level package 22 are electrically connected to the corresponding conductive pillars 2132 .

[0061] The second solder balls 221 on the second wafer-level package 22 are also electrically connected to the pins corresponding to the chip on the first wafer-level package 21. Preferably, the electrical connection can be achieved through bonding wires.

[0062] The second wafer-level package 22 is a fan-in wafer-level package (Fan-in WLP) structure.

[0063] like Figure 10 and Figure 11 As shown, the second wafer-level package 22 includes a second solder ball 221 at the bottom, a second carrier 222 disposed above the second solder ball 221, a second redistribution layer 223 formed within the second carrier 222, and a laser emitter 32 disposed on the second carrier 222. The second redistribution layer 223 is electrically connected to the second solder ball 221 and the laser emitter 32. Preferably, a portion of the second redistribution layer 223 is exposed from the bottom of the second carrier 222 to form a solder pad, which is soldered to the second solder ball 221 to achieve electrical connection. The laser emitter 32 is connected to the second redistribution layer 223 via a bonding wire.

[0064] The laser emitter 32 is a vertical cavity surface laser emitter (Vscel).

[0065] The beneficial effects of the stacked hybrid optical sensor wafer-level packaging structure of the present invention are:

[0066] The stacked structure places the light sensor and laser emitter in different structural layers with a height difference between the two, which prevents light from directly hitting the light sensor.

[0067] The variable-section through holes provided on the black plastic sealing layer are thicker as the black plastic sealing layer is closer to the light sensor, thereby forming a good light barrier.

[0068] The wafer-level packaging can reduce the thickness of the optical sensor to 10 μm.

[0069] The use of a black plastic sealing layer to block light can solve the problem that the existing epoxy resin glue cannot 100% block light penetration, and can form a better light barrier.

[0070] The use of black plastic layer can reduce cost expenditure.

[0071] The stacked package structure of the present invention can add more functions to the optical sensor product and reduce the package size.

[0072] The present invention also provides a packaging method for a stacked hybrid optical sensor wafer-level packaging structure, which is described below.

[0073] The packaging method of the present invention comprises the following steps:

[0074] like Figure 2 and Figure 9 As shown, a first wafer-level package 21 is prepared. A plurality of chips are provided at an opening 2141 on the top surface of the obtained first wafer-level package 21, and a light sensor 31 is provided near the opening 2141. A first solder ball 215 is provided at the bottom.

[0075] like Figure 10 As shown, a second wafer-level package 22 is prepared, a second solder ball 221 at the bottom of the second wafer-level package 22 is disposed at the opening 2141 of the first wafer-level package 21, and the second solder ball 221 is connected to the chip;

[0076] like Figure 11 As shown, a black plastic sealant is provided on the first wafer-level package 21 to form a black plastic layer 23 provided on the first wafer-level package 21 and located on the periphery of the second wafer-level package 22, and a through hole 231 is formed on the black plastic layer 23 corresponding to the light sensor 31 to expose the light sensor 31.

[0077] In a specific embodiment of the present invention, when providing the black plastic sealant, a mold is provided on the first wafer-level package body, and a placeholder column is provided in the mold at a position corresponding to the light sensor. The placeholder column has a variable cross-section structure, and the size of one end connected to the mold is larger than the size of the other end.

[0078] Black plastic sealant is injected into the mold to form a black plastic layer, and a through hole is formed in the black plastic layer through a placeholder column. The formed through hole has a variable cross-section structure, and the hole size close to the light sensor is smaller than the hole size far from the light sensor.

[0079] In a specific embodiment of the present invention, the steps of preparing a first wafer-level package include:

[0080] like Figure 3 As shown, a first carrier plate 212 is disposed on a glass plate 211;

[0081] Combine Figure 4 As shown, a first redistribution layer 2121 is formed in the first carrier 212;

[0082] Combine Figure 5 As shown, a first silicon interposer 213 is disposed on the first carrier 212 , and a plurality of through silicon vias 2131 are disposed in the first silicon interposer 213 ;

[0083] Disposing a conductive pillar 2132 in the TSV 2131 and electrically connecting the conductive pillar 2132 to the first redistribution layer 2121 ;

[0084] Combine Figure 6 As shown, a plurality of chips and light sensors 31 are arranged on the first silicon interposer 213 , and the arranged chips and light sensors 31 are electrically connected to corresponding conductive pillars 2132 ;

[0085] Combine Figure 9 As shown, a transparent plastic layer 214 is disposed on the first carrier 212 and the first silicon interposer 213 . The transparent plastic layer 214 wraps the light sensor 31 and forms openings 2141 at locations corresponding to the chips to expose the chips.

[0086] In a specific embodiment of the present invention, when multiple chips are arranged, the multiple chips are arrayed on the first silicon interposer. Figure 7 As shown, the chips arranged on the first silicon interposer 213 include a logic chip 33, a MEMS chip 34, a radio frequency chip 35, and a memory chip 36. The packaging structure at this time is a 2.5D packaging.

[0087] In a specific embodiment of the present invention, when multiple chips are arranged, the multiple chips are stacked on the first silicon interposer, and the light sensor is placed on the top chip. Figure 8 As shown, a logic chip 33 is disposed on the first silicon interposer 213 , a memory chip 36 is disposed on the logic chip 33 , a MEMS chip 34 is disposed on the memory chip 36 , a radio frequency chip 35 and a light sensor 31 are disposed on the MEMS chip 34 .

[0088] After the second wafer-level package 22 and the black plastic layer 23 are arranged on the first wafer-level package 21, Figure 11 and Figure 2 As shown, the glass plate 211 is removed by irradiating laser to expose the first redistribution layer 2121 to the bonding pad, and the first solder ball 215 is bonded to the bonding pad.

[0089] The present invention has been described in detail above with reference to the embodiments of the accompanying drawings. A person skilled in the art can make various modifications to the present invention based on the above description. Therefore, certain details in the embodiments should not be construed as limiting the present invention. The scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A stacked hybrid optical sensor wafer-level packaging structure, characterized in that: include: A first wafer-level package body has an opening on its top surface, a plurality of chips are disposed in the opening, a light sensor disposed near the opening is further disposed on the top surface of the first wafer-level package body, and a first solder ball is disposed on the bottom of the first wafer-level package body; a second wafer-level package provided at the opening of the first wafer-level package, wherein a laser emitter is provided on the top surface of the second wafer-level package, and a second solder ball is provided on the bottom of the second wafer-level package, wherein the second solder ball is connected to the chip at the opening; and a black plastic layer provided on the first wafer-level package and located on the periphery of the second wafer-level package, wherein the black plastic layer is provided with a through hole corresponding to the light sensor to expose the light sensor; The through hole has a variable cross-section structure, and the size of the hole close to the light sensor is smaller than the size of the hole far from the light sensor; The first wafer-level package further includes a first carrier board disposed on the first solder ball, wherein a first redistribution layer is formed in the first carrier board, and the first redistribution layer is electrically connected to the first solder ball; The first wafer-level package further includes a first silicon interposer disposed on the first carrier. The first silicon interposer is provided with a plurality of through-silicon vias (TSVs). The TSVs are provided with conductive pillars, and the conductive pillars are electrically connected to the first redistribution layer.

2. The stacked hybrid optical sensor wafer-level packaging structure according to claim 1, wherein: The first wafer-level package further includes a transparent plastic layer, and the transparent plastic layer wraps the light sensor.

3. A packaging method for the stacked hybrid optical sensor wafer-level packaging structure according to claim 1, characterized in that: The steps include: Prepare a first wafer-level package, wherein a plurality of chips are arranged at an opening on a top surface of the obtained first wafer-level package, a light sensor is arranged near the opening, and a first solder ball is arranged at the bottom; Prepare a second wafer-level package, place a second solder ball at the bottom of the second wafer-level package at the opening of the first wafer-level package, and connect the second solder ball to the chip; A black plastic sealant is provided on the first wafer-level package to form a black plastic layer provided on the first wafer-level package and located around the second wafer-level package, and a through hole is formed on the black plastic layer corresponding to the light sensor to expose the light sensor.

4. The packaging method according to claim 3, wherein: When providing the black plastic sealant, a mold is provided on the first wafer-level package body, and a placeholder column is provided in the mold at a position corresponding to the light sensor. The placeholder column has a variable cross-section structure, and the size of one end connected to the mold is larger than the size of the other end; Black plastic encapsulation glue is injected into the mold to form the black plastic encapsulation layer, and the through hole is formed in the black plastic encapsulation layer through the placeholder column. The formed through hole has a variable cross-section structure, and the hole size close to the light sensor is smaller than the hole size away from the light sensor.

5. The packaging method according to claim 3, wherein: The steps of preparing a first wafer-level package include: placing a first carrier plate on a glass plate; forming a first redistribution layer in the first carrier board; Disposing a first silicon interposer on the first carrier, and disposing a plurality of through silicon vias in the first silicon interposer; Disposing a conductive column in the TSV and electrically connecting the conductive column to the first redistribution layer; Arranging a plurality of chips and light sensors on the first silicon interposer, and electrically connecting the arranged chips and light sensors to corresponding conductive pillars; A transparent plastic layer is disposed on the first carrier board and the first silicon interposer. The transparent plastic layer wraps the light sensor and forms openings at positions corresponding to the plurality of chips to expose the plurality of chips.

6. The packaging method according to claim 5, wherein: When arranging multiple chips, the multiple chips are arrayed on the first silicon interposer.

7. The packaging method according to claim 5, wherein: When arranging multiple chips, the multiple chips are stacked on the first silicon interposer, and the light sensor is arranged on the chip located on the top.

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