Fully common-mode range trimmable voltage trimming operational amplifier

Abstract

The application relates to a full common-mode range offset voltage trimming operational amplifier, relates to integrated circuit technology, and comprises an operational amplifier circuit and a trimming circuit, characterized in that the trimming circuit comprises a first current source (101) to a seventh current source (107), and a fifteenth NMOS tube (M15) to a thirtieth PMOS tube (M30), a current output end of a sixth current source (106) is connected with a current input end of the seventh current source (107), and a gate is connected with a positive level input line. The application can correct the full common-mode range offset voltage of a rail-to-rail input operational amplifier to a target value, and the input offset voltage almost does not change with the change of a common-mode voltage, so that the linearity of the full common-mode range of the operational amplifier is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to integrated circuit technology, in particular to a full common mode range offset voltage trimming technique. BACKGROUND

[0002] Rail-to-rail input operational amplifier, P input pair transistor is turned on, N input pair transistor is turned off under low input common mode voltage, P input pair transistor is turned off, N input pair transistor is turned on under high input common mode voltage, P input pair transistor and N input pair transistor are turned on at the same time under intermediate input common mode voltage.

[0003] The traditional offset voltage trimming structure only trims the case where P input pair transistor and N input pair transistor are turned on at the same time, which cannot guarantee the accuracy under high common mode input, low common mode input, and weak conduction of the pair transistor. Or trim the cases where P transistor is turned on, N transistor is turned off, and P transistor is turned off, N transistor is turned on, respectively, which cannot eliminate the equivalent offset correction of the subsequent circuit caused by separate trimming, and cannot guarantee the accuracy under weak conduction of the pair transistor. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a full common mode range offset voltage trimming operational amplifier, which can improve the linearity of the operational amplifier in the full common mode range.

[0005] The technical solution adopted by the present application to solve the technical problem is a full common mode range offset voltage trimming operational amplifier, which comprises an operational amplifier circuit and a trimming circuit, and the trimming circuit comprises:

[0006] A first current source (101) having a current input end connected to VDD;

[0007] A second current source (102) having a current output end connected to VSS;

[0008] A third current source (103) having a current input end connected to VDD;

[0009] A fourth current source (104) having a current input end connected to VDD;

[0010] A fifth current source (105) having a current input end connected to VDD;

[0011] A sixth current source (106) having a current input end connected to VDD;

[0012] A seventh current source (107) having a current output end connected to VSS;

[0013] A fifteenth NMOS transistor (M15) having a gate and a drain connected to the current output end of the third current source (103) and the current input end of the second current source (102), and a source connected to VSS;

[0014] a sixteenth NMOS transistor (M16) having its gate connected to the gate of the fifteenth NMOS transistor (M15), its source connected to VSS, and its drain connected to the current output terminal of the fourth current source (104);

[0015] a seventeenth NMOS transistor (M17) having its gate and drain connected to the current output terminal of the fourth current source (104), and its source connected to VSS;

[0016] an eighteenth NMOS transistor (M18) having its gate connected to the gate of the seventeenth NMOS transistor (M17), and its source connected to VSS;

[0017] a twenty-first PMOS transistor (M21) having its source connected to VDD, its drain connected to the gate, and its gate connected to the negative level input line;

[0018] a twenty-second PMOS transistor (M22) having its source connected to VDD, its gate connected to the gate of the twenty-first PMOS transistor (M21), and its drain connected to the N transistor trimming current input terminal of the operational amplifier circuit;

[0019] a twenty-third PMOS transistor (M23) having its source connected to the current output terminal of the first current source (101), its drain connected to the current input terminal of the second current source (102), and its gate connected to the negative level input line;

[0020] a twenty-fourth PMOS transistor (M24) having its source connected to the current output terminal of the first current source (101), its drain connected to the current input terminal of the second current source (102), and its gate connected to the positive level input line;

[0021] a twenty-fifth NMOS transistor (M25) having its drain connected to the drain of the twenty-first PMOS transistor (M21), its source connected to the drain of the eighteenth NMOS transistor (M18), and its gate connected to the negative level input line;

[0022] a twenty-sixth NMOS transistor (M26) having its drain connected to the drain of the twenty-first PMOS transistor (M21), its source connected to the drain of the eighteenth NMOS transistor (M18), and its gate connected to the positive level input line;

[0023] a twenty-seventh PMOS transistor (M27) having its source connected to the current output terminal of the fifth current source (105), its drain connected to the P transistor trimming current input terminal of the operational amplifier circuit, and its gate connected to the negative level input line;

[0024] a twenty-eighth PMOS transistor (M28) having its source connected to the current output terminal of the fifth current source (105), its drain connected to the P transistor trimming current input terminal of the operational amplifier circuit, and its gate connected to the positive level input line;

[0025] a twenty-ninth PMOS transistor (M29) having its source connected to the current output terminal of the sixth current source (106), its drain connected to the current input terminal of the seventh current source (107), and its gate connected to the negative level input line.

[0026] thirtieth PMOS transistor (M30), a current output terminal of the sixth current source (106), a drain connected to a current input terminal of the seventh current source (107), and a gate connected to the positive level input line.

[0027] The operational amplifier circuit includes an output stage and a trimming stage, and the trimming stage includes:

[0028] an eighth current source (108) having a current input terminal connected to VDD;

[0029] a ninth current source (109) having a current input terminal connected to VDD;

[0030] nineteenth NMOS transistor (M19) having a drain and a gate connected to a current output terminal of the eighth current source (108) and a current input terminal of the seventh current source (107), and a source connected to ground;

[0031] eleventh PMOS transistor (M11) having a source connected to VDD and a gate connected to a gate of the twenty-first PMOS transistor (M21);

[0032] first NMOS transistor (M1) having a drain connected to a drain of the eleventh PMOS transistor (M11), a gate connected to the negative level input line, and a source connected to a source of the second NMOS transistor (M2);

[0033] twelfth PMOS transistor (M12) having a source connected to VDD and a gate connected to a gate of the eleventh PMOS transistor (M11);

[0034] second NMOS transistor (M2) having a drain connected to a drain of the twelfth PMOS transistor (M12), a gate connected to the positive level input line, and a source connected to a source of the first NMOS transistor (M1);

[0035] twentieth NMOS transistor (M20) having a drain connected to a source of the first NMOS transistor (M1), a source connected to ground, and a gate connected to a gate of the seventeenth NMOS transistor (M17);

[0036] third PMOS transistor (M3) having a source connected to a current output terminal of the ninth current source (109) and a gate connected to the negative level input line;

[0037] fourth PMOS transistor (M4) having a source connected to a current output terminal of the ninth current source (109) and a gate connected to the positive level input line;

[0038] thirteenth NMOS transistor (M13) having a drain connected to a drain of the third PMOS transistor (M3), a source connected to ground, and a gate connected to a gate of the first NMOS transistor (M1);

[0039] fourteenth NMOS transistor (M14) having a drain connected to a drain of the fourth PMOS transistor (M4), a source connected to ground, and a gate connected to a gate of the thirteenth NMOS transistor (M13).

[0040] The P-tube trimming module comprises a P-tube trimming current input end, a first P-type current connection point of which is connected to the drain of the fourteenth NMOS tube (M14), a first N-type current connection point of which is connected to the drain of the thirteenth NMOS tube (M13), a second P-type current connection point of which is connected to the drain of the second NMOS tube (M2), and a second N-type current connection point of which is connected to the drain of the first NMOS tube (M1);

[0041] The N-tube trimming module comprises an N-tube trimming current input end, a first P-type current connection point of which is connected to the drain of the fourteenth NMOS tube (M14), a first N-type current connection point of which is connected to the drain of the thirteenth NMOS tube (M13), a second P-type current connection point of which is connected to the drain of the second NMOS tube (M2), and a second N-type current connection point of which is connected to the drain of the first NMOS tube (M1).

[0042] The current values of the first current source (101), the second current source (102) and the third current source (103) are equal, and are denoted as I0;

[0043] The current values of the sixth current source (106), the seventh current source (107) and the eighth current source (108) are equal, and are denoted as I2;

[0044] The current value of the ninth current source (109) is denoted as I3, and the current value of the fifth current source (105) is denoted as I6;

[0045] The twenty-first PMOS tube (M21) and the twenty-second PMOS tube (M22) have the same size;

[0046] The twenty-third PMOS tube (M23) and the twenty-fourth PMOS tube (M24) have the same size;

[0047] The third PMOS tube (M3) and the fourth PMOS tube (M4) have the same size;

[0048] The twenty-seventh PMOS tube (M27) and the twenty-eighth PMOS tube (M28) have the same size;

[0049] The twenty-ninth PMOS tube (M29) and the thirtieth PMOS tube (M30) have the same size;

[0050] The twenty-fifth NMOS tube (M25) and the twenty-sixth NMOS tube (M26) have the same size;

[0051] The size ratio of each MOS tube is:

[0052] The fifteenth NMOS tube (M15): the sixteenth NMOS tube (M16) = 1: m;

[0053] Seventeenth NMOS transistor (M17): Eighteenth NMOS transistor (M18): Twentieth NMOS transistor (M20) = 1: n: p;

[0054] Twenty-first PMOS transistor (M21): Twenty-second PMOS transistor (M22): Eleventh PMOS transistor (M11): Twelfth PMOS transistor (M12) = 1: 1: p / (2n): p / (2n);

[0055] Nineteenth NMOS transistor (M19): Thirteenth NMOS transistor (M13): Fourteenth NMOS transistor (M14) = 1: q: q;

[0056] Twenty-third PMOS transistor (M23): Third PMOS transistor (M3) = I0: I3;

[0057] Twenty-seventh PMOS transistor (M27): Third PMOS transistor (M3) = I6: I3;

[0058] Twenty-ninth PMOS transistor (M29): Third PMOS transistor (M3) = I2: I3;

[0059] Twenty-fifth NMOS transistor (M25): First NMOS transistor (M1) = n: p.

[0060] By using the technology of the present application, the input offset voltage is hardly changed with the change of common-mode voltage while the full common-mode range offset voltage of the rail-to-rail input operational amplifier is corrected to be within the target value, thus improving the linearity of the full common-mode range of the operational amplifier. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 is the circuit diagram of the present application (including the operational amplifier circuit).

[0062] Figure 2 is the circuit diagram of the current conversion structure. DETAILED DESCRIPTION

[0063] For the convenience of combining with the drawings, hereinafter only the marks in the drawings represent the components, for example, M23 represents the “twenty-third PMOS transistor M23”, which is hereby stated.

[0064] Referring to Figure 1 and Figure 2The principle of the present application is that the total value of the trimming current of the P input pair transistor and the N input pair transistor and the ratio of the tail current of the P input pair transistor and the N input pair transistor remain unchanged during the input common-mode voltage change, and when the P input pair transistor and the N input pair transistor are turned on at the same time, the N input pair transistor is biased at a small current to weaken the equivalent offset voltage of the later stage circuit during the trimming process of the P input pair transistor and the N input pair transistor. The structure corrects the offset voltage of the rail-to-rail input operational amplifier in the full common-mode range to within the target value, thereby improving the linearity of the operational amplifier in the full common-mode range.

[0065] Figure 1 The left part of the dashed line of the figure is a trimming circuit, and the right part of the dashed line is an operational amplifier circuit.

[0066] Figure 2 The structure in the dashed box of the figure is cited from Chinese patent application 202123425035.4 "Small-area high-precision current trimming circuit".

[0067] The circuit of the present application comprises:

[0068] A first current source 101, the current input end of which is connected to VDD;

[0069] A second current source 102, the current output end of which is connected to VSS;

[0070] A third current source 103, the current input end of which is connected to VDD;

[0071] A fourth current source 104, the current input end of which is connected to VDD;

[0072] A fifth current source 105, the current input end of which is connected to VDD;

[0073] A sixth current source 106, the current input end of which is connected to VDD;

[0074] A seventh current source 107, the current output end of which is connected to VSS;

[0075] A fifteenth NMOS transistor M15, the gate and drain of which are connected to the current output end of the third current source 103 and the current input end of the second current source 102, and the source of which is connected to VSS;

[0076] A sixteenth NMOS transistor M16, the gate of which is connected to the gate of the fifteenth NMOS transistor M15, the source of which is connected to VSS, and the drain of which is connected to the current output end of the fourth current source 104;

[0077] A seventeenth NMOS transistor M17, the gate and drain of which are connected to the current output end of the fourth current source 104, and the source of which is connected to VSS;

[0078] An eighteenth NMOS transistor M18, the gate of which is connected to the gate of the seventeenth NMOS transistor M17, and the source of which is connected to VSS;

[0079] a twenty-first PMOS transistor M21 having a source connected to VDD, a drain connected to a gate of a twenty-second PMOS transistor M22, and a gate connected to a drain of the twenty-first PMOS transistor M21;

[0080] a twenty-second PMOS transistor M22 having a source connected to VDD, a drain connected to a current input terminal of an N transistor of the operational amplifier, and a gate connected to the gate of the twenty-first PMOS transistor M21;

[0081] a twenty-third PMOS transistor M23 having a source connected to a current output terminal of the first current source 101, a drain connected to a current input terminal of the second current source 102, and a gate connected to the negative level input line;

[0082] a twenty-fourth PMOS transistor M24 having a source connected to the current output terminal of the first current source 101, a drain connected to the current input terminal of the second current source 102, and a gate connected to the positive level input line;

[0083] a twenty-fifth NMOS transistor M25 having a source connected to the drain of the twenty-first PMOS transistor M21, a drain connected to the drain of the eighteenth NMOS transistor M18, and a gate connected to the negative level input line;

[0084] a twenty-sixth NMOS transistor M26 having a source connected to the drain of the twenty-first PMOS transistor M21, a drain connected to the drain of the eighteenth NMOS transistor M18, and a gate connected to the positive level input line;

[0085] a twenty-seventh PMOS transistor M27 having a source connected to a current output terminal of the fifth current source 105, a drain connected to a current input terminal of a P transistor of the operational amplifier, and a gate connected to the negative level input line;

[0086] a twenty-eighth PMOS transistor M28 having a source connected to the current output terminal of the fifth current source 105, a drain connected to the current input terminal of the P transistor of the operational amplifier, and a gate connected to the positive level input line;

[0087] a twenty-ninth PMOS transistor M29 having a source connected to a current output terminal of the sixth current source 106, a drain connected to a current input terminal of the seventh current source 107, and a gate connected to the negative level input line;

[0088] a thirtieth PMOS transistor M30 having a source connected to the current output terminal of the sixth current source 106, a drain connected to the current input terminal of the seventh current source 107, and a gate connected to the positive level input line.

[0089] The twenty-first PMOS transistor M21 and the twenty-second PMOS transistor M22 have the same size.

[0090] In the present application,

[0091] The ratio of the size of the M23 and the M24 to the size of the M3 and the M4 is equal to the ratio of the I0 and the I3,

[0092] The ratio of the size of M27, M28 to the size of M3, M4 is equal to the ratio of I6 to I3,

[0093] The ratio of the size of M29, M30 to the size of M3, M4 is equal to the ratio of I2 to I3.

[0094] The ratio of the size of M25, M26 to the size of M1, M2 is equal to the ratio of n to p.

[0095] The ratio of the size of M15 to M16 is 1:m,

[0096] The ratio of the size of M17, M18 and M20 is 1:n:p,

[0097] The ratio of the size of M21, M22, M11 and M12 is 1:1:p / (2n):p / (2n),

[0098] The ratio of the size of M19, M13 and M14 is 1:q:q.

[0099] m, n, p, q are preset values.

[0100] When a high common-mode voltage is input, M3, M4, M23, M24, M27, M28, M29, M30 are turned off, the current of M19, M13, M14 is 0, at this time, the P input pair is turned off, and the current flowing into the P tube trimming module is 0. The current flowing through M15, M16 is 0, the current of I1 flows through M17, the current of M18, M21, M22 is n*I1 (n times I1), the current of M11, M12 is p*I1 / 2, and the current of M20 is p*I1. At this time, the tail current of the N input pair is the maximum value p*I1, the current flowing into the N tube trimming module is also the maximum value n*I1, and the ratio of the total value of the N tube trimming current to the tail current of the N pair is n / p.

[0101] When the input common-mode voltage gradually decreases, M3, M4, M23, M24, M27, M28, M29, M30 gradually open, at this time, the P input pair gradually opens, and the current flowing into the P tube trimming module gradually increases to I6. During this process, the ratio of the total value of the P tube trimming current to the tail current of the P pair is a constant value. The current flowing through M15 increases from 0 to I0, the current of M16 increases from 0 to mI0, the current of M17 decreases from I1 to (I1-mI0), the current of M18, M21, M22 decreases to n(I1-mI0), the current of M11, M12 decreases to p(I1-mI0) / 2, and the current of M20 decreases to p(I1-mI0). At this time, the tail current of the N input pair decreases to a minimum value p(I1-mI0), the current flowing into the N tube trimming module also decreases to a minimum value n(I1-mI0), and the ratio of the total value of the N tube trimming current to the tail current of the N pair is still n / p.

[0102] When the input common mode voltage continues to decrease below the N input pair transistor turn-on voltage, Ml, M2, M25, M26 turn off, the current through M21, M22, Ml l, M12 is 0, at this time the N input pair transistor turns off, the current flowing into the N transistor trim module is 0. The P transistor state and the P transistor trim current remain unchanged.

Claims

1. A fully common-mode range trimmable operational amplifier comprising an operational amplifier circuit and a trim circuit, characterized in that, The trimming circuit comprises: a first current source (101) having a current input end connected to VDD; a second current source (102) having a current output end connected to VSS; a third current source (103) having a current input end connected to VDD; a fourth current source (104) having a current input end connected to VDD; a fifth current source (105) having a current input end connected to VDD; a sixth current source (106) having a current input end connected to VDD; a seventh current source (107) having a current output end connected to VSS; a fifteenth NMOS transistor (M15) having a gate and a drain connected to the current output end of the third current source (103) and the current input end of the second current source (102), and a source connected to VSS; a sixteenth NMOS transistor (M16) having a gate connected to the gate of the fifteenth NMOS transistor (M15), a source connected to VSS, and a drain connected to the current output end of the fourth current source (104); a seventeenth NMOS transistor (M17) having a gate and a drain connected to the current output end of the fourth current source (104), and a source connected to VSS; an eighteenth NMOS transistor (M18) having a gate connected to the gate of the seventeenth NMOS transistor (M17), a source connected to VSS; a twenty-first PMOS transistor (M21) having a source connected to VDD, a drain connected to a gate, and a gate; a twenty-second PMOS transistor (M22) having a source connected to VDD, a gate connected to the gate of the twenty-first PMOS transistor (M21), and a drain connected to the N transistor trimming current input end of the operational amplifier circuit; a twenty-third PMOS transistor (M23) having a source connected to the current output end of the first current source (101), a drain connected to the current input end of the second current source (102), and a gate connected to the negative level input line; a twenty-fourth PMOS transistor (M24) having a source connected to the current output end of the first current source (101), a drain connected to the current input end of the second current source (102), and a gate connected to the positive level input line; a twenty-fifth NMOS transistor (M25) having a drain connected to the drain of the twenty-first PMOS transistor (M21), a source connected to the drain of the eighteenth NMOS transistor (M18), and a gate connected to the negative level input line; a twenty-sixth NMOS transistor (M26) having a drain connected to the drain of the twenty-first PMOS transistor (M21), a source connected to the drain of the eighteenth NMOS transistor (M18), and a gate connected to the positive level input line; a twenty-seventh PMOS transistor (M27) having a source connected to the current output end of the fifth current source (105), a drain connected to the P transistor trimming current input end of the operational amplifier circuit, and a gate connected to the negative level input line; a twenty-eighth PMOS transistor (M28) having a source connected to the current output end of the fifth current source (105), a drain connected to the P transistor trimming current input end of the operational amplifier circuit, and a gate connected to the positive level input line; a twenty-ninth PMOS transistor (M29) having a source connected to the current output end of the sixth current source (106), a drain connected to the current input end of the seventh current source (107), and a gate connected to the negative level input line; a thirtieth PMOS transistor (M30) having a source connected to the current output end of the sixth current source (106), a drain connected to the current input end of the seventh current source (107), and a gate connected to the positive level input line.

2. The fully common-mode range offset voltage trimming operational amplifier as claimed in claim 1, wherein, The operational amplifier circuit comprises an output stage and a trimming stage, and the trimming stage comprises: an eighth current source (108) having a current input end connected to VDD; a ninth current source (109) having a current input end connected to VDD; a nineteenth NMOS transistor (M19) having a drain and a gate connected to a current output end of the eighth current source (108) and a current input end of the seventh current source (107), and a source connected to ground; an eleventh PMOS transistor (M11) having a source connected to VDD, and a gate connected to a gate of a twenty-first PMOS transistor (M21); a first NMOS transistor (M1) having a drain connected to a drain of the eleventh PMOS transistor (M11), a gate connected to a negative level input line, a twelfth PMOS transistor (M12) having a source connected to VDD, and a gate connected to a gate of the eleventh PMOS transistor (M11); a second NMOS transistor (M2) having a drain connected to a drain of the twelfth PMOS transistor (M12), a gate connected to a positive level input line, and a source connected to a source of the first NMOS transistor (M1); a twentieth NMOS transistor (M20) having a drain connected to a source of the first NMOS transistor (M1), a source connected to ground, and a gate connected to a gate of the seventeenth NMOS transistor; a third PMOS transistor (M3) having a source connected to a current output end of the ninth current source (109), and a gate connected to the negative level input line; a fourth PMOS transistor (M4) having a source connected to the current output end of the ninth current source (109), and a gate connected to the positive level input line; a thirteenth NMOS transistor (M13) having a drain connected to a drain of the third PMOS transistor (M3), a source connected to ground, and a gate connected to a gate of the first NMOS transistor (M1); a fourteenth NMOS transistor (M14) having a drain connected to a drain of the fourth PMOS transistor (M4), a source connected to ground, and a gate connected to a gate of the thirteenth NMOS transistor (M13); a P transistor trimming module comprising a P transistor trimming current input end, a first P type current connection point of which is connected to a drain of the fourteenth NMOS transistor (M14), a first N type current connection point of which is connected to a drain of the thirteenth NMOS transistor (M13), a second P type current connection point of which is connected to a drain of the second NMOS transistor (M2), and a second N type current connection point of which is connected to a drain of the first NMOS transistor (M1); an N transistor trimming module comprising an N transistor trimming current input end, a first P type current connection point of which is connected to a drain of the fourteenth NMOS transistor (M14), a first N type current connection point of which is connected to a drain of the thirteenth NMOS transistor (M13), a second P type current connection point of which is connected to a drain of the second NMOS transistor (M2), and a second N type current connection point of which is connected to a drain of the first NMOS transistor (M1).

3. The full common mode range offset voltage trimming operational amplifier of claim 2, wherein: current values of the first current source (101), the second current source (102), and the third current source (103) are equal, and are denoted as I0; current values of the sixth current source (106), the seventh current source (107), and the eighth current source (108) are equal, and are denoted as I2; a current value of the ninth current source (109) is denoted as I3, and a current value of the fifth current source (105) is denoted as I6. The twenty-first PMOS transistor (M21) and the twenty-second PMOS transistor (M22) are identical in size; The twenty-third PMOS transistor (M23) and the twenty-fourth PMOS transistor (M24) are identical in size; The third PMOS transistor (M3) and the fourth PMOS transistor (M4) are identical in size; The twenty-seventh PMOS transistor (M27) and the twenty-eighth PMOS transistor (M28) are identical in size; The twenty-ninth PMOS transistor (M29) and the thirtieth PMOS transistor (M30) are identical in size; The twenty-fifth NMOS transistor (M25) and the twenty-sixth NMOS transistor (M26) are identical in size; The size ratio of each MOS transistor is: The fifteenth NMOS transistor (M15):the sixteenth NMOS transistor (M16)=1:m; The seventeenth NMOS transistor (M17):the eighteenth NMOS transistor (M18):the twentieth NMOS transistor (M20)=1:n:p; The twenty-first PMOS transistor (M21):the twenty-second PMOS transistor (M22):the eleventh PMOS transistor (M11):the twelfth PMOS transistor (M12)=1:1:p / (2n):p / (2n); The nineteenth NMOS transistor (M19):the thirteenth NMOS transistor (M13):the fourteenth NMOS transistor (M14)=1:q:q; The twenty-third PMOS transistor (M23):the third PMOS transistor (M3)=I0:I3; The twenty-seventh PMOS transistor (M27):the third PMOS transistor (M3)=I6:I3; The twenty-ninth PMOS transistor (M29):the third PMOS transistor (M3)=I2:I3; The twenty-fifth NMOS transistor (M25):the first NMOS transistor (M1)=n:p.

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