LVDS-Based Source Synchronization Phase Correction Method, Device, Equipment, and Medium

Abstract

The present invention discloses a source synchronous phase correction method, device, equipment and medium based on LVDS. The source synchronous phase correction method based on LVDS includes the steps of: determining the position of the current clock sampling point, if the current clock sampling point is located in the data window, moving the data in the opposite phase direction from the initial position respectively to find the boundary of the data window to determine the corresponding optimal sampling point; if the current clock sampling point is located in the transition region, moving the data in a single phase direction in turn to find the boundary of the data window to determine the corresponding optimal sampling point. The present invention can simultaneously process the random jitter and fixed jitter in the transition region, improve the accuracy of identifying the data window and the transition region, and the stability of data transmission.

Description

Technical Field

[0001] The present invention relates to the source synchronous phase correction technology of LVDS, and particularly to a source synchronous phase correction method, device, equipment and medium based on LVDS in the field of high-speed data transmission. Background Art

[0002] LVDS (Low Voltage Differential Signaling) is a serial transmission technology that uses differential signal lines to transmit data. It has characteristics such as high transmission capacity, low noise, and low electromagnetic interference, and is widely used in the field of high-speed data transmission. When transmitting data, the clock and data at the sending end are edge-aligned. During the transmission process, affected by external factors such as temperature, voltage, and transmission path, the phase relationship between the receiving end clock and data will change. Phase correction is to delay the clock or data to make the sampling point of the clock located at the center of the data window to ensure correct sampling at the receiving end.

[0003] Traditional phase correction methods use delay units to adjust the path delay of the clock or data, and identify the effective boundary of the data window by judging whether the sampled data is stable. The center of the data window is the optimal sampling point. Although the above method can achieve phase correction, it can only handle the influence of random jitter on the phase relationship and does not consider fixed jitter. When there is fixed jitter in the transition region, the sampled data is stable but incorrect, resulting in incorrect sampling at the receiving end. Summary of the Invention

[0004] The purpose of the present invention is to solve the problems in the prior art, and provide a source synchronous phase correction method, device, equipment and medium based on LVDS, aiming to reduce the influence of random jitter and fixed jitter on phase correction, and improve the accuracy of identifying the data window and the transition region; for the phase correction problem during LVDS transmission, not only judge the stability of the sampled data, but also increase the judgment of the accuracy of the sampled data, so as to reduce the influence of random jitter and fixed jitter, improve the accuracy of identifying the data window and the transition region, and the stability of data transmission.

[0005] In the first aspect of the present invention, a source synchronous phase correction method based on LVDS is provided, including the steps of:

[0006] S1: The sending end continuously sends LVDS clock and data, and the data is a fixed synchronization code; the receiving end receives the LVDS clock and data;

[0007] S2: Continuously sample the data at the current clock. Denote the sampling point corresponding to the current clock as the initial position, and determine whether the sampled data is stable: If it is not stable, it indicates that the sampling point is in the first transition region, and execute S4; if it is stable, determine whether the sampled data is the cyclic shift result of the synchronization code: If it is not, it indicates that the sampling point is in the first transition region, and execute S4; if it is, it indicates that the sampling point is in the data window, and execute S3;

[0008] S3: Move the data in the first phase direction from the initial position, and accumulate x clock phase taps until the sampled data changes; move the data in the second phase direction opposite to the first phase direction from the initial position, and accumulate y clock phase taps until the sampled data changes; calculate the first optimal sampling point position according to the clock phase taps of the two moves Move the data to the first optimal sampling point position Tap op1 ;

[0009] S4: Move the data 1 clock phase tap in the second phase direction from the initial position, continuously sample the data, and execute S5;

[0010] S5: Determine whether the sampled data is stable: If it is not stable, it indicates that the sampling point is in the first transition region, and execute S4; if it is stable, determine whether the sampled data is the cyclic shift result of the synchronization code: If it is not, it indicates that the sampling point is in the first transition region, and execute S4; if it is, it indicates that the sampling point is in the data window, and execute S6;

[0011] S6: Record the phase difference between the current sampling point and the initial position as a clock phase taps, perform bitslip processing until the sampled data is the same as the synchronization code, and execute S7;

[0012] S7: Continue to move the data 1 clock phase tap in the second phase direction, continuously sample the data, and execute S8;

[0013] S8: Determine whether the sampled data is the synchronization code: If it is, it indicates that the sampling point is in the data window, and execute S7; if it is not, it indicates that the sampling point is in the second transition region; record the phase difference between the sampling point and the initial position as b clock phase taps, and execute S9;

[0014] S9: Calculate the second optimal sampling point position according to the sampling points recorded in S6 and S8 Move the data to the second optimal sampling point position Tap op2 。

[0015] Wherein, there is a transition region between two adjacent data windows.

[0016] Wherein, the first transition region and the second transition region are adjacent transition regions.

[0017] Among them, the first phase direction is the negative phase direction, and the second phase direction is the positive phase direction.

[0018] Among them, the first phase direction is the positive phase direction, and the second phase direction is the negative phase direction.

[0019] Among them, the sending end and the receiving end are physically connected through pins.

[0020] In the second aspect of the present invention, a source synchronous phase correction device based on LVDS is provided, which is used to receive the LVDS clock and data sent externally, and when receiving the LVDS clock and data, the steps of the method for source synchronous phase correction based on LVDS are adopted to perform source synchronous phase correction.

[0021] In the third aspect of the present invention, a device is provided, including the source synchronous phase correction device based on LVDS.

[0022] In the fourth aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for source synchronous phase correction based on LVDS are realized.

[0023] In the initial phase correction stage of the present invention, by moving the data in opposite phase directions at the initial position respectively to find the boundary of the data window to determine the sampling point, the sampling point is accurately loaded to the center of the data window, which can effectively reduce the influence brought by the positive and negative phase jitters and improve the stability of data transmission.

[0024] In the first transition region of the present invention, not only is it judged whether the sampled data is stable, but also it is judged whether the sampled data is correct, which can reduce the influence brought by random jitter and fixed jitter at the same time and improve the accuracy of identifying the data window and the transition region. Description of the Drawings

[0025] Figure 1 is a schematic flow chart of the method for source synchronous phase correction based on LVDS according to an embodiment of the present invention.

[0026] Figure 2 is a schematic diagram that the sampling point is not located at the center of the data window before phase correction according to an embodiment of the present invention

[0027] Figure 3 is a schematic diagram that the sampling point is located at the center of the data window after phase correction according to an embodiment of the present invention. Detailed Embodiments

[0028] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0029] In the embodiments of the present application, by reducing the influence brought by the positive and negative phase jitters, the stability of data transmission is improved; by comparing whether the continuous sampling results are consistent, the stability of the sampling data is judged, and by comparing whether the sampling result is consistent with the synchronization code, the correctness of the sampling data is judged, thereby reducing the influence brought by the random jitter and the fixed jitter and improving the accuracy of identifying the data window and the transition region.

[0030] Reference Figure 1 A source synchronization phase correction method based on LVDS includes the steps of:

[0031] Step 1: The sending end continuously sends a fixed synchronization code, and the receiving end receives the LVDS clock and data;

[0032] Step 2: Continuously sample the data at the current clock, and mark this sampling point as the initial position. Judge whether the sampling data is stable: If it is not stable, it indicates that this sampling point is located in the first transition region, and execute Step 4; if it is stable, judge whether the sampling data is a cyclic shift result of a certain synchronization code: If it is not, it indicates that this sampling point is located in the first transition region, and execute Step 4; if it is, it indicates that this sampling point is located in the data window, and execute Step 3;

[0033] Step 3: Move the data in the negative phase direction from the initial position, and accumulate x clock phase taps until the sampling data changes; return to the initial position, move the data in the positive phase direction from the initial position, and accumulate y clock phase taps until the sampling data changes; calculate the first optimal sampling point position according to the clock phase taps of the two moves as Move the data to the first optimal sampling point position Tap op1 ;

[0034] Step 4: Move the data 1 clock phase tap in the positive phase direction from the initial position, continuously sample the data, and execute Step 5;

[0035] Step 5: Judge whether the sampling data is stable: If it is not stable, it indicates that this sampling point is located in the first transition region, and execute Step 4; if it is stable, judge whether the sampling data is a cyclic shift result of a certain synchronization code: If it is not, it indicates that this sampling point is located in the first transition region, and execute Step 4; if it is, it indicates that this sampling point is located in the data window, and execute Step 6;

[0036] Step 6: Record the phase difference of the current sampling point relative to the initial position as a clock phase tap, perform bitslip processing until the sampled data is the same as the synchronization code, and execute step 7;

[0037] Step 7: Continue to move the data in the positive phase direction by 1 clock phase tap, continuously sample the data, and execute step 8;

[0038] Step 8: Determine whether the sampled data is a synchronization code: if yes, it indicates that the sampling point is located in the data window, and execute step 7; if no, it indicates that the sampling point is located in the second transition zone; record the phase difference of the sampling point relative to the initial position as b clock phase taps, and execute step 9;

[0039] Step 9: Calculate the second best sampling point position based on the sampling points recorded in steps 6 and 8: Move data to the second best sampling point position Tap op2 .

[0040] It should be noted that in step three, when calculating the first optimal sampling point, the first optimal sampling point can be calculated by first moving in the negative phase direction and then in the positive phase direction, or by first moving in the positive phase direction and then in the negative phase direction.

[0041] It should be noted that in step 4, when the data is moved at the initial position, it can be moved to the positive phase or to the negative phase direction, without specific limitation. In step 7, when the data is moved, it can be moved to the positive phase or to the negative phase direction, without specific limitation. However, in step 4 and step 7, the data movement direction needs to be consistent.

[0042] It should be noted that the first transition zone and the second transition zone are adjacent transition zones, and there is a data window between the two adjacent transition zones. Figure 2 shown.

[0043] The embodiment of the present invention can be implemented by using Xilinx's XC7A35TFTG256 FPGA platform to perform an LVDS transceiver experiment. The transmitting end outputs LVDS clock and data, the clock frequency is 100Mhz, and the data is a fixed synchronization code (10'b0011111010). The receiving end receives the LVDS clock and data, and the transmitting end and the receiving end are physically connected through pins.

[0044] The embodiment of the present application further provides a device for source synchronous phase correction based on LVDS, which is used to receive the LVDS clock and data sent externally. When receiving the LVDS clock and data, the steps of the method for source synchronous phase correction based on LVDS are adopted to perform source synchronous phase correction. The device for source synchronous phase correction based on LVDS can be a receiving and processing device for LVDS clock and data. After receiving and processing the LVDS clock and data sent externally, the steps of the method for source synchronous phase correction based on LVDS are adopted to perform source synchronous phase correction.

[0045] The embodiment of the present application further provides a device, including the device for source synchronous phase correction based on LVDS, which receives the LVDS clock and data sent externally. When receiving the LVDS clock and data, the steps of the method for source synchronous phase correction based on LVDS are adopted to perform source synchronous phase correction.

[0046] The embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. It is characterized in that when the computer program is executed by a processor, the steps of the method for source synchronous phase correction based on LVDS are implemented.

[0047] The present invention aims at the phase correction problem in the LVDS transmission process. It not only judges the stability of the sampled data, but also adds the judgment of the accuracy of the sampled data, thereby reducing the influence brought by random jitter and fixed jitter, and improving the accuracy of identifying the data window and transition region and the stability of data transmission.

[0048] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A source-synchronous phase correction method based on LVDS, characterized in that, Including the steps: S1: The sending end continuously sends LVDS clock and data, and the data is a fixed synchronization code; the receiving end receives the LVDS clock and data. S2: Continuously sample the data at the current clock. The sampling point corresponding to the current clock is recorded as the initial position. Determine whether the sampled data is stable: If it is not stable, it indicates that the sampling point is in the first transition region, and execute S4; if it is stable, determine whether the sampled data is a cyclic shift result of the synchronization code: If it is not, it indicates that the sampling point is in the first transition region, and execute S4; if it is, it indicates that the sampling point is in the data window, and execute S3. S3: Move the data in the first phase direction from the initial position, and accumulate x clock phase taps until the sampled data changes. Move the data in the second phase direction opposite to the first phase direction from the initial position, and accumulate y clock phase taps until the sampled data changes. Calculate the first optimal sampling point position based on the clock phase taps of two moves , move the data to the first optimal sampling point position ; S4: Move the data 1 clock phase tap in the second phase direction from the initial position, continuously sample the data, and execute S5. S5: Determine whether the sampled data is stable: If it is not stable, it indicates that the sampling point is in the first transition region, and execute S4; if it is stable, determine whether the sampled data is a cyclic shift result of the synchronization code: If it is not, it indicates that the sampling point is in the first transition region, and execute S4; if it is, it indicates that the sampling point is in the data window, and execute S6. S6: Record the phase difference between the current sampling point and the initial position as a clock phase taps, perform bitslip processing until the sampled data is the same as the synchronization code, and execute S7. S7: Continue to move the data 1 clock phase tap in the second phase direction, continuously sample the data, and execute S8. S8: Determine whether the sampled data is the synchronization code: If it is, it indicates that the sampling point is in the data window, and execute S7; if it is not, it indicates that the sampling point is in the second transition region. Record the phase difference between the sampling point and the initial position as b clock phase taps, and execute S9. S9: Calculate the position of the second optimal sampling point based on the sampling points recorded in S6 and S8 , and move the data to the position of the second optimal sampling point .

2. The source-synchronous phase correction method based on LVDS according to claim 1, characterized in that, There is a transition region between two adjacent data windows.

3. The source-synchronous phase correction method based on LVDS according to claim 1, characterized in that, The first transition region and the second transition region are adjacent transition regions.

4. The source-synchronous phase correction method based on LVDS according to claim 1, characterized in that, The first phase direction is the negative phase direction, and the second phase direction is the positive phase direction.

5. The source-synchronous phase correction method based on LVDS according to claim 1, characterized in that, The first phase direction is the positive phase direction, and the second phase direction is the negative phase direction.

6. The source-synchronous phase correction method based on LVDS according to claim 1, characterized in that, The sending end and the receiving end are physically connected through pins.

7. A computer-readable storage medium, on which a computer program is stored, characterized in that, When the computer program is executed by a processor, it realizes the steps of the method for source synchronous phase correction based on LVDS described in any one of claims 1-6.

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